upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Alexey Brodkin a4a43fcf9c arc/cache: Flush & invalidate all caches right before enabling IOC ... According to ARC HS databook it is required to flush and disable caches prior programming IOC registers. Otherwise ongoing coherent memory operations may not observe the coherency protocols as expected. But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache) we're doing our best flushing and invalidating it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>		8 years ago
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arc	arc/cache: Flush & invalidate all caches right before enabling IOC	8 years ago
arm	siemens,am33x: add draco etamin board	8 years ago
avr32	…
blackfin	…
m68k	…
microblaze	Remove unneeded remnants of bcopy().	8 years ago
mips	…
nds32	…
nios2	…
openrisc	…
powerpc	Remove unneeded remnants of bcopy().	8 years ago
sandbox	dm: test: Add GPIO open drain tests	8 years ago
sh	…
sparc	…
x86	…
.gitignore	…
Kconfig	…