upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Alexey Brodkin a4a43fcf9c arc/cache: Flush & invalidate all caches right before enabling IOC ... According to ARC HS databook it is required to flush and disable caches prior programming IOC registers. Otherwise ongoing coherent memory operations may not observe the coherency protocols as expected. But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache) we're doing our best flushing and invalidating it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>		8 years ago
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cpu	…
dts	axs103: add support of generic OHCI USB 1.1 controller	9 years ago
include/asm	arc: Add virt_to_phys() stub	8 years ago
lib	arc/cache: Flush & invalidate all caches right before enabling IOC	8 years ago
Kconfig	arc: cache - accommodate different L1 cache line lengths	8 years ago
Makefile	…
config.mk	…