upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Lokesh Vutla ea8eff1fe0 arm: dra7xx: clock: Add the dplls data ... A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>		12 years ago
..
Makefile	OMAP: Tweak omap-common/Makefile since reset.S -> reset.c	12 years ago
boot-common.c	omap_hsmmc: add driver check for write protection	12 years ago
clocks-common.c	arm: dra7xx: clock: Add the dplls data	12 years ago
config.mk	arm: Remove additional config flags	12 years ago
emif-common.c	ARM: OMAP4+: Cleanup emif specific files	12 years ago
hwinit-common.c	ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup	12 years ago
lowlevel_init.S	am33xx: Fix fetching of mmc1 bootmode from bootrom for AM33XX	12 years ago
mem-common.c	…
reset.c	ARM: OMAP3+: Detect reset type	13 years ago
timer.c	arm: Move lastinc to arch_global_data	12 years ago
u-boot-spl.lds	common: Add .u_boot_list into all linker files	12 years ago
utils.c	…
vc.c	ARM: OMAP4+: Change the PRCM structure prototype common for all Socs	12 years ago