TBM/tbm-mcu
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base: TBM:6defd2365c668a9a13b6663e6049f74ce32cddda
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TBM:master
TBM:wip/virtual-tbm
TBM:0.1.0
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compare: TBM:52956ae46d1aba0bf991f2d1ef11a34a54caa5bc
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TBM:wip/virtual-tbm
TBM:master
TBM:0.1.0

3 commits
6defd2365c ... 52956ae46d

Author SHA1 Message Date
S.J.R. van Schaik
52956ae46d stm32f0: spi: divide clock rate by 2 instead of 64 2017-10-12 17:00:00 +02:00
S.J.R. van Schaik
63525ac93b stm32f1: spi: divide clock rate by 2 instead of 64 2017-10-12 16:53:12 +02:00
S.J.R. van Schaik
a53484051a stm32f1: spi: use SPI mode 0 instead of SPI mode 3 2017-10-10 18:20:32 +02:00
2 changed files with 4 additions and 4 deletions
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2
source/platform/stm32f0/spi.c
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@ -18,7 +18,7 @@ static struct spi_ops stm32f0_spi_ops = {
static void stm32f0_spi_init(void)
{
spi_set_master_mode(SPI1);
spi_set_baudrate_prescaler(SPI1, SPI_CR1_BR_FPCLK_DIV_64);
spi_set_baudrate_prescaler(SPI1, SPI_CR1_BR_FPCLK_DIV_2);
spi_set_clock_polarity_0(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_full_duplex_mode(SPI1);

6
source/platform/stm32f1/spi.c
View file

@ -19,9 +19,9 @@ static void stm32f1_spi_init(void)
{
spi_reset(SPI1);
spi_init_master(SPI1,
SPI_CR1_BAUDRATE_FPCLK_DIV_64,
SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_2,
SPI_CR1_BAUDRATE_FPCLK_DIV_2,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
spi_enable_software_slave_management(SPI1);