upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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296 lines
7.4 KiB
296 lines
7.4 KiB
14 years ago
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/*
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* (C) Copyright 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __MACH_MX35_IOMUX_H__
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#define __MACH_MX35_IOMUX_H__
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#include <asm/arch/imx-regs.h>
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/*
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* various IOMUX functions
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*/
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typedef enum iomux_pin_config {
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MUX_CONFIG_FUNC = 0, /* used as function */
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MUX_CONFIG_ALT1, /* used as alternate function 1 */
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MUX_CONFIG_ALT2, /* used as alternate function 2 */
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MUX_CONFIG_ALT3, /* used as alternate function 3 */
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MUX_CONFIG_ALT4, /* used as alternate function 4 */
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MUX_CONFIG_ALT5, /* used as alternate function 5 */
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MUX_CONFIG_ALT6, /* used as alternate function 6 */
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MUX_CONFIG_ALT7, /* used as alternate function 7 */
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MUX_CONFIG_SION = 0x1 << 4, /* used as LOOPBACK:MUX SION bit */
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MUX_CONFIG_GPIO = MUX_CONFIG_ALT5, /* used as GPIO */
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} iomux_pin_cfg_t;
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/*
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* various IOMUX pad functions
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*/
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typedef enum iomux_pad_config {
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PAD_CTL_DRV_3_3V = 0x0 << 13,
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PAD_CTL_DRV_1_8V = 0x1 << 13,
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PAD_CTL_HYS_CMOS = 0x0 << 8,
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PAD_CTL_HYS_SCHMITZ = 0x1 << 8,
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PAD_CTL_PKE_NONE = 0x0 << 7,
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PAD_CTL_PKE_ENABLE = 0x1 << 7,
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PAD_CTL_PUE_KEEPER = 0x0 << 6,
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PAD_CTL_PUE_PUD = 0x1 << 6,
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PAD_CTL_100K_PD = 0x0 << 4,
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PAD_CTL_47K_PU = 0x1 << 4,
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PAD_CTL_100K_PU = 0x2 << 4,
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PAD_CTL_22K_PU = 0x3 << 4,
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PAD_CTL_ODE_CMOS = 0x0 << 3,
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PAD_CTL_ODE_OpenDrain = 0x1 << 3,
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PAD_CTL_DRV_NORMAL = 0x0 << 1,
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PAD_CTL_DRV_HIGH = 0x1 << 1,
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PAD_CTL_DRV_MAX = 0x2 << 1,
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PAD_CTL_SRE_SLOW = 0x0 << 0,
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PAD_CTL_SRE_FAST = 0x1 << 0
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} iomux_pad_config_t;
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/*
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* various IOMUX general purpose functions
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*/
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typedef enum iomux_gp_func {
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MUX_SDCTL_CSD0_SEL = 0x1 << 0,
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MUX_SDCTL_CSD1_SEL = 0x1 << 1,
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MUX_TAMPER_DETECT_EN = 0x1 << 2,
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} iomux_gp_func_t;
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/*
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* various IOMUX input select register index
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*/
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typedef enum iomux_input_select {
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MUX_IN_AMX_P5_RXCLK = 0,
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MUX_IN_AMX_P5_RXFS,
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MUX_IN_AMX_P6_DA,
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MUX_IN_AMX_P6_DB,
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MUX_IN_AMX_P6_RXCLK,
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MUX_IN_AMX_P6_RXFS,
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MUX_IN_AMX_P6_TXCLK,
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MUX_IN_AMX_P6_TXFS,
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MUX_IN_CAN1_CANRX,
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MUX_IN_CAN2_CANRX,
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MUX_IN_CCM_32K_MUXED,
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MUX_IN_CCM_PMIC_RDY,
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MUX_IN_CSPI1_SS2_B,
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MUX_IN_CSPI1_SS3_B,
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MUX_IN_CSPI2_CLK_IN,
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MUX_IN_CSPI2_DATAREADY_B,
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MUX_IN_CSPI2_MISO,
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MUX_IN_CSPI2_MOSI,
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MUX_IN_CSPI2_SS0_B,
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MUX_IN_CSPI2_SS1_B,
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MUX_IN_CSPI2_SS2_B,
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MUX_IN_CSPI2_SS3_B,
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MUX_IN_EMI_WEIM_DTACK_B,
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MUX_IN_ESDHC1_DAT4_IN,
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MUX_IN_ESDHC1_DAT5_IN,
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MUX_IN_ESDHC1_DAT6_IN,
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MUX_IN_ESDHC1_DAT7_IN,
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MUX_IN_ESDHC3_CARD_CLK_IN,
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MUX_IN_ESDHC3_CMD_IN,
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MUX_IN_ESDHC3_DAT0,
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MUX_IN_ESDHC3_DAT1,
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MUX_IN_ESDHC3_DAT2,
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MUX_IN_ESDHC3_DAT3,
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MUX_IN_GPIO1_IN_0,
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MUX_IN_GPIO1_IN_10,
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MUX_IN_GPIO1_IN_11,
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MUX_IN_GPIO1_IN_1,
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MUX_IN_GPIO1_IN_20,
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MUX_IN_GPIO1_IN_21,
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MUX_IN_GPIO1_IN_22,
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MUX_IN_GPIO1_IN_2,
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MUX_IN_GPIO1_IN_3,
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MUX_IN_GPIO1_IN_4,
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MUX_IN_GPIO1_IN_5,
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MUX_IN_GPIO1_IN_6,
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MUX_IN_GPIO1_IN_7,
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MUX_IN_GPIO1_IN_8,
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MUX_IN_GPIO1_IN_9,
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MUX_IN_GPIO2_IN_0,
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MUX_IN_GPIO2_IN_10,
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MUX_IN_GPIO2_IN_11,
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MUX_IN_GPIO2_IN_12,
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MUX_IN_GPIO2_IN_13,
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MUX_IN_GPIO2_IN_14,
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MUX_IN_GPIO2_IN_15,
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MUX_IN_GPIO2_IN_16,
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MUX_IN_GPIO2_IN_17,
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MUX_IN_GPIO2_IN_18,
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MUX_IN_GPIO2_IN_19,
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MUX_IN_GPIO2_IN_20,
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MUX_IN_GPIO2_IN_21,
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MUX_IN_GPIO2_IN_22,
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MUX_IN_GPIO2_IN_23,
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MUX_IN_GPIO2_IN_24,
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MUX_IN_GPIO2_IN_25,
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MUX_IN_GPIO2_IN_26,
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MUX_IN_GPIO2_IN_27,
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MUX_IN_GPIO2_IN_28,
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MUX_IN_GPIO2_IN_29,
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MUX_IN_GPIO2_IN_2,
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MUX_IN_GPIO2_IN_30,
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MUX_IN_GPIO2_IN_31,
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MUX_IN_GPIO2_IN_3,
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MUX_IN_GPIO2_IN_4,
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MUX_IN_GPIO2_IN_5,
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MUX_IN_GPIO2_IN_6,
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MUX_IN_GPIO2_IN_7,
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MUX_IN_GPIO2_IN_8,
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MUX_IN_GPIO2_IN_9,
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MUX_IN_GPIO3_IN_0,
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MUX_IN_GPIO3_IN_10,
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MUX_IN_GPIO3_IN_11,
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MUX_IN_GPIO3_IN_12,
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MUX_IN_GPIO3_IN_13,
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MUX_IN_GPIO3_IN_14,
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MUX_IN_GPIO3_IN_15,
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MUX_IN_GPIO3_IN_4,
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MUX_IN_GPIO3_IN_5,
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MUX_IN_GPIO3_IN_6,
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MUX_IN_GPIO3_IN_7,
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MUX_IN_GPIO3_IN_8,
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MUX_IN_GPIO3_IN_9,
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MUX_IN_I2C3_SCL_IN,
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MUX_IN_I2C3_SDA_IN,
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MUX_IN_IPU_DISPB_D0_VSYNC,
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MUX_IN_IPU_DISPB_D12_VSYNC,
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MUX_IN_IPU_DISPB_SD_D,
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MUX_IN_IPU_SENSB_DATA_0,
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MUX_IN_IPU_SENSB_DATA_1,
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MUX_IN_IPU_SENSB_DATA_2,
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MUX_IN_IPU_SENSB_DATA_3,
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MUX_IN_IPU_SENSB_DATA_4,
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MUX_IN_IPU_SENSB_DATA_5,
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MUX_IN_IPU_SENSB_DATA_6,
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MUX_IN_IPU_SENSB_DATA_7,
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MUX_IN_KPP_COL_0,
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MUX_IN_KPP_COL_1,
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MUX_IN_KPP_COL_2,
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MUX_IN_KPP_COL_3,
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MUX_IN_KPP_COL_4,
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MUX_IN_KPP_COL_5,
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MUX_IN_KPP_COL_6,
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MUX_IN_KPP_COL_7,
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MUX_IN_KPP_ROW_0,
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MUX_IN_KPP_ROW_1,
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MUX_IN_KPP_ROW_2,
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MUX_IN_KPP_ROW_3,
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MUX_IN_KPP_ROW_4,
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MUX_IN_KPP_ROW_5,
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MUX_IN_KPP_ROW_6,
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MUX_IN_KPP_ROW_7,
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MUX_IN_OWIRE_BATTERY_LINE,
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MUX_IN_SPDIF_HCKT_CLK2,
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MUX_IN_SPDIF_SPDIF_IN1,
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MUX_IN_UART3_UART_RTS_B,
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MUX_IN_UART3_UART_RXD_MUX,
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MUX_IN_USB_OTG_DATA_0,
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MUX_IN_USB_OTG_DATA_1,
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MUX_IN_USB_OTG_DATA_2,
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MUX_IN_USB_OTG_DATA_3,
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MUX_IN_USB_OTG_DATA_4,
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MUX_IN_USB_OTG_DATA_5,
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MUX_IN_USB_OTG_DATA_6,
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MUX_IN_USB_OTG_DATA_7,
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MUX_IN_USB_OTG_DIR,
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MUX_IN_USB_OTG_NXT,
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MUX_IN_USB_UH2_DATA_0,
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MUX_IN_USB_UH2_DATA_1,
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MUX_IN_USB_UH2_DATA_2,
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MUX_IN_USB_UH2_DATA_3,
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MUX_IN_USB_UH2_DATA_4,
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MUX_IN_USB_UH2_DATA_5,
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MUX_IN_USB_UH2_DATA_6,
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MUX_IN_USB_UH2_DATA_7,
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MUX_IN_USB_UH2_DIR,
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MUX_IN_USB_UH2_NXT,
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MUX_IN_USB_UH2_USB_OC,
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} iomux_input_select_t;
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/*
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* various IOMUX input functions
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*/
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typedef enum iomux_input_config {
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INPUT_CTL_PATH0 = 0x0,
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INPUT_CTL_PATH1,
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INPUT_CTL_PATH2,
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INPUT_CTL_PATH3,
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INPUT_CTL_PATH4,
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INPUT_CTL_PATH5,
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INPUT_CTL_PATH6,
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INPUT_CTL_PATH7,
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} iomux_input_cfg_t;
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/*
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* Request ownership for an IO pin. This function has to be the first one
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* being called before that pin is used. The caller has to check the
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* return value to make sure it returns 0.
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*
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* @param pin a name defined by iomux_pin_name_t
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* @param cfg an input function as defined in iomux_pin_cfg_t
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*
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* @return 0 if successful; Non-zero otherwise
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*/
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void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
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/*
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* Release ownership for an IO pin
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*
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* @param pin a name defined by iomux_pin_name_t
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* @param cfg an input function as defined in iomux_pin_cfg_t
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*/
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void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg);
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/*
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* This function enables/disables the general purpose function for a particular
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* signal.
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*
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* @param gp one signal as defined in iomux_gp_func_t
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* @param en 1 to enable; 0 to disable
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*/
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void mxc_iomux_set_gpr(iomux_gp_func_t gp, int en);
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/*
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* This function configures the pad value for a IOMUX pin.
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*
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* @param pin a pin number as defined in iomux_pin_name_t
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* @param config the ORed value of elements defined in
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* iomux_pad_config_t
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*/
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void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
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/*
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* This function configures input path.
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*
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* @param input index of input select register as defined in
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* iomux_input_select_t
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* @param config the binary value of elements defined in
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* iomux_input_cfg_t
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*/
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void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
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#endif
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