upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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234 lines
7.7 KiB
234 lines
7.7 KiB
16 years ago
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/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation's version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef MMC_H
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#define MMC_H
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15 years ago
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#include <asm/arch/mmc_host_def.h>
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16 years ago
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/* Responses */
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#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
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#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
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#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK)
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#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK)
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#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
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#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK)
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#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
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#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
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#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK)
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/* All supported commands */
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#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
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#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
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#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE)
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#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ)
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#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE)
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#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16)
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#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16)
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#define MMC_DSR_DEFAULT 0x0404
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#define SD_CMD8_CHECK_PATTERN 0xAA
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#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8)
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/* Clock Configurations and Macros */
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#define MMC_CLOCK_REFERENCE 96
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#define MMC_RELATIVE_CARD_ADDRESS 0x1234
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#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80)
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#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400)
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#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1)
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#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u))
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#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29)
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#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29)
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#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29)
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#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30)
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#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30)
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#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30)
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#define MMC_SD2_CSD_C_SIZE_LSB_MASK 0xFFFF
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#define MMC_SD2_CSD_C_SIZE_MSB_MASK 0x003F
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#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET 16
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#define MMC_CSD_C_SIZE_LSB_MASK 0x0003
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#define MMC_CSD_C_SIZE_MSB_MASK 0x03FF
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#define MMC_CSD_C_SIZE_MSB_OFFSET 2
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#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0)
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#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3)
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#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0)
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#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3)
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#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3)
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typedef struct {
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unsigned not_used:1;
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unsigned crc:7;
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unsigned ecc:2;
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unsigned file_format:2;
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unsigned tmp_write_protect:1;
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unsigned perm_write_protect:1;
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unsigned copy:1;
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unsigned file_format_grp:1;
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unsigned content_prot_app:1;
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unsigned reserved_1:4;
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unsigned write_bl_partial:1;
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unsigned write_bl_len:4;
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unsigned r2w_factor:3;
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unsigned default_ecc:2;
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unsigned wp_grp_enable:1;
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unsigned wp_grp_size:5;
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unsigned erase_grp_mult:5;
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unsigned erase_grp_size:5;
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unsigned c_size_mult:3;
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unsigned vdd_w_curr_max:3;
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unsigned vdd_w_curr_min:3;
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unsigned vdd_r_curr_max:3;
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unsigned vdd_r_curr_min:3;
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unsigned c_size_lsb:2;
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unsigned c_size_msb:10;
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unsigned reserved_2:2;
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unsigned dsr_imp:1;
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unsigned read_blk_misalign:1;
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unsigned write_blk_misalign:1;
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unsigned read_bl_partial:1;
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unsigned read_bl_len:4;
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unsigned ccc:12;
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unsigned tran_speed:8;
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unsigned nsac:8;
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unsigned taac:8;
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unsigned reserved_3:2;
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unsigned spec_vers:4;
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unsigned csd_structure:2;
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} mmc_csd_reg_t;
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/* csd for sd2.0 */
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typedef struct {
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unsigned not_used:1;
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unsigned crc:7;
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unsigned reserved_1:2;
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unsigned file_format:2;
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unsigned tmp_write_protect:1;
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unsigned perm_write_protect:1;
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unsigned copy:1;
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unsigned file_format_grp:1;
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unsigned reserved_2:5;
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unsigned write_bl_partial:1;
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unsigned write_bl_len:4;
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unsigned r2w_factor:3;
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unsigned reserved_3:2;
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unsigned wp_grp_enable:1;
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unsigned wp_grp_size:7;
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unsigned sector_size:7;
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unsigned erase_blk_len:1;
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unsigned reserved_4:1;
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unsigned c_size_lsb:16;
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unsigned c_size_msb:6;
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unsigned reserved_5:6;
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unsigned dsr_imp:1;
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unsigned read_blk_misalign:1;
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unsigned write_blk_misalign:1;
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unsigned read_bl_partial:1;
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unsigned read_bl_len:4;
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unsigned ccc:12;
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unsigned tran_speed:8;
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unsigned nsac:8;
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unsigned taac:8;
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unsigned reserved_6:6;
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unsigned csd_structure:2;
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} mmc_sd2_csd_reg_t;
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/* extended csd - 512 bytes long */
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typedef struct {
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unsigned char reserved_1[181];
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unsigned char erasedmemorycontent;
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unsigned char reserved_2;
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unsigned char buswidthmode;
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unsigned char reserved_3;
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unsigned char highspeedinterfacetiming;
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unsigned char reserved_4;
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unsigned char powerclass;
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unsigned char reserved_5;
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unsigned char commandsetrevision;
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unsigned char reserved_6;
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unsigned char commandset;
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unsigned char extendedcsdrevision;
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unsigned char reserved_7;
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unsigned char csdstructureversion;
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unsigned char reserved_8;
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unsigned char cardtype;
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unsigned char reserved_9[3];
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unsigned char powerclass_52mhz_1_95v;
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unsigned char powerclass_26mhz_1_95v;
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unsigned char powerclass_52mhz_3_6v;
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unsigned char powerclass_26mhz_3_6v;
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unsigned char reserved_10;
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unsigned char minreadperf_4b_26mhz;
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unsigned char minwriteperf_4b_26mhz;
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unsigned char minreadperf_8b_26mhz_4b_52mhz;
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unsigned char minwriteperf_8b_26mhz_4b_52mhz;
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unsigned char minreadperf_8b_52mhz;
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unsigned char minwriteperf_8b_52mhz;
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unsigned char reserved_11;
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unsigned int sectorcount;
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unsigned char reserved_12[288];
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unsigned char supportedcommandsets;
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unsigned char reserved_13[7];
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} mmc_extended_csd_reg_t;
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/* mmc sd responce */
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typedef struct {
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unsigned int ocr;
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} mmc_resp_r3;
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typedef struct {
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unsigned short cardstatus;
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unsigned short newpublishedrca;
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} mmc_resp_r6;
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15 years ago
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typedef union {
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unsigned int resp[4];
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mmc_resp_r3 r3;
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mmc_resp_r6 r6;
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mmc_csd_reg_t Card_CSD;
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} mmc_resp_t;
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16 years ago
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#endif /* MMC_H */
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