upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
2.1 KiB
61 lines
2.1 KiB
10 years ago
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/*
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* Copyright (C) 2013 Boundary Devices
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* ZQ Calibration */
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DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
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DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
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DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
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DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
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DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
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/*
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* DQS gating, read delay, write delay calibration values
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*/
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DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217
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DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B
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DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B
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DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C
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DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C
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DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48
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DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40
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DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E
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/* read data bit delay */
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DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
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DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
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/* Complete calibration by forced measurment */
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DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
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DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
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/* in DDR3, 64-bit mode, only MMDC0 is initiated */
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025
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DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
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DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313
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DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63
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DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
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DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
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DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
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DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023
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DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
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DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
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DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
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DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
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/* final ddr setup */
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DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
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DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
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DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
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DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565
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DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
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DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
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