upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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116 lines
3.1 KiB
116 lines
3.1 KiB
16 years ago
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/*
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* Pulse Width Modulation Memory Map
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*
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ATA_H__
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#define __ATA_H__
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/* Pulse Width Modulation (PWM) */
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typedef struct pwm_ctrl {
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#ifdef CONFIG_M5272
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u8 cr0;
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u8 res1[3];
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u8 cr1;
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u8 res2[3];
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u8 cr2;
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u8 res3[7];
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u8 pwr0;
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u8 res4[3];
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u8 pwr1;
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u8 res5[3];
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u8 pwr2;
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u8 res6[7];
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#else
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u8 en; /* 0x00 PWM Enable */
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u8 pol; /* 0x01 Polarity */
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u8 clk; /* 0x02 Clock Select */
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u8 prclk; /* 0x03 Prescale Clock Select */
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u8 cae; /* 0x04 Center Align Enable */
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u8 ctl; /* 0x05 Control */
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u16 res1; /* 0x06 - 0x07 */
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u8 scla; /* 0x08 Scale A */
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u8 sclb; /* 0x09 Scale B */
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u16 res2; /* 0x0A - 0x0B */
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#ifdef CONFIG_M5275
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u8 cnt[4]; /* 0x0C Channel n Counter */
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u16 res3; /* 0x10 - 0x11 */
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u8 per[4]; /* 0x14 Channel n Period */
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u16 res4; /* 0x16 - 0x17 */
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u8 dty[4]; /* 0x18 Channel n Duty */
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#else
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u8 cnt[8]; /* 0x0C Channel n Counter */
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u8 per[8]; /* 0x14 Channel n Period */
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u8 dty[8]; /* 0x1C Channel n Duty */
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u8 sdn; /* 0x24 Shutdown */
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u8 res3[3]; /* 0x25 - 0x27 */
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#endif /* CONFIG_M5275 */
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#endif /* CONFIG_M5272 */
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} pwm_t;
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#ifdef CONFIG_M5272
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#define PWM_CR_EN (0x80)
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#define PWM_CR_FRC1 (0x40)
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#define PWM_CR_LVL (0x20)
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#define PWM_CR_CLKSEL(x) ((x) & 0x0F)
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#define PWM_CR_CLKSEL_MASK (0xF0)
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#else
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#define PWM_EN_PWMEn(x) (1 << ((x) & 0x07))
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#define PWM_EN_PWMEn_MASK (0xF0)
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#define PWM_POL_PPOLn(x) (1 << ((x) & 0x07))
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#define PWM_POL_PPOLn_MASK (0xF0)
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#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
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#define PWM_CLK_PCLKn_MASK (0xF0)
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#define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4)
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#define PWM_PRCLK_PCKB_MASK (0x8F)
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#define PWM_PRCLK_PCKA(x) ((x) & 0x07)
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#define PWM_PRCLK_PCKA_MASK (0xF8)
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#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07))
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#define PWM_CLK_PCLKn_MASK (0xF0)
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#define PWM_CTL_CON67 (0x80)
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#define PWM_CTL_CON45 (0x40)
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#define PWM_CTL_CON23 (0x20)
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#define PWM_CTL_CON01 (0x10)
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#define PWM_CTL_PSWAR (0x08)
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#define PWM_CTL_PFRZ (0x04)
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#define PWM_SDN_IF (0x80)
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#define PWM_SDN_IE (0x40)
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#define PWM_SDN_RESTART (0x20)
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#define PWM_SDN_LVL (0x10)
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#define PWM_SDN_PWM7IN (0x04)
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#define PWM_SDN_PWM7IL (0x02)
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#define PWM_SDN_SDNEN (0x01)
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#endif /* CONFIG_M5272 */
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#endif /* __ATA_H__ */
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