upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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112 lines
3.2 KiB
112 lines
3.2 KiB
16 years ago
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/*
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* Queue Serial Peripheral Interface Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __QSPI_H__
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#define __QSPI_H__
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/* QSPI module registers */
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typedef struct qspi_ctrl {
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u16 mr; /* 0x00 Mode */
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u16 res1;
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u16 dlyr; /* 0x04 Delay */
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u16 res2;
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u16 wr; /* 0x08 Wrap */
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u16 res3;
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u16 ir; /* 0x0C Interrupt */
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u16 res4;
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u16 ar; /* 0x10 Address */
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u16 res5;
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u16 dr; /* 0x14 Data */
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u16 res6;
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} qspi_t;
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/* MR */
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#define QSPI_QMR_MSTR (0x8000)
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#define QSPI_QMR_DOHIE (0x4000)
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#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
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#define QSPI_QMR_BITS_MASK (0xC3FF)
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#define QSPI_QMR_BITS_8 (0x2000)
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#define QSPI_QMR_BITS_9 (0x2400)
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#define QSPI_QMR_BITS_10 (0x2800)
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#define QSPI_QMR_BITS_11 (0x2C00)
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#define QSPI_QMR_BITS_12 (0x3000)
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#define QSPI_QMR_BITS_13 (0x3400)
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#define QSPI_QMR_BITS_14 (0x3800)
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#define QSPI_QMR_BITS_15 (0x3C00)
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#define QSPI_QMR_BITS_16 (0x0000)
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#define QSPI_QMR_CPOL (0x0200)
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#define QSPI_QMR_CPHA (0x0100)
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#define QSPI_QMR_BAUD(x) ((x)&0x00FF)
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#define QSPI_QMR_BAUD_MASK (0xFF00)
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/* DLYR */
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#define QSPI_QDLYR_SPE (0x8000)
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#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
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#define QSPI_QDLYR_QCD_MASK (0x80FF)
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#define QSPI_QDLYR_DTL(x) ((x)&0x00FF)
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#define QSPI_QDLYR_DTL_MASK (0xFF00)
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/* WR */
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#define QSPI_QWR_HALT (0x8000)
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#define QSPI_QWR_WREN (0x4000)
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#define QSPI_QWR_WRTO (0x2000)
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#define QSPI_QWR_CSIV (0x1000)
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#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
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#define QSPI_QWR_ENDQP_MASK (0xF0FF)
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#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
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#define QSPI_QWR_CPTQP_MASK (0xFF0F)
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#define QSPI_QWR_NEWQP(x) ((x)&0x000F)
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#define QSPI_QWR_NEWQP_MASK (0xFFF0)
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/* IR */
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#define QSPI_QIR_WCEFB (0x8000)
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#define QSPI_QIR_ABRTB (0x4000)
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#define QSPI_QIR_ABRTL (0x1000)
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#define QSPI_QIR_WCEFE (0x0800)
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#define QSPI_QIR_ABRTE (0x0400)
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#define QSPI_QIR_SPIFE (0x0100)
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#define QSPI_QIR_WCEF (0x0008)
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#define QSPI_QIR_ABRT (0x0004)
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#define QSPI_QIR_SPIF (0x0001)
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/* AR */
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#define QSPI_QAR_ADDR(x) ((x)&0x003F)
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#define QSPI_QAR_ADDR_MASK (0xFFC0)
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#define QSPI_QAR_TRANS (0x0000)
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#define QSPI_QAR_RECV (0x0010)
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#define QSPI_QAR_CMD (0x0020)
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/* DR */
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#define QSPI_QDR_CONT (0x8000)
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#define QSPI_QDR_BITSE (0x4000)
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#define QSPI_QDR_DT (0x2000)
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#define QSPI_QDR_DSCK (0x1000)
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#define QSPI_QDR_QSPI_CS3 (0x0800)
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#define QSPI_QDR_QSPI_CS2 (0x0400)
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#define QSPI_QDR_QSPI_CS1 (0x0200)
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#define QSPI_QDR_QSPI_CS0 (0x0100)
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#endif /* __QSPI_H__ */
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