upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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68 lines
2.7 KiB
68 lines
2.7 KiB
19 years ago
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/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2006
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* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
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* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*----------------------------------------------------------------------------+
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| EBC Configuration Register - EBC0_CFG
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+----------------------------------------------------------------------------*/
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/* External Bus Three-State Control */
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#define EBC0_CFG_EBTC_DRIVEN 0x80000000
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/* Device-Paced Time-out Disable */
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#define EBC0_CFG_PTD_ENABLED 0x00000000
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/* Ready Timeout Count */
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#define EBC0_CFG_RTC_MASK 0x38000000
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#define EBC0_CFG_RTC_16PERCLK 0x00000000
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#define EBC0_CFG_RTC_32PERCLK 0x08000000
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#define EBC0_CFG_RTC_64PERCLK 0x10000000
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#define EBC0_CFG_RTC_128PERCLK 0x18000000
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#define EBC0_CFG_RTC_256PERCLK 0x20000000
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#define EBC0_CFG_RTC_512PERCLK 0x28000000
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#define EBC0_CFG_RTC_1024PERCLK 0x30000000
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#define EBC0_CFG_RTC_2048PERCLK 0x38000000
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/* External Master Priority Low */
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#define EBC0_CFG_EMPL_LOW 0x00000000
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#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
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#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
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#define EBC0_CFG_EMPL_HIGH 0x06000000
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/* External Master Priority High */
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#define EBC0_CFG_EMPH_LOW 0x00000000
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#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
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#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
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#define EBC0_CFG_EMPH_HIGH 0x01800000
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/* Chip Select Three-State Control */
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#define EBC0_CFG_CSTC_DRIVEN 0x00400000
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/* Burst Prefetch */
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#define EBC0_CFG_BPF_ONEDW 0x00000000
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#define EBC0_CFG_BPF_TWODW 0x00100000
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#define EBC0_CFG_BPF_FOURDW 0x00200000
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/* External Master Size */
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#define EBC0_CFG_EMS_8BIT 0x00000000
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/* Power Management Enable */
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#define EBC0_CFG_PME_DISABLED 0x00000000
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#define EBC0_CFG_PME_ENABLED 0x00020000
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/* Power Management Timer */
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#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
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#define SDR0_USB0 0x0320 /* USB Control Register */
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