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upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/configs/LicheePi_Zero_defconfig

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sunxi: add support for Lichee Pi Zero Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
8 years ago
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
CONFIG_SPL=y
sunxi: add support for Lichee Pi Zero Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
8 years ago
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=14779
configs: Migrate CONFIG_NR_DRAM_BANKS We have the following cases: - CONFIG_NR_DRAM_BANKS was defined, migrate normally - CONFIG_NR_DRAM_BANKS_MAX was defined and then used for CONFIG_NR_DRAM_BANKS after a check, just migrate it over now. - CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 + 2), set this to 8. Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago
CONFIG_NR_DRAM_BANKS=1
sunxi: add support for Lichee Pi Zero Lichee Pi Zero is a development board with a V3s SoC, which features 64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not soldered in production batch), a 40-pin RGB LCD connector and some extra pins available as 2.54mm pins or stamp holes. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
8 years ago
# CONFIG_CMD_FLASH is not set
sunxi: defaultly enable SPL for Lichee Pi Zero As we have already DRAM initialization code for V3s SoC, we can defaultly enable SPL now on Lichee Pi Zero. Add CONFIG_SPL in Lichee Pi Zero defconfig. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years ago
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
6 years ago
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero"
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
7 years ago
# CONFIG_NETDEVICES is not set
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y