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/*
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* Copyright 2007 (C)
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* Copyright 2008 (C)
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* Mark Jonas <mark.jonas@de.bosch.com>
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*
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* SH7720 Internal I/O register
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_CPU_SH7720_H_
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#define _ASM_CPU_SH7720_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000000B
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/* EXP */
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#define TRA 0xFFFFFFD0
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#define EXPEVT 0xFFFFFFD4
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#define INTEVT 0xFFFFFFD8
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/* MMU */
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#define MMUCR 0xFFFFFFE0
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#define PTEH 0xFFFFFFF0
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#define PTEL 0xFFFFFFF4
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#define TTB 0xFFFFFFF8
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/* CACHE */
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#define CCR 0xFFFFFFEC
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/* INTC */
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#define IPRF 0xA4080000
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#define IPRG 0xA4080002
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#define IPRH 0xA4080004
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#define IPRI 0xA4080006
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#define IPRJ 0xA4080008
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#define IRR5 0xA4080020
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#define IRR6 0xA4080022
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#define IRR7 0xA4080024
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#define IRR8 0xA4080026
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#define IRR9 0xA4080028
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#define IRR0 0xA4140004
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#define IRR1 0xA4140006
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#define IRR2 0xA4140008
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#define IRR3 0xA414000A
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#define IRR4 0xA414000C
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#define ICR1 0xA4140010
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#define ICR2 0xA4140012
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#define PINTER 0xA4140014
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#define IPRC 0xA4140016
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#define IPRD 0xA4140018
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#define IPRE 0xA414001A
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#define ICR0 0xA414FEE0
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#define IPRA 0xA414FEE2
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#define IPRB 0xA414FEE4
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/* BSC */
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#define BSC_BASE 0xA4FD0000
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#define CMNCR (BSC_BASE + 0x00)
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#define CS0BCR (BSC_BASE + 0x04)
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#define CS2BCR (BSC_BASE + 0x08)
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#define CS3BCR (BSC_BASE + 0x0C)
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#define CS4BCR (BSC_BASE + 0x10)
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#define CS5ABCR (BSC_BASE + 0x14)
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#define CS5BBCR (BSC_BASE + 0x18)
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#define CS6ABCR (BSC_BASE + 0x1C)
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#define CS6BBCR (BSC_BASE + 0x20)
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#define CS0WCR (BSC_BASE + 0x24)
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#define CS2WCR (BSC_BASE + 0x28)
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#define CS3WCR (BSC_BASE + 0x2C)
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#define CS4WCR (BSC_BASE + 0x30)
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#define CS5AWCR (BSC_BASE + 0x34)
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#define CS5BWCR (BSC_BASE + 0x38)
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#define CS6AWCR (BSC_BASE + 0x3C)
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#define CS6BWCR (BSC_BASE + 0x40)
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#define SDCR (BSC_BASE + 0x44)
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#define RTCSR (BSC_BASE + 0x48)
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#define RTCNR (BSC_BASE + 0x4C)
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#define RTCOR (BSC_BASE + 0x50)
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#define SDMR2 (BSC_BASE + 0x4000)
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#define SDMR3 (BSC_BASE + 0x5000)
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/* DMAC */
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/* CPG */
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#define UCLKCR 0xA40A0008
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#define FRQCR 0xA415FF80
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/* LOW POWER MODE */
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/* TMU */
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#define TMU_BASE 0xA412FE90
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#define TSTR (TMU_BASE + 0x02)
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#define TCOR0 (TMU_BASE + 0x04)
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#define TCNT0 (TMU_BASE + 0x08)
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#define TCR0 (TMU_BASE + 0x0C)
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#define TCOR1 (TMU_BASE + 0x10)
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#define TCNT1 (TMU_BASE + 0x14)
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#define TCR1 (TMU_BASE + 0x18)
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#define TCOR2 (TMU_BASE + 0x1C)
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#define TCNT2 (TMU_BASE + 0x20)
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#define TCR2 (TMU_BASE + 0x24)
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/* TPU */
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#define TPU_BASE 0xA4480000
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#define TPU_TSTR (TPU_BASE + 0x00)
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#define TPU_TCR0 (TPU_BASE + 0x10)
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#define TPU_TMDR0 (TPU_BASE + 0x14)
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#define TPU_TIOR0 (TPU_BASE + 0x18)
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#define TPU_TIER0 (TPU_BASE + 0x1C)
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#define TPU_TSR0 (TPU_BASE + 0x20)
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#define TPU_TCNT0 (TPU_BASE + 0x24)
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#define TPU_TGRA0 (TPU_BASE + 0x28)
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#define TPU_TGRB0 (TPU_BASE + 0x2C)
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#define TPU_TGRC0 (TPU_BASE + 0x30)
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#define TPU_TGRD0 (TPU_BASE + 0x34)
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#define TPU_TCR1 (TPU_BASE + 0x50)
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#define TPU_TMDR1 (TPU_BASE + 0x54)
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#define TPU_TIOR1 (TPU_BASE + 0x58)
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#define TPU_TIER1 (TPU_BASE + 0x5C)
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#define TPU_TSR1 (TPU_BASE + 0x60)
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#define TPU_TCNT1 (TPU_BASE + 0x64)
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#define TPU_TGRA1 (TPU_BASE + 0x68)
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#define TPU_TGRB1 (TPU_BASE + 0x6C)
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#define TPU_TGRC1 (TPU_BASE + 0x70)
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#define TPU_TGRD1 (TPU_BASE + 0x74)
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#define TPU_TCR2 (TPU_BASE + 0x90)
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#define TPU_TMDR2 (TPU_BASE + 0x94)
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#define TPU_TIOR2 (TPU_BASE + 0x98)
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#define TPU_TIER2 (TPU_BASE + 0x9C)
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#define TPU_TSR2 (TPU_BASE + 0xB0)
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#define TPU_TCNT2 (TPU_BASE + 0xB4)
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#define TPU_TGRA2 (TPU_BASE + 0xB8)
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#define TPU_TGRB2 (TPU_BASE + 0xBC)
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#define TPU_TGRC2 (TPU_BASE + 0xC0)
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#define TPU_TGRD2 (TPU_BASE + 0xC4)
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#define TPU_TCR3 (TPU_BASE + 0xD0)
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#define TPU_TMDR3 (TPU_BASE + 0xD4)
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#define TPU_TIOR3 (TPU_BASE + 0xD8)
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#define TPU_TIER3 (TPU_BASE + 0xDC)
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#define TPU_TSR3 (TPU_BASE + 0xE0)
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#define TPU_TCNT3 (TPU_BASE + 0xE4)
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#define TPU_TGRA3 (TPU_BASE + 0xE8)
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#define TPU_TGRB3 (TPU_BASE + 0xEC)
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#define TPU_TGRC3 (TPU_BASE + 0xF0)
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#define TPU_TGRD3 (TPU_BASE + 0xF4)
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/* CMT */
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/* SIOF */
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/* SCIF */
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#define SCIF0_BASE 0xA4430000
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/* SIM */
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/* IrDA */
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/* IIC */
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/* LCDC */
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/* USBF */
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/* MMCIF */
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/* PFC */
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#define PFC_BASE 0xA4050100
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#define PACR (PFC_BASE + 0x00)
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#define PBCR (PFC_BASE + 0x02)
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#define PCCR (PFC_BASE + 0x04)
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#define PDCR (PFC_BASE + 0x06)
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#define PECR (PFC_BASE + 0x08)
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#define PFCR (PFC_BASE + 0x0A)
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#define PGCR (PFC_BASE + 0x0C)
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#define PHCR (PFC_BASE + 0x0E)
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#define PJCR (PFC_BASE + 0x10)
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#define PKCR (PFC_BASE + 0x12)
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#define PLCR (PFC_BASE + 0x14)
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#define PMCR (PFC_BASE + 0x16)
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#define PPCR (PFC_BASE + 0x18)
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#define PRCR (PFC_BASE + 0x1A)
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#define PSCR (PFC_BASE + 0x1C)
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#define PTCR (PFC_BASE + 0x1E)
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#define PUCR (PFC_BASE + 0x20)
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#define PVCR (PFC_BASE + 0x22)
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#define PSELA (PFC_BASE + 0x24)
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#define PSELB (PFC_BASE + 0x26)
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#define PSELC (PFC_BASE + 0x28)
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#define PSELD (PFC_BASE + 0x2A)
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/* I/O Port */
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#define PORT_BASE 0xA4050100
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#define PADR (PORT_BASE + 0x40)
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#define PBDR (PORT_BASE + 0x42)
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#define PCDR (PORT_BASE + 0x44)
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#define PDDR (PORT_BASE + 0x46)
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#define PEDR (PORT_BASE + 0x48)
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#define PFDR (PORT_BASE + 0x4A)
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#define PGDR (PORT_BASE + 0x4C)
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#define PHDR (PORT_BASE + 0x4E)
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#define PJDR (PORT_BASE + 0x50)
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#define PKDR (PORT_BASE + 0x52)
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#define PLDR (PORT_BASE + 0x54)
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#define PMDR (PORT_BASE + 0x56)
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#define PPDR (PORT_BASE + 0x58)
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#define PRDR (PORT_BASE + 0x5A)
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#define PSDR (PORT_BASE + 0x5C)
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#define PTDR (PORT_BASE + 0x5E)
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#define PUDR (PORT_BASE + 0x60)
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#define PVDR (PORT_BASE + 0x62)
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/* H-UDI */
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#endif /* _ASM_CPU_SH7720_H_ */
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