upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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60 lines
1.6 KiB
60 lines
1.6 KiB
8 years ago
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/*
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* Copyright (C) 2016, Imagination Technologies Ltd.
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*
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* Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Imagination Technologies Ltd. MIPSfpga
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*/
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#ifndef __XILFPGA_CONFIG_H
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#define __XILFPGA_CONFIG_H
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/* BootROM + MIG is pretty smart. DDR and Cache initialized */
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/*--------------------------------------------
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* CPU configuration
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*/
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/* CPU Timer rate */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
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/* Cache Configuration */
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
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/*----------------------------------------------------------------------
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* Memory Layout
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*/
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/* SDRAM Configuration (for final code, data, stack, heap) */
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */
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/*----------------------------------------------------------------------
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* Commands
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*/
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/*------------------------------------------------------------
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* Console Configuration
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*/
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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/* -------------------------------------------------
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* Environment
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*/
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#define CONFIG_ENV_SIZE 0x4000
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/* ---------------------------------------------------------------------
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* Board boot configuration
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*/
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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#endif /* __XILFPGA_CONFIG_H */
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