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/*
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* (C) Copyright 2005-2007
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* Samsung Electronics,
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _APOLLON_OMAP24XX_MEM_H_
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#define _APOLLON_OMAP24XX_MEM_H_
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/* Slower full frequency range default timings for x32 operation*/
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#define APOLLON_2420_SDRC_SHARING 0x00000100
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#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011
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#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032
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/* optimized timings good for current shipping parts */
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#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485
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#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C
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#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907
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#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013
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#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001
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#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01
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#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306
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#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506
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#ifdef PRCM_CONFIG_I
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#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
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#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
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#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz
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#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
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#elif PRCM_CONFIG_II
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#define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
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#define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
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#define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz
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#define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
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#endif
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/* GPMC settings */
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#ifdef PRCM_CONFIG_I /* L3 at 165MHz */
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/* CS0: OneNAND */
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# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
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# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000
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# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400
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# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006
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# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11
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# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
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# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24))
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/* CS1: Ethernet */
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# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011200
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# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
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# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
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# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a
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# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
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# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
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# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
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/* CS2: OneNAND */
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/* It's same as CS0 */
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# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
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/* CS3: NOR */
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#ifdef ASYNC_NOR
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# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
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# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
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# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
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# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
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# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
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#else
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# define SYNC_NOR_VALUE 0x24aaa
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# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211
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# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01
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# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201
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# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03
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# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c
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#endif /* ASYNC_NOR */
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# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
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# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24))
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#endif /* endif PRCM_CONFIG_I */
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#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
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/* CS0: OneNAND */
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# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
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# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080
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# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300
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# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004
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# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910
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# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
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# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
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/* CS1: ethernet */
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# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203
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# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
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# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
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# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
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# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
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# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
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# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
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/* CS2: OneNAND */
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/* It's same as CS0 */
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# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
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/* CS3: NOR */
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#define ASYNC_NOR
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#ifdef ASYNC_NOR
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# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
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# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
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# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
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# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
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# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
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#else
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# define SYNC_NOR_VALUE 0x24aaa
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# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202
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# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501
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# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501
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# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07
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# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F
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#endif /* ASYNC_NOR */
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# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
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# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24))
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#endif /* endif PRCM_CONFIG_II */
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#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
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# ifdef CFG_NAND_BOOT
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# define APOLLON_24XX_GPMC_CONFIG1_0 0x0
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# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400
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# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400
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# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01
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# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414
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# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80
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# else /* NOR boot */
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# define APOLLON_24XX_GPMC_CONFIG1_0 0x3
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# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501
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# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602
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# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008
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# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F
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# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4
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# endif /* endif CFG_NAND_BOOT */
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# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
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# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000
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# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01
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# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
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# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
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# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F
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# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
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# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
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#endif /* endif CFG_PRCM_III */
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#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */
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