upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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95 lines
3.5 KiB
95 lines
3.5 KiB
18 years ago
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/*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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*
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* Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _DAVINCI_I2C_H_
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#define _DAVINCI_I2C_H_
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define I2C_BASE 0x01c21000
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#define I2C_OA (I2C_BASE + 0x00)
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#define I2C_IE (I2C_BASE + 0x04)
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#define I2C_STAT (I2C_BASE + 0x08)
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#define I2C_SCLL (I2C_BASE + 0x0c)
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#define I2C_SCLH (I2C_BASE + 0x10)
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#define I2C_CNT (I2C_BASE + 0x14)
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#define I2C_DRR (I2C_BASE + 0x18)
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#define I2C_SA (I2C_BASE + 0x1c)
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#define I2C_DXR (I2C_BASE + 0x20)
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#define I2C_CON (I2C_BASE + 0x24)
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#define I2C_IV (I2C_BASE + 0x28)
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#define I2C_PSC (I2C_BASE + 0x30)
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/* I2C masks */
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/* I2C Interrupt Enable Register (I2C_IE): */
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#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
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#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
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#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
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#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
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#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
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#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
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/* I2C Status Register (I2C_STAT): */
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#define I2C_STAT_BB (1 << 12) /* Bus busy */
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#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
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#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
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#define I2C_STAT_AAS (1 << 9) /* Address as slave */
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#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
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#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
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#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
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#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
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#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
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#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
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/* I2C Interrupt Code Register (I2C_INTCODE): */
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#define I2C_INTCODE_MASK 7
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#define I2C_INTCODE_NONE 0
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#define I2C_INTCODE_AL 1 /* Arbitration lost */
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#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
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#define I2C_INTCODE_ARDY 3 /* Register access ready */
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#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
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#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
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#define I2C_INTCODE_SCD 6 /* Stop condition detect */
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/* I2C Configuration Register (I2C_CON): */
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#define I2C_CON_EN (1 << 5) /* I2C module enable */
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#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
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#define I2C_CON_MST (1 << 10) /* Master/slave mode */
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#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
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#define I2C_CON_XA (1 << 8) /* Expand address */
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#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
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#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
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#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
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#endif
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