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# SPDX-License-Identifier: GPL-2.0+
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NAND FLASH commands and notes
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See NOTE below!!!
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# (C) Copyright 2003
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# Dave Ellis, SIXNET, dge@sixnetio.com
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#
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Commands:
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nand bad
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Print a list of all of the bad blocks in the current device.
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nand device
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Print information about the current NAND device.
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nand device num
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Make device `num' the current device and print information about it.
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nand erase off|partition size
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nand erase clean [off|partition size]
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Erase `size' bytes starting at offset `off'. Alternatively partition
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name can be specified, in this case size will be eventually limited
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to not exceed partition size (this behaviour applies also to read
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and write commands). Only complete erase blocks can be erased.
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If `erase' is specified without an offset or size, the entire flash
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is erased. If `erase' is specified with partition but without an
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size, the entire partition is erased.
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If `clean' is specified, a JFFS2-style clean marker is written to
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each block after it is erased.
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This command will not erase blocks that are marked bad. There is
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a debug option in cmd_nand.c to allow bad blocks to be erased.
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Please read the warning there before using it, as blocks marked
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bad by the manufacturer must _NEVER_ be erased.
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nand info
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Print information about all of the NAND devices found.
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nand read addr ofs|partition size
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Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
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are marked bad are skipped. If a page cannot be read because an
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uncorrectable data error is found, the command stops with an error.
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nand read.oob addr ofs|partition size
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Read `size' bytes from the out-of-band data area corresponding to
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`ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
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data for one 512-byte page or 2 256-byte pages. There is no check
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for bad blocks or ECC errors.
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nand write addr ofs|partition size
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Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
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are marked bad are skipped. If a page cannot be read because an
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uncorrectable data error is found, the command stops with an error.
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As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
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as long as the image is short enough to fit even after skipping the
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bad blocks. Compact images, such as those produced by mkfs.jffs2
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should work well, but loading an image copied from another flash is
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going to be trouble if there are any bad blocks.
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nand write.trimffs addr ofs|partition size
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Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to
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the NAND flash in a manner identical to the 'nand write' command
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described above -- with the additional check that all pages at the end
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of eraseblocks which contain only 0xff data will not be written to the
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NAND flash. This behaviour is required when flashing UBI images
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containing UBIFS volumes as per the UBI FAQ[1].
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[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
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nand write.oob addr ofs|partition size
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Write `size' bytes from `addr' to the out-of-band data area
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corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
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of data for one 512-byte page or 2 256-byte pages. There is no check
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for bad blocks.
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nand read.raw addr ofs|partition [count]
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nand write.raw addr ofs|partition [count]
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Read or write one or more pages at "ofs" in NAND flash, from or to
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"addr" in memory. This is a raw access, so ECC is avoided and the
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OOB area is transferred as well. If count is absent, it is assumed
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to be one page. As with .yaffs2 accesses, the data is formatted as
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a packed sequence of "data, oob, data, oob, ..." -- no alignment of
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individual pages is maintained.
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Configuration Options:
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CONFIG_SYS_NAND_U_BOOT_OFFS
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NAND Offset from where SPL will read u-boot image. This is the starting
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address of u-boot MTD partition in NAND.
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CONFIG_CMD_NAND
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Enables NAND support and commands.
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CONFIG_CMD_NAND_TORTURE
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Enables the torture command (see description of this command below).
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CONFIG_SYS_MAX_NAND_DEVICE
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The maximum number of NAND devices you want to support.
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mtd: move & update nand_ecclayout structure (plus board changes)
nand_ecclayout is present in mtd.h at Linux.
Move this structure to mtd.h to comply with Linux.
Also, increase the ecc placement locations to 640 to suport device having
writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone
up to 640 bytes and consequently the maximum ecc placement locations have
also gone up to 640.
Changes from Prabhabkar's version (squashed into one patch to preserve
bisectability):
- Added _LARGE to MTD_MAX_*_ENTRIES
This makes the names match current Linux source, and resolves
a conflict between
http://patchwork.ozlabs.org/patch/280488/
and
http://patchwork.ozlabs.org/patch/284513/
The former was posted first and is closer to matching Linux, but
unlike Linux it does not add _LARGE to the names. The second adds
_LARGE to one of the names, and depends on it in a subsequent patch
(http://patchwork.ozlabs.org/patch/284512/).
- Made max oobfree/eccpos configurable, and used this on tricorder,
alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build
for me without doing so, due to a size increase).
On tricorder SPL, this saves 2576 bytes (and makes the SPL build
again) versus the new default of 640 eccpos and 32 oobfree, and
saves 336 bytes versus the old default of 128 eccpos and 8 oobfree.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Vipin Kumar <vipin.kumar@st.com>
[scottwood@freescale.com: changes as described above]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Cc: Stefan Roese <sr@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
11 years ago
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CONFIG_SYS_NAND_MAX_ECCPOS
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If specified, overrides the maximum number of ECC bytes
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supported. Useful for reducing image size, especially with SPL.
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This must be at least 48 if nand_base.c is used.
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CONFIG_SYS_NAND_MAX_OOBFREE
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If specified, overrides the maximum number of free OOB regions
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supported. Useful for reducing image size, especially with SPL.
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This must be at least 2 if nand_base.c is used.
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CONFIG_SYS_NAND_MAX_CHIPS
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The maximum number of NAND chips per device to be supported.
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CONFIG_SYS_NAND_SELF_INIT
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Traditionally, glue code in drivers/mtd/nand/nand.c has driven
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the initialization process -- it provides the mtd and nand
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structs, calls a board init function for a specific device,
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calls nand_scan(), and registers with mtd.
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This arrangement does not provide drivers with the flexibility to
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run code between nand_scan_ident() and nand_scan_tail(), or other
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deviations from the "normal" flow.
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If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/nand.c
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will make one call to board_nand_init(), with no arguments. That
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function is responsible for calling a driver init function for
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each NAND device on the board, that performs all initialization
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tasks except setting mtd->name, and registering with the rest of
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U-Boot. Those last tasks are accomplished by calling nand_register()
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on the new mtd device.
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Example of new init to be added to the end of an existing driver
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init:
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/* chip is struct nand_chip, and is now provided by the driver. */
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mtd = nand_to_mtd(&chip);
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/*
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* Fill in appropriate values if this driver uses these fields,
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* or uses the standard read_byte/write_buf/etc. functions from
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* nand_base.c that use these fields.
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*/
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chip.IO_ADDR_R = ...;
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chip.IO_ADDR_W = ...;
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if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
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error out
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/*
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* Insert here any code you wish to run after the chip has been
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* identified, but before any other I/O is done.
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*/
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if (nand_scan_tail(mtd))
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error out
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/*
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* devnum is the device number to be used in nand commands
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* and in mtd->name. Must be less than CONFIG_SYS_MAX_NAND_DEVICE.
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*/
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if (nand_register(devnum, mtd))
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error out
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In addition to providing more flexibility to the driver, it reduces
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the difference between a U-Boot driver and its Linux counterpart.
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nand_init() is now reduced to calling board_nand_init() once, and
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printing a size summary. This should also make it easier to
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transition to delayed NAND initialization.
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Please convert your driver even if you don't need the extra
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flexibility, so that one day we can eliminate the old mechanism.
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CONFIG_SYS_NAND_ONFI_DETECTION
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Enables detection of ONFI compliant devices during probe.
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And fetching device parameters flashed on device, by parsing
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ONFI parameter page.
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Platform specific options
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=========================
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CONFIG_NAND_OMAP_GPMC
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Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
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GPMC controller is used for parallel NAND flash devices, and can
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do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
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and BCH16 ECC algorithms.
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CONFIG_NAND_OMAP_ELM
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Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
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ELM controller is used for ECC error detection (not ECC calculation)
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of BCH4, BCH8 and BCH16 ECC algorithms.
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Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
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thus such SoC platforms need to depend on software library for ECC error
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detection. However ECC calculation on such plaforms would still be
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done by GPMC controller.
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CONFIG_SPL_NAND_AM33XX_BCH
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Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
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hardware ECC correction. This is useful for platforms which have ELM
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hardware engine and use NAND boot mode.
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Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
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so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
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SPL-NAND driver with software ECC correction support.
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CONFIG_NAND_OMAP_ECCSCHEME
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On OMAP platforms, this CONFIG specifies NAND ECC scheme.
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It can take following values:
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OMAP_ECC_HAM1_CODE_SW
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1-bit Hamming code using software lib.
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(for legacy devices only)
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OMAP_ECC_HAM1_CODE_HW
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1-bit Hamming code using GPMC hardware.
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(for legacy devices only)
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
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4-bit BCH code (unsupported)
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OMAP_ECC_BCH4_CODE_HW
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4-bit BCH code (unsupported)
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OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
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8-bit BCH code with
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- ecc calculation using GPMC hardware engine,
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- error detection using software library.
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- requires CONFIG_BCH to enable software BCH library
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(For legacy device which do not have ELM h/w engine)
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OMAP_ECC_BCH8_CODE_HW
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8-bit BCH code with
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- ecc calculation using GPMC hardware engine,
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- error detection using ELM hardware engine.
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OMAP_ECC_BCH16_CODE_HW
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16-bit BCH code with
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- ecc calculation using GPMC hardware engine,
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- error detection using ELM hardware engine.
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How to select ECC scheme on OMAP and AMxx platforms ?
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-----------------------------------------------------
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Though higher ECC schemes have more capability to detect and correct
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bit-flips, but still selection of ECC scheme is dependent on following
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- hardware engines present in SoC.
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Some legacy OMAP SoC do not have ELM h/w engine thus such
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SoC cannot support BCHx_HW ECC schemes.
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- size of OOB/Spare region
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With higher ECC schemes, more OOB/Spare area is required to
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store ECC. So choice of ECC scheme is limited by NAND oobsize.
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In general following expression can help:
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NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
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where
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NAND_OOBSIZE = number of bytes available in
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OOB/spare area per NAND page.
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NAND_PAGESIZE = bytes in main-area of NAND page.
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ECC_BYTES = number of ECC bytes generated to
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protect 512 bytes of data, which is:
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3 for HAM1_xx ecc schemes
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7 for BCH4_xx ecc schemes
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14 for BCH8_xx ecc schemes
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26 for BCH16_xx ecc schemes
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example to check for BCH16 on 2K page NAND
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NAND_PAGESIZE = 2048
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NAND_OOBSIZE = 64
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2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
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Thus BCH16 cannot be supported on 2K page NAND.
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However, for 4K pagesize NAND
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NAND_PAGESIZE = 4096
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NAND_OOBSIZE = 224
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ECC_BYTES = 26
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2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
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Thus BCH16 can be supported on 4K page NAND.
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CONFIG_NAND_OMAP_GPMC_PREFETCH
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On OMAP platforms that use the GPMC controller
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(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
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uses the prefetch mode to speed up read operations.
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NOTE:
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=====
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The Disk On Chip driver is currently broken and has been for some time.
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There is a driver in drivers/mtd/nand, taken from Linux, that works with
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the current NAND system but has not yet been adapted to the u-boot
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environment.
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Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
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JFFS2 related commands:
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implement "nand erase clean" and old "nand erase"
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using both the new code which is able to skip bad blocks
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"nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
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Miscellaneous and testing commands:
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"markbad [offset]"
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create an artificial bad block (for testing bad block handling)
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"scrub [offset length]"
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like "erase" but don't skip bad block. Instead erase them.
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DANGEROUS!!! Factory set bad blocks will be lost. Use only
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to remove artificial bad blocks created with the "markbad" command.
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"torture offset [size]"
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Torture block to determine if it is still reliable.
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Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
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This command returns 0 if the block is still reliable, else 1.
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If the block is detected as unreliable, it is up to the user to decide to
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mark this block as bad.
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The analyzed block is put through 3 erase / write cycles (or less if the block
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is detected as unreliable earlier).
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This command can be used in scripts, e.g. together with the markbad command to
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automate retries and handling of possibly newly detected bad blocks if the
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nand write command fails.
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It can also be used manually by users having seen some NAND errors in logs to
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search the root cause of these errors.
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The underlying nand_torture() function is also useful for code willing to
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automate actions following a nand->write() error. This would e.g. be required
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in order to program or update safely firmware to NAND, especially for the UBI
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part of such firmware.
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Optionally, a second parameter size can be given to test multiple blocks with
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one call. If size is not a multiple of the NAND's erase size, then the block
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that contains offset + size will be tested in full. If used with size, this
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command returns 0 if all tested blocks have been found reliable, else 1.
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NAND locking command (for chips with active LOCKPRE pin)
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"nand lock"
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set NAND chip to lock state (all pages locked)
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"nand lock tight"
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set NAND chip to lock tight state (software can't change locking anymore)
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"nand lock status"
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displays current locking status of all pages
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"nand unlock [offset] [size]"
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unlock consecutive area (can be called multiple times for different areas)
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"nand unlock.allexcept [offset] [size]"
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unlock all except specified consecutive area
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I have tested the code with board containing 128MiB NAND large page chips
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and 32MiB small page chips.
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