upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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118 lines
2.4 KiB
118 lines
2.4 KiB
8 years ago
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/*
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* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
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* (c) Copyright 2016 Topic Embedded Products.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "ps7_init_gpl.h"
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#include <asm/io.h>
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/* For delay calculation using global registers*/
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#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
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#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
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#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
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#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
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#define APU_FREQ 666666666
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#define PS7_MASK_POLL_TIME 100000000
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/* IO accessors. No memory barriers desired. */
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static inline void iowrite(unsigned long val, unsigned long addr)
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{
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__raw_writel(val, addr);
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}
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static inline unsigned long ioread(unsigned long addr)
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{
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return __raw_readl(addr);
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}
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/* start timer */
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static void perf_start_clock(void)
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{
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iowrite((1 << 0) | /* Timer Enable */
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(1 << 3) | /* Auto-increment */
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(0 << 8), /* Pre-scale */
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SCU_GLOBAL_TIMER_CONTROL);
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}
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/* Compute mask for given delay in miliseconds*/
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static int get_number_of_cycles_for_delay(unsigned int delay)
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{
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return (APU_FREQ / (2 * 1000)) * delay;
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}
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/* stop timer */
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static void perf_disable_clock(void)
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{
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iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
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}
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/* stop timer and reset timer count regs */
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static void perf_reset_clock(void)
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{
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perf_disable_clock();
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iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
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iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
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}
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static void perf_reset_and_start_timer(void)
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{
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perf_reset_clock();
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perf_start_clock();
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}
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int ps7_config(unsigned long *ps7_config_init)
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{
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unsigned long *ptr = ps7_config_init;
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unsigned long opcode;
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unsigned long addr;
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unsigned long val;
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unsigned long mask;
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unsigned int numargs;
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int i;
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int delay;
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for (;;) {
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opcode = ptr[0];
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if (opcode == OPCODE_EXIT)
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return PS7_INIT_SUCCESS;
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addr = (opcode & OPCODE_ADDRESS_MASK);
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switch (opcode & ~OPCODE_ADDRESS_MASK) {
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case OPCODE_MASKWRITE:
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numargs = 3;
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mask = ptr[1];
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val = ptr[2];
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iowrite((ioread(addr) & ~mask) | (val & mask), addr);
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break;
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case OPCODE_MASKPOLL:
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numargs = 2;
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mask = ptr[1];
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i = 0;
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while (!(ioread(addr) & mask)) {
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if (i == PS7_MASK_POLL_TIME)
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return PS7_INIT_TIMEOUT;
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i++;
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}
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break;
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case OPCODE_MASKDELAY:
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numargs = 2;
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mask = ptr[1];
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delay = get_number_of_cycles_for_delay(mask);
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perf_reset_and_start_timer();
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while (ioread(addr) < delay)
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;
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break;
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default:
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return PS7_INIT_CORRUPT;
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}
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ptr += numargs;
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}
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}
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