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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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* Gary Jennejohn <gj@denx.de>
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* David Mueller <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2009-2010
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* Michel Pollet <buserror@gmail.com>
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*
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* (C) Copyright 2012
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* Gabriel Huau <contact@huau-gabriel.fr>
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*
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* Configuation settings for the MINI2440 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_TEXT_BASE 0x0
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#define CONFIG_S3C2440_GPIO
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_ARM920T /* This is an ARM920T Core */
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#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
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#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
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#define CONFIG_MINI2440 /* on a MIN2440 Board */
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#define MACH_TYPE_MINI2440 1999
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#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
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/*
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* We don't use lowlevel_init
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*/
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F
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/*
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* input clock of PLL
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*/
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/* MINI2440 has 12.0000MHz input clock */
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#define CONFIG_SYS_CLK_FREQ 12000000
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_DRIVER_DM9000
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#define CONFIG_DRIVER_DM9000_NO_EEPROM
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#define CONFIG_DM9000_BASE 0x20000300
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE+4)
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/*
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* select serial console configuration
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*/
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#define CONFIG_S3C24X0_SERIAL
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#define CONFIG_SERIAL1
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/*
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* allow to overwrite serial and ethaddr
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*/
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#define CONFIG_ENV_OVERWRITE
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/*
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* Command definition
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_PORTIO
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SAVES
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_LONGHELP
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#define CONFIG_SYS_PROMPT "MINI2440 => "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 32
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x30000000
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#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
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/* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x32000000
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/* boot parameters address */
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#define CONFIG_BOOT_PARAM_ADDR 0x30000100
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/*
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* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
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* it to wrap 100 times (total 1562500) to get 1 sec.
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*/
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#define CONFIG_SYS_HZ 1562500
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/*
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* valid baudrates
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*/
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CONFIG_BAUDRATE 115200
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/*
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* Stack sizes
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
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#define CONFIG_SYS_SDRAM_BASE 0x30000000
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#define CONFIG_SYS_FLASH_BASE 0x0
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/*
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* Stack should be on the SRAM because
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* DRAM is not init
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*/
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#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
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/*
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* NOR FLASH organization
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* Now uses the standard CFI interface
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#define CONFIG_SYS_MONITOR_BASE 0x0
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/* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* 512 * 4096 sectors, or 32 * 64k blocks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_FLASH_SHOW_PROGRESS 1
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/*
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* Config for NOR flash
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_MY_ENV_OFFSET 0x40000
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/* addr of environment */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
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/* 16k Total Size of Environment Sector */
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#define CONFIG_ENV_SIZE 0x4000
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/* ATAG configuration */
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#define CONFIG_INITRD_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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#endif /* __CONFIG_H */
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