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upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support
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u-boot/board/amcc/yucca/init.S

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Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
/*
[PATCH] Update AMCC Yucca 440SPe eval board support The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>" The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
15 years ago
#include <asm/mmu.h>
ppc4xx: Use common NS16550 driver for PPC4xx UART This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
14 years ago
#include <asm/ppc4xx.h>
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
Add support for PCI-Express on PPC440SPe (Yucca board).
19 years ago
/**************************************************************************
* TLB table for revA
*************************************************************************/
.globl tlbtabA
tlbtabA:
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
tlbtab_start
[PATCH] Update AMCC Yucca 440SPe eval board support The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
[PATCH] Update AMCC Yucca 440SPe eval board support The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
tlbtab_end
Add support for PCI-Express on PPC440SPe (Yucca board).
19 years ago
/**************************************************************************
* TLB table for revB
*
Merge with /home/raj/git/u-boot
19 years ago
* Notice: revB of the 440SPe chip is very strict about PLB real addresses
Add support for PCI-Express on PPC440SPe (Yucca board).
19 years ago
* and ranges to be mapped for config space: it seems to only work with
* d_nnnn_nnnn range (hangs the core upon config transaction attempts when
* set otherwise) while revA uses c_nnnn_nnnn.
*************************************************************************/
.globl tlbtabB
tlbtabB:
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
tlbtab_start
[PATCH] Update AMCC Yucca 440SPe eval board support The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
[PATCH] Update AMCC Yucca 440SPe eval board support The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
18 years ago
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
Add support for PCI-Express on PPC440SPe (Yucca board).
19 years ago
ppc4xx: TLB init file cleanup This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
15 years ago
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
Add support for AMCC 440SPe CPU based eval board (Yucca).
19 years ago
tlbtab_end