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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* Modified by Udi Finkelstein
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*
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* This file includes communication routines for SMC1 that can run even if
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* SMC2 have already been initialized.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <commproc.h>
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#include <devices.h>
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#include <lcd.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SMC_INDEX 0
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#define PROFF_SMC PROFF_SMC1
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#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
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#define RBC823_KBD_BAUDRATE 38400
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#define CPM_KEYBOARD_BASE 0x1000
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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void smc1_setbrg (void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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/* Set up the baud rate generator.
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* See 8xx_io/commproc.c for details.
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*
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* Wire BRG2 to SMC1, BRG1 to SMC2
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*/
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cp->cp_simode = 0x00001000;
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cp->cp_brgc2 =
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(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
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}
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int smc1_init (void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile smc_t *sp;
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volatile smc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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uint dpaddr;
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/* initialize pointers to SMC */
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sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
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up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
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/* Disable transmitter/receiver.
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*/
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sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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/* Enable SDMA.
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*/
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im->im_siu_conf.sc_sdcr = 1;
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/* clear error conditions */
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#ifdef CONFIG_SYS_SDSR
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im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
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#else
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im->im_sdma.sdma_sdsr = 0x83;
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#endif
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/* clear SDMA interrupt mask */
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#ifdef CONFIG_SYS_SDMR
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im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
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#else
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im->im_sdma.sdma_sdmr = 0x00;
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#endif
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/* Use Port B for SMC1 instead of other functions.
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*/
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cp->cp_pbpar |= 0x000000c0;
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cp->cp_pbdir &= ~0x000000c0;
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cp->cp_pbodr &= ~0x000000c0;
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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#ifdef CONFIG_SYS_ALLOC_DPRAM
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dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
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#else
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dpaddr = CPM_KEYBOARD_BASE ;
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#endif
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/* Allocate space for two buffer descriptors in the DP ram.
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* For now, this address seems OK, but it may have to
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* change with newer versions of the firmware.
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* damm: allocating space after the two buffers for rx/tx data
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*/
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rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
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rbdf->cbd_bufaddr = (uint) (rbdf+2);
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rbdf->cbd_sc = 0;
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tbdf = rbdf + 1;
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tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
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tbdf->cbd_sc = 0;
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/* Set up the uart parameters in the parameter ram.
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*/
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up->smc_rbase = dpaddr;
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up->smc_tbase = dpaddr+sizeof(cbd_t);
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up->smc_rfcr = SMC_EB;
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up->smc_tfcr = SMC_EB;
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/* Set UART mode, 8 bit, no parity, one stop.
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* Enable receive and transmit.
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*/
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sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
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/* Mask all interrupts and remove anything pending.
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*/
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sp->smc_smcm = 0;
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sp->smc_smce = 0xff;
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/* Set up the baud rate generator.
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*/
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smc1_setbrg ();
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/* Make the first buffer the only buffer.
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*/
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tbdf->cbd_sc |= BD_SC_WRAP;
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rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
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/* Single character receive.
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*/
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up->smc_mrblr = 1;
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up->smc_maxidl = 0;
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/* Initialize Tx/Rx parameters.
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*/
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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/* Enable transmitter/receiver.
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*/
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sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
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return (0);
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}
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void smc1_putc(const char c)
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{
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volatile cbd_t *tbdf;
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volatile char *buf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
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tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
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/* Wait for last character to go.
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*/
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buf = (char *)tbdf->cbd_bufaddr;
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*buf = c;
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tbdf->cbd_datlen = 1;
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tbdf->cbd_sc |= BD_SC_READY;
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__asm__("eieio");
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while (tbdf->cbd_sc & BD_SC_READY) {
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WATCHDOG_RESET ();
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__asm__("eieio");
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}
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}
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int smc1_getc(void)
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{
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volatile cbd_t *rbdf;
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volatile unsigned char *buf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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unsigned char c;
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up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
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rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
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/* Wait for character to show up.
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*/
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buf = (unsigned char *)rbdf->cbd_bufaddr;
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while (rbdf->cbd_sc & BD_SC_EMPTY)
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WATCHDOG_RESET ();
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c = *buf;
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rbdf->cbd_sc |= BD_SC_EMPTY;
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return(c);
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}
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int smc1_tstc(void)
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{
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volatile cbd_t *rbdf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
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rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
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return(!(rbdf->cbd_sc & BD_SC_EMPTY));
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}
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/* search for keyboard and register it if found */
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int drv_keyboard_init(void)
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{
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int error = 0;
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device_t kbd_dev;
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if (0) {
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/* register the keyboard */
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memset (&kbd_dev, 0, sizeof(device_t));
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strcpy(kbd_dev.name, "kbd");
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kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
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kbd_dev.putc = NULL;
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kbd_dev.puts = NULL;
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kbd_dev.getc = smc1_getc;
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kbd_dev.tstc = smc1_tstc;
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error = device_register (&kbd_dev);
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} else {
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lcd_is_enabled = 0;
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lcd_disable();
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}
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return error;
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}
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