Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>master
TsiChung Liew
17 years ago
committed by
John Rigby
parent
922cd75155
commit
05316f8ece
@ -0,0 +1,44 @@ |
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o mii.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,27 @@ |
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp |
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
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@ -0,0 +1,108 @@ |
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/*
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* (C) Copyright 2000-2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <spi.h> |
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#include <asm/immap.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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int checkboard(void) |
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{ |
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/*
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* need to to: |
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* Check serial flash size. if 2mb evb, else 8mb demo |
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*/ |
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puts("Board: "); |
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puts("Freescale M54451 EVB\n"); |
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return 0; |
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}; |
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phys_size_t initdram(int board_type) |
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{ |
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u32 dramsize; |
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#ifdef CONFIG_CF_SBF |
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/*
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* Serial Boot: The dram is already initialized in start.S |
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* only require to return DRAM size |
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*/ |
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dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1; |
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#else |
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volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM); |
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volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO); |
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u32 i; |
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dramsize = CFG_SDRAM_SIZE * 0x100000; |
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if ((sdram->sdcfg1 == CFG_SDRAM_CFG1) && |
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(sdram->sdcfg2 == CFG_SDRAM_CFG2)) |
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return dramsize; |
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for (i = 0x13; i < 0x20; i++) { |
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if (dramsize == (1 << i)) |
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break; |
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} |
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i--; |
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gpio->mscr_sdram = 0x44; |
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sdram->sdcs0 = (CFG_SDRAM_BASE | i); |
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sdram->sdcfg1 = CFG_SDRAM_CFG1; |
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sdram->sdcfg2 = CFG_SDRAM_CFG2; |
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udelay(200); |
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/* Issue PALL */ |
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sdram->sdcr = CFG_SDRAM_CTRL | 2; |
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__asm__("nop"); |
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/* Perform two refresh cycles */ |
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sdram->sdcr = CFG_SDRAM_CTRL | 4; |
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__asm__("nop"); |
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sdram->sdcr = CFG_SDRAM_CTRL | 4; |
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__asm__("nop"); |
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/* Issue LEMR */ |
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sdram->sdmr = CFG_SDRAM_MODE; |
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__asm__("nop"); |
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sdram->sdmr = CFG_SDRAM_EMOD; |
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__asm__("nop"); |
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sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000000; |
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udelay(100); |
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#endif |
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return (dramsize); |
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}; |
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int testdram(void) |
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{ |
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/* TODO: XXX XXX XXX */ |
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printf("DRAM test not implemented!\n"); |
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return (0); |
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} |
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@ -0,0 +1,303 @@ |
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/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/fec.h> |
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#include <asm/immap.h> |
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#include <config.h> |
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#include <net.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) |
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#undef MII_DEBUG |
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#undef ET_DEBUG |
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int fecpin_setclear(struct eth_device *dev, int setclear) |
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{ |
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; |
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struct fec_info_s *info = (struct fec_info_s *)dev->priv; |
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if (setclear) { |
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gpio->par_feci2c |= |
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(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); |
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if (info->iobase == CFG_FEC0_IOBASE) |
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gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO; |
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else |
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gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA; |
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} else { |
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gpio->par_feci2c &= |
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~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0); |
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if (info->iobase == CFG_FEC0_IOBASE) |
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gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK; |
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else |
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gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK; |
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} |
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return 0; |
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} |
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#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII) |
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#include <miiphy.h> |
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/* Make MII read/write commands for the FEC. */ |
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#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | (REG & 0x1f) << 18)) |
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#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | (REG & 0x1f) << 18) | (VAL & 0xffff)) |
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/* PHY identification */ |
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#define PHY_ID_KSZ8041NL 0x00221512 |
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#define STR_ID_KSZ8041NL "KSZ8041NL" |
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/****************************************************************************
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* mii_init -- Initialize the MII for MII command without ethernet |
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* This function is a subset of eth_init |
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**************************************************************************** |
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*/ |
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void mii_reset(struct fec_info_s *info) |
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{ |
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volatile fec_t *fecp = (fec_t *) (info->miibase); |
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struct eth_device *dev; |
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int i, miispd; |
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u16 rst = 0; |
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dev = eth_get_dev(); |
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miispd = (gd->bus_clk / 1000000) / 5; |
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fecp->mscr = miispd << 1; |
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miiphy_write(dev->name, info->phy_addr, PHY_BMCR, PHY_BMCR_RESET); |
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for (i = 0; i < FEC_RESET_DELAY; ++i) { |
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udelay(500); |
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miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &rst); |
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if ((rst & PHY_BMCR_RESET) == 0) |
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break; |
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} |
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if (i == FEC_RESET_DELAY) |
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printf("Mii reset timeout %d\n", i); |
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} |
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/* send command to phy using mii, wait for result */ |
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uint mii_send(uint mii_cmd) |
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{ |
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struct fec_info_s *info; |
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struct eth_device *dev; |
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volatile fec_t *ep; |
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uint mii_reply; |
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int j = 0; |
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/* retrieve from register structure */ |
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dev = eth_get_dev(); |
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info = dev->priv; |
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ep = (fec_t *) info->miibase; |
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ep->mmfr = mii_cmd; /* command to phy */ |
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/* wait for mii complete */ |
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while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { |
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udelay(1); |
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j++; |
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} |
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if (j >= MCFFEC_TOUT_LOOP) { |
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printf("MII not complete\n"); |
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return -1; |
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} |
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mii_reply = ep->mmfr; /* result from phy */ |
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ep->eir = FEC_EIR_MII; /* clear MII complete */ |
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#ifdef ET_DEBUG |
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printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", |
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__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); |
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#endif |
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return (mii_reply & 0xffff); /* data read from phy */ |
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} |
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#endif /* CFG_DISCOVER_PHY || (CONFIG_MII) */ |
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#if defined(CFG_DISCOVER_PHY) |
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int mii_discover_phy(struct eth_device *dev) |
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{ |
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#define MAX_PHY_PASSES 11 |
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struct fec_info_s *info = dev->priv; |
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int phyaddr, pass; |
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uint phyno, phytype; |
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if (info->phyname_init) |
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return info->phy_addr; |
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phyaddr = -1; /* didn't find a PHY yet */ |
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for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { |
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if (pass > 1) { |
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/* PHY may need more time to recover from reset.
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* The LXT970 needs 50ms typical, no maximum is |
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* specified, so wait 10ms before try again. |
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* With 11 passes this gives it 100ms to wake up. |
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*/ |
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udelay(10000); /* wait 10ms */ |
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} |
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for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { |
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phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); |
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#ifdef ET_DEBUG |
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printf("PHY type 0x%x pass %d type\n", phytype, pass); |
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#endif |
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if (phytype != 0xffff) { |
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phyaddr = phyno; |
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phytype <<= 16; |
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phytype |= |
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mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); |
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switch (phytype & 0xffffffff) { |
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case PHY_ID_KSZ8041NL: |
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strcpy(info->phy_name, |
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STR_ID_KSZ8041NL); |
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info->phyname_init = 1; |
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break; |
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default: |
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strcpy(info->phy_name, "unknown"); |
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info->phyname_init = 1; |
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break; |
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} |
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#ifdef ET_DEBUG |
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printf("PHY @ 0x%x pass %d type ", phyno, pass); |
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switch (phytype & 0xffffffff) { |
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case PHY_ID_KSZ8041NL: |
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printf(STR_ID_KSZ8041NL); |
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break; |
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default: |
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printf("0x%08x\n", phytype); |
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break; |
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} |
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#endif |
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} |
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} |
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} |
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if (phyaddr < 0) |
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printf("No PHY device found.\n"); |
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return phyaddr; |
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} |
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#endif /* CFG_DISCOVER_PHY */ |
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void mii_init(void) __attribute__ ((weak, alias("__mii_init"))); |
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void __mii_init(void) |
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{ |
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volatile fec_t *fecp; |
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struct fec_info_s *info; |
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struct eth_device *dev; |
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int miispd = 0, i = 0; |
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u16 autoneg = 0; |
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/* retrieve from register structure */ |
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dev = eth_get_dev(); |
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info = dev->priv; |
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fecp = (fec_t *) info->miibase; |
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/* We use strictly polling mode only */ |
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fecp->eimr = 0; |
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/* Clear any pending interrupt */ |
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fecp->eir = 0xffffffff; |
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/* Set MII speed */ |
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miispd = (gd->bus_clk / 1000000) / 5; |
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fecp->mscr = miispd << 1; |
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info->phy_addr = mii_discover_phy(dev); |
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#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) |
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while (i < MCFFEC_TOUT_LOOP) { |
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autoneg = 0; |
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miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); |
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i++; |
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if ((autoneg & AUTONEGLINK) == AUTONEGLINK) |
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break; |
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udelay(500); |
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} |
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if (i >= MCFFEC_TOUT_LOOP) { |
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printf("Auto Negotiation not complete\n"); |
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} |
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|
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/* adapt to the half/full speed settings */ |
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info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; |
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info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); |
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} |
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|
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/*****************************************************************************
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* Read and write a MII PHY register, routines used by MII Utilities |
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* |
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* FIXME: These routines are expected to return 0 on success, but mii_send |
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* does _not_ return an error code. Maybe 0xFFFF means error, i.e. |
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* no PHY connected... |
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* For now always return 0. |
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* FIXME: These routines only work after calling eth_init() at least once! |
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* Otherwise they hang in mii_send() !!! Sorry! |
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*****************************************************************************/ |
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int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, |
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unsigned short *value) |
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{ |
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short rdreg; /* register working value */ |
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#ifdef MII_DEBUG |
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printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); |
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#endif |
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rdreg = mii_send(mk_mii_read(addr, reg)); |
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*value = rdreg; |
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#ifdef MII_DEBUG |
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printf("0x%04x\n", *value); |
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#endif |
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return 0; |
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} |
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|
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int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, |
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unsigned short value) |
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{ |
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short rdreg; /* register working value */ |
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#ifdef MII_DEBUG |
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printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); |
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#endif |
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rdreg = mii_send(mk_mii_write(addr, reg, value)); |
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#ifdef MII_DEBUG |
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printf("0x%04x\n", value); |
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#endif |
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return 0; |
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} |
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|
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#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ |
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@ -0,0 +1,143 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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OUTPUT_ARCH(m68k) |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mcf5445x/start.o (.text) |
||||
lib_m68k/traps.o (.text) |
||||
lib_m68k/interrupts.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .; |
||||
common/environment.o (.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
|
||||
.reloc : |
||||
{ |
||||
__got_start = .; |
||||
*(.got) |
||||
__got_end = .; |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
_sbss = .; |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
_ebss = .; |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,149 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(m68k) |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mcf5445x/start.o (.text) |
||||
/* cpu/mcf5445x/cpu_init.o (.text) |
||||
cpu/mcf5445x/cpu.o (.text) |
||||
cpu/mcf5445x/dspi.o (.text) |
||||
cpu/mcf5445x/interrupt.o (.text) |
||||
cpu/mcf5445x/speed.o (.text) |
||||
lib_m68k/board.o (.text) |
||||
common/serial.o (.text) |
||||
common/console.o (.text) |
||||
lib_generic/display_options.o (.text) |
||||
board/freescale/m54455evb/m54455evb.o (.text) |
||||
|
||||
. = DEFINED(env_offset) ? env_offset : .; |
||||
common/environment.o (.text) |
||||
*/ |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
|
||||
.reloc : |
||||
{ |
||||
__got_start = .; |
||||
*(.got) |
||||
__got_end = .; |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
_sbss = .; |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
_ebss = .; |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,350 @@ |
||||
/*
|
||||
* Configuation settings for the Freescale MCF54451 EVB board. |
||||
* |
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef _M54451EVB_H |
||||
#define _M54451EVB_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_MCF5445x /* define processor family */ |
||||
#define CONFIG_M54451 /* define processor type */ |
||||
#define CONFIG_M54451EVB /* M54451EVB board */ |
||||
|
||||
#define CONFIG_MCFUART |
||||
#define CFG_UART_PORT (0) |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
||||
|
||||
#undef CONFIG_WATCHDOG |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/* Command line configuration */ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_BOOTD |
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_FLASH |
||||
#define CONFIG_CMD_I2C |
||||
#undef CONFIG_CMD_JFFS2 |
||||
#define CONFIG_CMD_MEMORY |
||||
#define CONFIG_CMD_MISC |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_SPI |
||||
#define CONFIG_CMD_SF |
||||
|
||||
#undef CONFIG_CMD_LOADB |
||||
#undef CONFIG_CMD_LOADS |
||||
|
||||
/* Network configuration */ |
||||
#define CONFIG_MCFFEC |
||||
#ifdef CONFIG_MCFFEC |
||||
# define CONFIG_NET_MULTI 1 |
||||
# define CONFIG_MII 1 |
||||
# define CONFIG_MII_INIT 1 |
||||
# define CFG_DISCOVER_PHY |
||||
# define CFG_RX_ETH_BUFFER 8 |
||||
# define CFG_FAULT_ECHO_LINK_DOWN |
||||
|
||||
# define CFG_FEC0_PINMUX 0 |
||||
# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE |
||||
# define MCFFEC_TOUT_LOOP 50000 |
||||
|
||||
# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
||||
# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" |
||||
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 |
||||
# define CONFIG_ETHPRIME "FEC0" |
||||
# define CONFIG_IPADDR 192.162.1.2 |
||||
# define CONFIG_NETMASK 255.255.255.0 |
||||
# define CONFIG_SERVERIP 192.162.1.1 |
||||
# define CONFIG_GATEWAYIP 192.162.1.1 |
||||
# define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
|
||||
/* If CFG_DISCOVER_PHY is not defined - hardcoded */ |
||||
# ifndef CFG_DISCOVER_PHY |
||||
# define FECDUPLEX FULL |
||||
# define FECSPEED _100BASET |
||||
# else |
||||
# ifndef CFG_FAULT_ECHO_LINK_DOWN |
||||
# define CFG_FAULT_ECHO_LINK_DOWN |
||||
# endif |
||||
# endif /* CFG_DISCOVER_PHY */ |
||||
#endif |
||||
|
||||
#define CONFIG_HOSTNAME M54451EVB |
||||
#ifdef CFG_STMICRO_BOOT |
||||
/* ST Micro serial flash */ |
||||
#define CFG_LOAD_ADDR2 0x40010007 |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=0x40010000\0" \
|
||||
"sbfhdr=sbfhdr.bin\0" \
|
||||
"uboot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr} ${sbfhdr};" \
|
||||
"tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=sf probe 0:1 10000 1;" \
|
||||
"sf erase 0 30000;" \
|
||||
"sf write ${loadaddr} 0 30000;" \
|
||||
"save\0" \
|
||||
"" |
||||
#else |
||||
#define CFG_UBOOT_END 0x3FFFF |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
|
||||
"loadaddr=40010000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off 0 " MK_STR(CFG_UBOOT_END)\
|
||||
"; era 0 " MK_STR(CFG_UBOOT_END) \
|
||||
"2ffff;" \
|
||||
"cp.b ${loadaddr} 0 ${filesize};" \
|
||||
"save\0" \
|
||||
"" |
||||
#endif |
||||
|
||||
/* Realtime clock */ |
||||
#define CONFIG_MCFRTC |
||||
#undef RTC_DEBUG |
||||
#define CFG_RTC_OSCILLATOR (32 * CFG_HZ) |
||||
|
||||
/* Timer */ |
||||
#define CONFIG_MCFTMR |
||||
#undef CONFIG_MCFPIT |
||||
|
||||
/* I2c */ |
||||
#define CONFIG_FSL_I2C |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_OFFSET 0x58000 |
||||
#define CFG_IMMR CFG_MBAR |
||||
|
||||
/* DSPI and Serial Flash */ |
||||
#define CONFIG_CF_DSPI |
||||
#define CONFIG_SERIAL_FLASH |
||||
#define CONFIG_HARD_SPI |
||||
#define CFG_SER_FLASH_BASE 0x01000000 |
||||
#define CFG_SBFHDR_SIZE 0x7 |
||||
#ifdef CONFIG_CMD_SPI |
||||
# define CONFIG_SPI_FLASH |
||||
# define CONFIG_SPI_FLASH_STMICRO |
||||
|
||||
# define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ |
||||
DSPI_DCTAR_CPOL | \
|
||||
DSPI_DCTAR_CPHA | \
|
||||
DSPI_DCTAR_PCSSCK_1CLK | \
|
||||
DSPI_DCTAR_PASC(0) | \
|
||||
DSPI_DCTAR_PDT(0) | \
|
||||
DSPI_DCTAR_CSSCK(0) | \
|
||||
DSPI_DCTAR_ASC(0) | \
|
||||
DSPI_DCTAR_PBR(0) | \
|
||||
DSPI_DCTAR_DT(1) | \
|
||||
DSPI_DCTAR_BR(1)) |
||||
#endif |
||||
|
||||
/* Input, PCI, Flexbus, and VCO */ |
||||
#define CONFIG_EXTRA_CLOCK |
||||
|
||||
#define CONFIG_PRAM 2048 /* 2048 KB */ |
||||
|
||||
#define CFG_PROMPT "-> " |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) |
||||
|
||||
#define CFG_HZ 1000 |
||||
|
||||
#define CFG_MBAR 0xFC000000 |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR 0x80000000 |
||||
#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ |
||||
#define CFG_INIT_RAM_CTRL 0x221 |
||||
#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
#define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x40000000 |
||||
#define CFG_SDRAM_SIZE 128 /* SDRAM size in MB */ |
||||
#define CFG_SDRAM_CFG1 0x33633F30 |
||||
#define CFG_SDRAM_CFG2 0x57670000 |
||||
#define CFG_SDRAM_CTRL 0xE20D2C00 |
||||
#define CFG_SDRAM_EMOD 0x80810000 |
||||
#define CFG_SDRAM_MODE 0x008D0000 |
||||
#define CFG_SDRAM_DRV_STRENGTH 0x44 |
||||
|
||||
#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 |
||||
#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) |
||||
|
||||
#ifdef CONFIG_CF_SBF |
||||
# define CFG_MONITOR_BASE (TEXT_BASE + 0x400) |
||||
#else |
||||
# define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) |
||||
#endif |
||||
#define CFG_BOOTPARAMS_LEN 64*1024 |
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization ?? |
||||
*/ |
||||
/* Initial Memory map for Linux */ |
||||
#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) |
||||
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash |
||||
*/ |
||||
#if defined(CONFIG_CF_SBF) |
||||
# define CFG_ENV_IS_IN_SPI_FLASH 1 |
||||
# define CFG_ENV_SPI_CS 1 |
||||
# define CFG_ENV_OFFSET 0x20000 |
||||
# define CFG_ENV_SIZE 0x2000 |
||||
# define CFG_ENV_SECT_SIZE 0x10000 |
||||
#else |
||||
# define CFG_ENV_IS_IN_FLASH 1 |
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) |
||||
# define CFG_ENV_SECT_SIZE 0x2000 |
||||
#endif |
||||
#undef CONFIG_ENV_OVERWRITE |
||||
#undef CFG_ENV_IS_EMBEDDED |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#ifdef CFG_STMICRO_BOOT |
||||
# define CFG_FLASH_BASE CFG_SER_FLASH_BASE |
||||
# define CFG_FLASH0_BASE CFG_SER_FLASH_BASE |
||||
# define CFG_FLASH1_BASE CFG_CS0_BASE |
||||
#endif |
||||
#ifdef CFG_SPANSION_BOOT |
||||
# define CFG_FLASH_BASE CFG_CS0_BASE |
||||
# define CFG_FLASH0_BASE CFG_CS0_BASE |
||||
# define CFG_FLASH1_BASE CFG_SER_FLASH_BASE |
||||
#endif |
||||
|
||||
#define CFG_FLASH_CFI |
||||
#ifdef CFG_FLASH_CFI |
||||
|
||||
# define CONFIG_FLASH_CFI_DRIVER 1 |
||||
# define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
||||
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
||||
# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
||||
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
||||
# define CFG_FLASH_CHECKSUM |
||||
# define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE } |
||||
|
||||
#endif |
||||
|
||||
/*
|
||||
* This is setting for JFFS2 support in u-boot. |
||||
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. |
||||
*/ |
||||
#ifdef CFG_SPANSION_BOOT |
||||
# define CONFIG_JFFS2_DEV "nor0" |
||||
# define CONFIG_JFFS2_PART_SIZE 0x01000000 |
||||
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) |
||||
#endif |
||||
#ifdef CFG_STMICRO_BOOT |
||||
# define CONFIG_JFFS2_DEV "nor0" |
||||
# define CONFIG_JFFS2_PART_SIZE 0x01000000 |
||||
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Memory bank definitions |
||||
*/ |
||||
/*
|
||||
* CS0 - NOR Flash 8MB |
||||
* CS1 - Available |
||||
* CS2 - Available |
||||
* CS3 - Available |
||||
* CS4 - Available |
||||
* CS5 - Available |
||||
*/ |
||||
|
||||
/* SPANSION Flash */ |
||||
#define CFG_CS0_BASE 0x00000000 |
||||
#define CFG_CS0_MASK 0x007F0001 |
||||
#define CFG_CS0_CTRL 0x00001180 |
||||
|
||||
#define CFG_SPANSION_BASE CFG_CS0_BASE |
||||
|
||||
#endif /* _M54451EVB_H */ |
||||
Loading…
Reference in new issue