Wolfgang Denk
15 years ago
commit
05c2f4fe29
@ -0,0 +1,498 @@ |
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/*
|
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* Copyright (C) 2009 BuS Elektronik GmbH & Co. KG |
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* Jens Scharsig (esw@bus-elektronik.de) |
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* |
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* (C) Copyright 2003 |
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* Author : Hamid Ikdoumi (Atmel) |
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|
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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#ifndef CONFIG_AT91_LEGACY |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/at91_emac.h> |
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#include <asm/arch/at91_pmc.h> |
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#include <asm/arch/at91_pio.h> |
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#else |
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/* remove next 5 lines, if all RM9200 boards convert to at91 arch */ |
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#include <asm/arch-at91/at91rm9200.h> |
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#include <asm/arch-at91/hardware.h> |
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#include <asm/arch-at91/at91_emac.h> |
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#include <asm/arch-at91/at91_pmc.h> |
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#include <asm/arch-at91/at91_pio.h> |
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#endif |
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#include <net.h> |
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#include <netdev.h> |
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#include <malloc.h> |
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#include <miiphy.h> |
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#include <linux/mii.h> |
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#undef MII_DEBUG |
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#undef ET_DEBUG |
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|
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#if (CONFIG_SYS_RX_ETH_BUFFER > 1024) |
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#error AT91 EMAC supports max 1024 RX buffers. \ |
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Please decrease the CONFIG_SYS_RX_ETH_BUFFER value |
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#endif |
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|
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/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ |
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#if (AT91C_MASTER_CLOCK > 80000000) |
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_64 |
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#elif (AT91C_MASTER_CLOCK > 40000000) |
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_32 |
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#elif (AT91C_MASTER_CLOCK > 20000000) |
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_16 |
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#else |
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#define HCLK_DIV AT91_EMAC_CFG_MCLK_8 |
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#endif |
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|
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#ifdef ET_DEBUG |
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#define DEBUG_AT91EMAC(...) printf(__VA_ARGS__); |
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#else |
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#define DEBUG_AT91EMAC(...) |
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#endif |
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|
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#ifdef MII_DEBUG |
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#define DEBUG_AT91PHY(...) printf(__VA_ARGS__); |
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#else |
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#define DEBUG_AT91PHY(...) |
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#endif |
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|
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#ifndef CONFIG_DRIVER_AT91EMAC_QUIET |
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#define VERBOSEP(...) printf(__VA_ARGS__); |
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#else |
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#define VERBOSEP(...) |
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#endif |
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#define RBF_ADDR 0xfffffffc |
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#define RBF_OWNER (1<<0) |
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#define RBF_WRAP (1<<1) |
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#define RBF_BROADCAST (1<<31) |
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#define RBF_MULTICAST (1<<30) |
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#define RBF_UNICAST (1<<29) |
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#define RBF_EXTERNAL (1<<28) |
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#define RBF_UNKOWN (1<<27) |
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#define RBF_SIZE 0x07ff |
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#define RBF_LOCAL4 (1<<26) |
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#define RBF_LOCAL3 (1<<25) |
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#define RBF_LOCAL2 (1<<24) |
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#define RBF_LOCAL1 (1<<23) |
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#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER |
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#define RBF_FRAMELEN 0x600 |
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typedef struct { |
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unsigned long addr, size; |
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} rbf_t; |
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typedef struct { |
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rbf_t rbfdt[RBF_FRAMEMAX]; |
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unsigned long rbindex; |
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} emac_device; |
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void at91emac_EnableMDIO(at91_emac_t *at91mac) |
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{ |
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/* Mac CTRL reg set for MDIO enable */ |
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writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); |
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} |
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void at91emac_DisableMDIO(at91_emac_t *at91mac) |
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{ |
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/* Mac CTRL reg set for MDIO disable */ |
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writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); |
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} |
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int at91emac_read(at91_emac_t *at91mac, unsigned char addr, |
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unsigned char reg, unsigned short *value) |
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{ |
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at91emac_EnableMDIO(at91mac); |
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writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | |
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AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | |
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AT91_EMAC_MAN_PHYA(addr), |
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&at91mac->man); |
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udelay(10000); |
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*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; |
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at91emac_DisableMDIO(at91mac); |
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DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value) |
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return 0; |
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} |
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int at91emac_write(at91_emac_t *at91mac, unsigned char addr, |
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unsigned char reg, unsigned short value) |
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{ |
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DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value) |
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at91emac_EnableMDIO(at91mac); |
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writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | |
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AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | |
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AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), |
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&at91mac->man); |
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udelay(10000); |
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at91emac_DisableMDIO(at91mac); |
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return 0; |
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} |
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
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at91_emac_t *get_emacbase_by_name(char *devname) |
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{ |
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struct eth_device *netdev; |
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netdev = eth_get_dev_by_name(devname); |
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return (at91_emac_t *) netdev->iobase; |
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} |
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int at91emac_mii_read(char *devname, unsigned char addr, |
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unsigned char reg, unsigned short *value) |
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{ |
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at91_emac_t *emac; |
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emac = get_emacbase_by_name(devname); |
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at91emac_read(emac , addr, reg, value); |
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return 0; |
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} |
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int at91emac_mii_write(char *devname, unsigned char addr, |
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unsigned char reg, unsigned short value) |
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{ |
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at91_emac_t *emac; |
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emac = get_emacbase_by_name(devname); |
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at91emac_write(emac, addr, reg, value); |
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return 0; |
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} |
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#endif |
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static int at91emac_phy_reset(struct eth_device *netdev) |
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{ |
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int i; |
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u16 status, adv; |
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at91_emac_t *emac; |
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emac = (at91_emac_t *) netdev->iobase; |
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adv = ADVERTISE_CSMA | ADVERTISE_ALL; |
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at91emac_write(emac, 0, MII_ADVERTISE, adv); |
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VERBOSEP("%s: Starting autonegotiation...\n", netdev->name); |
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at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART)); |
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for (i = 0; i < 100000 / 100; i++) { |
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at91emac_read(emac, 0, MII_BMSR, &status); |
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if (status & BMSR_ANEGCOMPLETE) |
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break; |
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udelay(100); |
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} |
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if (status & BMSR_ANEGCOMPLETE) { |
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VERBOSEP("%s: Autonegotiation complete\n", netdev->name); |
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} else { |
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printf("%s: Autonegotiation timed out (status=0x%04x)\n", |
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netdev->name, status); |
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return 1; |
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} |
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return 0; |
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} |
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static int at91emac_phy_init(struct eth_device *netdev) |
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{ |
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u16 phy_id, status, adv, lpa; |
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int media, speed, duplex; |
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int i; |
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at91_emac_t *emac; |
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emac = (at91_emac_t *) netdev->iobase; |
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/* Check if the PHY is up to snuff... */ |
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at91emac_read(emac, 0, MII_PHYSID1, &phy_id); |
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if (phy_id == 0xffff) { |
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printf("%s: No PHY present\n", netdev->name); |
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return 1; |
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} |
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at91emac_read(emac, 0, MII_BMSR, &status); |
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if (!(status & BMSR_LSTATUS)) { |
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/* Try to re-negotiate if we don't have link already. */ |
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if (at91emac_phy_reset(netdev)) |
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return 2; |
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for (i = 0; i < 100000 / 100; i++) { |
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at91emac_read(emac, 0, MII_BMSR, &status); |
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if (status & BMSR_LSTATUS) |
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break; |
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udelay(100); |
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} |
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} |
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if (!(status & BMSR_LSTATUS)) { |
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VERBOSEP("%s: link down\n", netdev->name); |
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return 3; |
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} else { |
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at91emac_read(emac, 0, MII_ADVERTISE, &adv); |
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at91emac_read(emac, 0, MII_LPA, &lpa); |
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media = mii_nway_result(lpa & adv); |
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speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) |
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? 1 : 0); |
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duplex = (media & ADVERTISE_FULL) ? 1 : 0; |
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VERBOSEP("%s: link up, %sMbps %s-duplex\n", |
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netdev->name, |
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speed ? "100" : "10", |
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duplex ? "full" : "half"); |
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} |
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return 0; |
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} |
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int at91emac_UpdateLinkSpeed(at91_emac_t *emac) |
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{ |
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unsigned short stat1; |
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at91emac_read(emac, 0, MII_BMSR, &stat1); |
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if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ |
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return 1; |
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if (stat1 & BMSR_100FULL) { |
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/*set Emac for 100BaseTX and Full Duplex */ |
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writel(readl(&emac->cfg) | |
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AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, |
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&emac->cfg); |
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return 0; |
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} |
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if (stat1 & BMSR_10FULL) { |
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/*set MII for 10BaseT and Full Duplex */ |
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writel((readl(&emac->cfg) & |
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) |
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) | AT91_EMAC_CFG_FD, |
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&emac->cfg); |
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return 0; |
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} |
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if (stat1 & BMSR_100HALF) { |
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/*set MII for 100BaseTX and Half Duplex */ |
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writel((readl(&emac->cfg) & |
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) |
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) | AT91_EMAC_CFG_SPD, |
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&emac->cfg); |
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return 0; |
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} |
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if (stat1 & BMSR_10HALF) { |
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/*set MII for 10BaseT and Half Duplex */ |
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writel((readl(&emac->cfg) & |
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~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), |
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&emac->cfg); |
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return 0; |
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} |
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return 1; |
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} |
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static int at91emac_init(struct eth_device *netdev, bd_t *bd) |
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{ |
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int i; |
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u32 value; |
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emac_device *dev; |
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at91_emac_t *emac; |
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at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; |
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
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emac = (at91_emac_t *) netdev->iobase; |
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dev = (emac_device *) netdev->priv; |
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/* PIO Disable Register */ |
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value = AT91_PMX_AA_EMDIO | AT91_PMX_AA_EMDC | |
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AT91_PMX_AA_ERXER | AT91_PMX_AA_ERX1 | |
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AT91_PMX_AA_ERX0 | AT91_PMX_AA_ECRS | |
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AT91_PMX_AA_ETX1 | AT91_PMX_AA_ETX0 | |
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AT91_PMX_AA_ETXEN | AT91_PMX_AA_EREFCK; |
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writel(value, &pio->pioa.pdr); |
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writel(value, &pio->pioa.asr); |
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#ifdef CONFIG_RMII |
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value = AT91_PMX_BA_ERXCK; |
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#else |
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value = AT91_PMX_BA_ERXCK | AT91_PMX_BA_ECOL | |
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AT91_PMX_BA_ERXDV | AT91_PMX_BA_ERX3 | |
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AT91_PMX_BA_ERX2 | AT91_PMX_BA_ETXER | |
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AT91_PMX_BA_ETX3 | AT91_PMX_BA_ETX2; |
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#endif |
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writel(value, &pio->piob.pdr); |
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writel(value, &pio->piob.bsr); |
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writel(1 << AT91_ID_EMAC, &pmc->pcer); |
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); |
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DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", |
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cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), |
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cpu_to_le32(*((u32 *)netdev->enetaddr))); |
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writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l); |
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writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h); |
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DEBUG_AT91EMAC("init MAC-ADDR %x%x \n", |
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readl(&emac->sa2h), readl(&emac->sa2l)); |
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/* Init Ethernet buffers */ |
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for (i = 0; i < RBF_FRAMEMAX; i++) { |
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dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i]; |
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dev->rbfdt[i].size = 0; |
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} |
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dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; |
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dev->rbindex = 0; |
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writel((u32) &(dev->rbfdt[0]), &emac->rbqp); |
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writel(readl(&emac->rsr) & |
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~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), |
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&emac->rsr); |
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value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | |
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HCLK_DIV; |
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#ifdef CONFIG_RMII |
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value |= AT91C_EMAC_RMII; |
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#endif |
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writel(value, &emac->cfg); |
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, |
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&emac->ctl); |
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if (!at91emac_phy_init(netdev)) { |
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at91emac_UpdateLinkSpeed(emac); |
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return 0; |
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} |
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return 1; |
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} |
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static void at91emac_halt(struct eth_device *netdev) |
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{ |
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at91_emac_t *emac; |
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emac = (at91_emac_t *) netdev->iobase; |
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writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), |
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&emac->ctl); |
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DEBUG_AT91EMAC("halt MAC\n"); |
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} |
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static int at91emac_send(struct eth_device *netdev, volatile void *packet, |
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int length) |
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{ |
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at91_emac_t *emac; |
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emac = (at91_emac_t *) netdev->iobase; |
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while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) |
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; |
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writel((u32) packet, &emac->tar); |
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writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); |
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while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) |
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; |
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DEBUG_AT91EMAC("Send %d \n", length); |
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writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); |
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return 0; |
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} |
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|
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static int at91emac_recv(struct eth_device *netdev) |
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{ |
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emac_device *dev; |
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at91_emac_t *emac; |
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rbf_t *rbfp; |
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int size; |
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emac = (at91_emac_t *) netdev->iobase; |
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dev = (emac_device *) netdev->priv; |
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rbfp = &dev->rbfdt[dev->rbindex]; |
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while (rbfp->addr & RBF_OWNER) { |
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size = rbfp->size & RBF_SIZE; |
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NetReceive(NetRxPackets[dev->rbindex], size); |
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DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n", |
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dev->rbindex, size, rbfp->addr); |
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rbfp->addr &= ~RBF_OWNER; |
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rbfp->size = 0; |
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if (dev->rbindex < (RBF_FRAMEMAX-1)) |
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dev->rbindex++; |
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else |
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dev->rbindex = 0; |
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|
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rbfp = &(dev->rbfdt[dev->rbindex]); |
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if (!(rbfp->addr & RBF_OWNER)) |
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writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, |
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&emac->rsr); |
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} |
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|
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if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { |
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/* EMAC silicon bug 41.3.1 workaround 1 */ |
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writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); |
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writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); |
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dev->rbindex = 0; |
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printf("%s: reset receiver (EMAC dead lock bug)\n", |
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netdev->name); |
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} |
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return 0; |
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} |
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|
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int at91emac_register(bd_t *bis, unsigned long iobase) |
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{ |
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emac_device *emac; |
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emac_device *emacfix; |
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struct eth_device *dev; |
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|
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if (iobase == 0) |
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iobase = AT91_EMAC_BASE; |
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emac = malloc(sizeof(*emac)+512); |
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if (emac == NULL) |
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return 1; |
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dev = malloc(sizeof(*dev)); |
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if (dev == NULL) { |
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free(emac); |
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return 1; |
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} |
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/* alignment as per Errata (64 bytes) is insufficient! */ |
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emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); |
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memset(emacfix, 0, sizeof(emac_device)); |
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|
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memset(dev, 0, sizeof(*dev)); |
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#ifndef CONFIG_RMII |
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sprintf(dev->name, "AT91 EMAC"); |
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#else |
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sprintf(dev->name, "AT91 EMAC RMII"); |
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#endif |
||||
dev->iobase = iobase; |
||||
dev->priv = emacfix; |
||||
dev->init = at91emac_init; |
||||
dev->halt = at91emac_halt; |
||||
dev->send = at91emac_send; |
||||
dev->recv = at91emac_recv; |
||||
|
||||
eth_register(dev); |
||||
|
||||
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
||||
miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write); |
||||
#endif |
||||
return 1; |
||||
} |
||||
@ -0,0 +1,653 @@ |
||||
/*
|
||||
* Cirrus Logic EP93xx ethernet MAC / MII driver. |
||||
* |
||||
* Copyright (C) 2010, 2009 |
||||
* Matthias Kaehlcke <matthias@kaehlcke.net> |
||||
* |
||||
* Copyright (C) 2004, 2005 |
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> |
||||
* |
||||
* Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver, |
||||
* which is |
||||
* |
||||
* (C) Copyright 2002 2003 |
||||
* Adam Bezanson, Network Audio Technologies, Inc. |
||||
* <bezanson@netaudiotech.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, but |
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
||||
* for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License along |
||||
* with this program; if not, write to the Free Software Foundation, Inc., |
||||
* 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <command.h> |
||||
#include <common.h> |
||||
#include <asm/arch/ep93xx.h> |
||||
#include <asm/io.h> |
||||
#include <malloc.h> |
||||
#include <miiphy.h> |
||||
#include <linux/types.h> |
||||
#include "ep93xx_eth.h" |
||||
|
||||
#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv) |
||||
#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs) |
||||
|
||||
/* ep93xx_miiphy ops forward declarations */ |
||||
static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, |
||||
unsigned char const reg, unsigned short * const value); |
||||
static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, |
||||
unsigned char const reg, unsigned short const value); |
||||
|
||||
#if defined(EP93XX_MAC_DEBUG) |
||||
/**
|
||||
* Dump ep93xx_mac values to the terminal. |
||||
*/ |
||||
static void dump_dev(struct eth_device *dev) |
||||
{ |
||||
struct ep93xx_priv *priv = GET_PRIV(dev); |
||||
int i; |
||||
|
||||
printf("\ndump_dev()\n"); |
||||
printf(" rx_dq.base %p\n", priv->rx_dq.base); |
||||
printf(" rx_dq.current %p\n", priv->rx_dq.current); |
||||
printf(" rx_dq.end %p\n", priv->rx_dq.end); |
||||
printf(" rx_sq.base %p\n", priv->rx_sq.base); |
||||
printf(" rx_sq.current %p\n", priv->rx_sq.current); |
||||
printf(" rx_sq.end %p\n", priv->rx_sq.end); |
||||
|
||||
for (i = 0; i < NUMRXDESC; i++) |
||||
printf(" rx_buffer[%2.d] %p\n", i, NetRxPackets[i]); |
||||
|
||||
printf(" tx_dq.base %p\n", priv->tx_dq.base); |
||||
printf(" tx_dq.current %p\n", priv->tx_dq.current); |
||||
printf(" tx_dq.end %p\n", priv->tx_dq.end); |
||||
printf(" tx_sq.base %p\n", priv->tx_sq.base); |
||||
printf(" tx_sq.current %p\n", priv->tx_sq.current); |
||||
printf(" tx_sq.end %p\n", priv->tx_sq.end); |
||||
} |
||||
|
||||
/**
|
||||
* Dump all RX status queue entries to the terminal. |
||||
*/ |
||||
static void dump_rx_status_queue(struct eth_device *dev) |
||||
{ |
||||
struct ep93xx_priv *priv = GET_PRIV(dev); |
||||
int i; |
||||
|
||||
printf("\ndump_rx_status_queue()\n"); |
||||
printf(" descriptor address word1 word2\n"); |
||||
for (i = 0; i < NUMRXDESC; i++) { |
||||
printf(" [ %p ] %08X %08X\n", |
||||
priv->rx_sq.base + i, |
||||
(priv->rx_sq.base + i)->word1, |
||||
(priv->rx_sq.base + i)->word2); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* Dump all RX descriptor queue entries to the terminal. |
||||
*/ |
||||
static void dump_rx_descriptor_queue(struct eth_device *dev) |
||||
{ |
||||
struct ep93xx_priv *priv = GET_PRIV(dev); |
||||
int i; |
||||
|
||||
printf("\ndump_rx_descriptor_queue()\n"); |
||||
printf(" descriptor address word1 word2\n"); |
||||
for (i = 0; i < NUMRXDESC; i++) { |
||||
printf(" [ %p ] %08X %08X\n", |
||||
priv->rx_dq.base + i, |
||||
(priv->rx_dq.base + i)->word1, |
||||
(priv->rx_dq.base + i)->word2); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* Dump all TX descriptor queue entries to the terminal. |
||||
*/ |
||||
static void dump_tx_descriptor_queue(struct eth_device *dev) |
||||
{ |
||||
struct ep93xx_priv *priv = GET_PRIV(dev); |
||||
int i; |
||||
|
||||
printf("\ndump_tx_descriptor_queue()\n"); |
||||
printf(" descriptor address word1 word2\n"); |
||||
for (i = 0; i < NUMTXDESC; i++) { |
||||
printf(" [ %p ] %08X %08X\n", |
||||
priv->tx_dq.base + i, |
||||
(priv->tx_dq.base + i)->word1, |
||||
(priv->tx_dq.base + i)->word2); |
||||
} |
||||
} |
||||
|
||||
/**
|
||||
* Dump all TX status queue entries to the terminal. |
||||
*/ |
||||
static void dump_tx_status_queue(struct eth_device *dev) |
||||
{ |
||||
struct ep93xx_priv *priv = GET_PRIV(dev); |
||||
int i; |
||||
|
||||
printf("\ndump_tx_status_queue()\n"); |
||||
printf(" descriptor address word1\n"); |
||||
for (i = 0; i < NUMTXDESC; i++) { |
||||
printf(" [ %p ] %08X\n", |
||||
priv->rx_sq.base + i, |
||||
(priv->rx_sq.base + i)->word1); |
||||
} |
||||
} |
||||
#else |
||||
#define dump_dev(x) |
||||
#define dump_rx_descriptor_queue(x) |
||||
#define dump_rx_status_queue(x) |
||||
#define dump_tx_descriptor_queue(x) |
||||
#define dump_tx_status_queue(x) |
||||
#endif /* defined(EP93XX_MAC_DEBUG) */ |
||||
|
||||
/**
|
||||
* Reset the EP93xx MAC by twiddling the soft reset bit and spinning until |
||||
* it's cleared. |
||||
*/ |
||||
static void ep93xx_mac_reset(struct eth_device *dev) |
||||
{ |
||||
struct mac_regs *mac = GET_REGS(dev); |
||||
uint32_t value; |
||||
|
||||
debug("+ep93xx_mac_reset"); |
||||
|
||||
value = readl(&mac->selfctl); |
||||
value |= SELFCTL_RESET; |
||||
writel(value, &mac->selfctl); |
||||
|
||||
while (readl(&mac->selfctl) & SELFCTL_RESET) |
||||
; /* noop */ |
||||
|
||||
debug("-ep93xx_mac_reset"); |
||||
} |
||||
|
||||
/* Eth device open */ |
||||
static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd) |
||||
{ |
||||
struct ep93xx_priv *priv = GET_PRIV(dev); |
||||
struct mac_regs *mac = GET_REGS(dev); |
||||
uchar *mac_addr = dev->enetaddr; |
||||
int i; |
||||
|
||||
debug("+ep93xx_eth_open"); |
||||
|
||||
/* Reset the MAC */ |
||||
ep93xx_mac_reset(dev); |
||||
|
||||
/* Reset the descriptor queues' current and end address values */ |
||||
priv->tx_dq.current = priv->tx_dq.base; |
||||
priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC); |
||||
|
||||
priv->tx_sq.current = priv->tx_sq.base; |
||||
priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC); |
||||
|
||||
priv->rx_dq.current = priv->rx_dq.base; |
||||
priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC); |
||||
|
||||
priv->rx_sq.current = priv->rx_sq.base; |
||||
priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC); |
||||
|
||||
/*
|
||||
* Set the transmit descriptor and status queues' base address, |
||||
* current address, and length registers. Set the maximum frame |
||||
* length and threshold. Enable the transmit descriptor processor. |
||||
*/ |
||||
writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd); |
||||
writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd); |
||||
writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen); |
||||
|
||||
writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd); |
||||
writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd); |
||||
writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen); |
||||
|
||||
writel(0x00040000, &mac->txdthrshld); |
||||
writel(0x00040000, &mac->txststhrshld); |
||||
|
||||
writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen); |
||||
writel(BMCTL_TXEN, &mac->bmctl); |
||||
|
||||
/*
|
||||
* Set the receive descriptor and status queues' base address, |
||||
* current address, and length registers. Enable the receive |
||||
* descriptor processor. |
||||
*/ |
||||
writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd); |
||||
writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd); |
||||
writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen); |
||||
|
||||
writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd); |
||||
writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd); |
||||
writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen); |
||||
|
||||
writel(0x00040000, &mac->rxdthrshld); |
||||
|
||||
writel(BMCTL_RXEN, &mac->bmctl); |
||||
|
||||
writel(0x00040000, &mac->rxststhrshld); |
||||
|
||||
/* Wait until the receive descriptor processor is active */ |
||||
while (!(readl(&mac->bmsts) & BMSTS_RXACT)) |
||||
; /* noop */ |
||||
|
||||
/*
|
||||
* Initialize the RX descriptor queue. Clear the TX descriptor queue. |
||||
* Clear the RX and TX status queues. Enqueue the RX descriptor and |
||||
* status entries to the MAC. |
||||
*/ |
||||
for (i = 0; i < NUMRXDESC; i++) { |
||||
/* set buffer address */ |
||||
(priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i]; |
||||
|
||||
/* set buffer length, clear buffer index and NSOF */ |
||||
(priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN; |
||||
} |
||||
|
||||
memset(priv->tx_dq.base, 0, |
||||
(sizeof(struct tx_descriptor) * NUMTXDESC)); |
||||
memset(priv->rx_sq.base, 0, |
||||
(sizeof(struct rx_status) * NUMRXDESC)); |
||||
memset(priv->tx_sq.base, 0, |
||||
(sizeof(struct tx_status) * NUMTXDESC)); |
||||
|
||||
writel(NUMRXDESC, &mac->rxdqenq); |
||||
writel(NUMRXDESC, &mac->rxstsqenq); |
||||
|
||||
/* Set the primary MAC address */ |
||||
writel(AFP_IAPRIMARY, &mac->afp); |
||||
writel(mac_addr[0] | (mac_addr[1] << 8) | |
||||
(mac_addr[2] << 16) | (mac_addr[3] << 24), |
||||
&mac->indad); |
||||
writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper); |
||||
|
||||
/* Turn on RX and TX */ |
||||
writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON | |
||||
RXCTL_RCRCA | RXCTL_MA, &mac->rxctl); |
||||
writel(TXCTL_STXON, &mac->txctl); |
||||
|
||||
/* Dump data structures if we're debugging */ |
||||
dump_dev(dev); |
||||
dump_rx_descriptor_queue(dev); |
||||
dump_rx_status_queue(dev); |
||||
dump_tx_descriptor_queue(dev); |
||||
dump_tx_status_queue(dev); |
||||
|
||||
debug("-ep93xx_eth_open"); |
||||
|
||||
return 1; |
||||
} |
||||
|
||||
/**
|
||||
* Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL |
||||
* registers. |
||||
*/ |
||||
static void ep93xx_eth_close(struct eth_device *dev) |
||||
{ |
||||
struct mac_regs *mac = GET_REGS(dev); |
||||
|
||||
debug("+ep93xx_eth_close"); |
||||
|
||||
writel(0x00000000, &mac->rxctl); |
||||
writel(0x00000000, &mac->txctl); |
||||
|
||||
debug("-ep93xx_eth_close"); |
||||
} |
||||
|
||||
/**
|
||||
* Copy a frame of data from the MAC into the protocol layer for further |
||||
* processing. |
||||
*/ |
||||
static int ep93xx_eth_rcv_packet(struct eth_device *dev) |
||||
{ |
||||
struct mac_regs *mac = GET_REGS(dev); |
||||
struct ep93xx_priv *priv = GET_PRIV(dev); |
||||
int len = -1; |
||||
|
||||
debug("+ep93xx_eth_rcv_packet"); |
||||
|
||||
if (RX_STATUS_RFP(priv->rx_sq.current)) { |
||||
if (RX_STATUS_RWE(priv->rx_sq.current)) { |
||||
/*
|
||||
* We have a good frame. Extract the frame's length |
||||
* from the current rx_status_queue entry, and copy |
||||
* the frame's data into NetRxPackets[] of the |
||||
* protocol stack. We track the total number of |
||||
* bytes in the frame (nbytes_frame) which will be |
||||
* used when we pass the data off to the protocol |
||||
* layer via NetReceive(). |
||||
*/ |
||||
len = RX_STATUS_FRAME_LEN(priv->rx_sq.current); |
||||
|
||||
NetReceive((uchar *)priv->rx_dq.current->word1, len); |
||||
|
||||
debug("reporting %d bytes...\n", len); |
||||
} else { |
||||
/* Do we have an erroneous packet? */ |
||||
error("packet rx error, status %08X %08X", |
||||
priv->rx_sq.current->word1, |
||||
priv->rx_sq.current->word2); |
||||
dump_rx_descriptor_queue(dev); |
||||
dump_rx_status_queue(dev); |
||||
} |
||||
|
||||
/*
|
||||
* Clear the associated status queue entry, and |
||||
* increment our current pointers to the next RX |
||||
* descriptor and status queue entries (making sure |
||||
* we wrap properly). |
||||
*/ |
||||
memset((void *)priv->rx_sq.current, 0, |
||||
sizeof(struct rx_status)); |
||||
|
||||
priv->rx_sq.current++; |
||||
if (priv->rx_sq.current >= priv->rx_sq.end) |
||||
priv->rx_sq.current = priv->rx_sq.base; |
||||
|
||||
priv->rx_dq.current++; |
||||
if (priv->rx_dq.current >= priv->rx_dq.end) |
||||
priv->rx_dq.current = priv->rx_dq.base; |
||||
|
||||
/*
|
||||
* Finally, return the RX descriptor and status entries |
||||
* back to the MAC engine, and loop again, checking for |
||||
* more descriptors to process. |
||||
*/ |
||||
writel(1, &mac->rxdqenq); |
||||
writel(1, &mac->rxstsqenq); |
||||
} else { |
||||
len = 0; |
||||
} |
||||
|
||||
debug("-ep93xx_eth_rcv_packet %d", len); |
||||
return len; |
||||
} |
||||
|
||||
/**
|
||||
* Send a block of data via ethernet. |
||||
*/ |
||||
static int ep93xx_eth_send_packet(struct eth_device *dev, |
||||
volatile void * const packet, int const length) |
||||
{ |
||||
struct mac_regs *mac = GET_REGS(dev); |
||||
struct ep93xx_priv *priv = GET_PRIV(dev); |
||||
int ret = -1; |
||||
|
||||
debug("+ep93xx_eth_send_packet"); |
||||
|
||||
/* Parameter check */ |
||||
BUG_ON(packet == NULL); |
||||
|
||||
/*
|
||||
* Initialize the TX descriptor queue with the new packet's info. |
||||
* Clear the associated status queue entry. Enqueue the packet |
||||
* to the MAC for transmission. |
||||
*/ |
||||
|
||||
/* set buffer address */ |
||||
priv->tx_dq.current->word1 = (uint32_t)packet; |
||||
|
||||
/* set buffer length and EOF bit */ |
||||
priv->tx_dq.current->word2 = length | TX_DESC_EOF; |
||||
|
||||
/* clear tx status */ |
||||
priv->tx_sq.current->word1 = 0; |
||||
|
||||
/* enqueue the TX descriptor */ |
||||
writel(1, &mac->txdqenq); |
||||
|
||||
/* wait for the frame to become processed */ |
||||
while (!TX_STATUS_TXFP(priv->tx_sq.current)) |
||||
; /* noop */ |
||||
|
||||
if (!TX_STATUS_TXWE(priv->tx_sq.current)) { |
||||
error("packet tx error, status %08X", |
||||
priv->tx_sq.current->word1); |
||||
dump_tx_descriptor_queue(dev); |
||||
dump_tx_status_queue(dev); |
||||
|
||||
/* TODO: Add better error handling? */ |
||||
goto eth_send_out; |
||||
} |
||||
|
||||
ret = 0; |
||||
/* Fall through */ |
||||
|
||||
eth_send_out: |
||||
debug("-ep93xx_eth_send_packet %d", ret); |
||||
return ret; |
||||
} |
||||
|
||||
#if defined(CONFIG_MII) |
||||
int ep93xx_miiphy_initialize(bd_t * const bd) |
||||
{ |
||||
miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
/**
|
||||
* Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are |
||||
* allocated, if necessary, for the TX and RX descriptor and status queues, |
||||
* as well as for received packets. The EP93XX MAC hardware is initialized. |
||||
* Transmit and receive operations are enabled. |
||||
*/ |
||||
int ep93xx_eth_initialize(u8 dev_num, int base_addr) |
||||
{ |
||||
int ret = -1; |
||||
struct eth_device *dev; |
||||
struct ep93xx_priv *priv; |
||||
|
||||
debug("+ep93xx_eth_initialize"); |
||||
|
||||
priv = malloc(sizeof(*priv)); |
||||
if (!priv) { |
||||
error("malloc() failed"); |
||||
goto eth_init_failed_0; |
||||
} |
||||
memset(priv, 0, sizeof(*priv)); |
||||
|
||||
priv->regs = (struct mac_regs *)base_addr; |
||||
|
||||
priv->tx_dq.base = calloc(NUMTXDESC, |
||||
sizeof(struct tx_descriptor)); |
||||
if (priv->tx_dq.base == NULL) { |
||||
error("calloc() failed"); |
||||
goto eth_init_failed_1; |
||||
} |
||||
|
||||
priv->tx_sq.base = calloc(NUMTXDESC, |
||||
sizeof(struct tx_status)); |
||||
if (priv->tx_sq.base == NULL) { |
||||
error("calloc() failed"); |
||||
goto eth_init_failed_2; |
||||
} |
||||
|
||||
priv->rx_dq.base = calloc(NUMRXDESC, |
||||
sizeof(struct rx_descriptor)); |
||||
if (priv->rx_dq.base == NULL) { |
||||
error("calloc() failed"); |
||||
goto eth_init_failed_3; |
||||
} |
||||
|
||||
priv->rx_sq.base = calloc(NUMRXDESC, |
||||
sizeof(struct rx_status)); |
||||
if (priv->rx_sq.base == NULL) { |
||||
error("calloc() failed"); |
||||
goto eth_init_failed_4; |
||||
} |
||||
|
||||
dev = malloc(sizeof *dev); |
||||
if (dev == NULL) { |
||||
error("malloc() failed"); |
||||
goto eth_init_failed_5; |
||||
} |
||||
memset(dev, 0, sizeof *dev); |
||||
|
||||
dev->iobase = base_addr; |
||||
dev->priv = priv; |
||||
dev->init = ep93xx_eth_open; |
||||
dev->halt = ep93xx_eth_close; |
||||
dev->send = ep93xx_eth_send_packet; |
||||
dev->recv = ep93xx_eth_rcv_packet; |
||||
|
||||
sprintf(dev->name, "ep93xx_eth-%hu", dev_num); |
||||
|
||||
eth_register(dev); |
||||
|
||||
/* Done! */ |
||||
ret = 1; |
||||
goto eth_init_done; |
||||
|
||||
eth_init_failed_5: |
||||
free(priv->rx_sq.base); |
||||
/* Fall through */ |
||||
|
||||
eth_init_failed_4: |
||||
free(priv->rx_dq.base); |
||||
/* Fall through */ |
||||
|
||||
eth_init_failed_3: |
||||
free(priv->tx_sq.base); |
||||
/* Fall through */ |
||||
|
||||
eth_init_failed_2: |
||||
free(priv->tx_dq.base); |
||||
/* Fall through */ |
||||
|
||||
eth_init_failed_1: |
||||
free(priv); |
||||
/* Fall through */ |
||||
|
||||
eth_init_failed_0: |
||||
/* Fall through */ |
||||
|
||||
eth_init_done: |
||||
debug("-ep93xx_eth_initialize %d", ret); |
||||
return ret; |
||||
} |
||||
|
||||
#if defined(CONFIG_MII) |
||||
|
||||
/**
|
||||
* Maximum MII address we support |
||||
*/ |
||||
#define MII_ADDRESS_MAX 31 |
||||
|
||||
/**
|
||||
* Maximum MII register address we support |
||||
*/ |
||||
#define MII_REGISTER_MAX 31 |
||||
|
||||
/**
|
||||
* Read a 16-bit value from an MII register. |
||||
*/ |
||||
static int ep93xx_miiphy_read(char * const dev, unsigned char const addr, |
||||
unsigned char const reg, unsigned short * const value) |
||||
{ |
||||
struct mac_regs *mac = (struct mac_regs *)MAC_BASE; |
||||
int ret = -1; |
||||
uint32_t self_ctl; |
||||
|
||||
debug("+ep93xx_miiphy_read"); |
||||
|
||||
/* Parameter checks */ |
||||
BUG_ON(dev == NULL); |
||||
BUG_ON(addr > MII_ADDRESS_MAX); |
||||
BUG_ON(reg > MII_REGISTER_MAX); |
||||
BUG_ON(value == NULL); |
||||
|
||||
/*
|
||||
* Save the current SelfCTL register value. Set MAC to suppress |
||||
* preamble bits. Wait for any previous MII command to complete |
||||
* before issuing the new command. |
||||
*/ |
||||
self_ctl = readl(&mac->selfctl); |
||||
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) |
||||
writel(self_ctl & ~(1 << 8), &mac->selfctl); |
||||
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ |
||||
|
||||
while (readl(&mac->miists) & MIISTS_BUSY) |
||||
; /* noop */ |
||||
|
||||
/*
|
||||
* Issue the MII 'read' command. Wait for the command to complete. |
||||
* Read the MII data value. |
||||
*/ |
||||
writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg, |
||||
&mac->miicmd); |
||||
while (readl(&mac->miists) & MIISTS_BUSY) |
||||
; /* noop */ |
||||
|
||||
*value = (unsigned short)readl(&mac->miidata); |
||||
|
||||
/* Restore the saved SelfCTL value and return. */ |
||||
writel(self_ctl, &mac->selfctl); |
||||
|
||||
ret = 0; |
||||
/* Fall through */ |
||||
|
||||
debug("-ep93xx_miiphy_read"); |
||||
return ret; |
||||
} |
||||
|
||||
/**
|
||||
* Write a 16-bit value to an MII register. |
||||
*/ |
||||
static int ep93xx_miiphy_write(char * const dev, unsigned char const addr, |
||||
unsigned char const reg, unsigned short const value) |
||||
{ |
||||
struct mac_regs *mac = (struct mac_regs *)MAC_BASE; |
||||
int ret = -1; |
||||
uint32_t self_ctl; |
||||
|
||||
debug("+ep93xx_miiphy_write"); |
||||
|
||||
/* Parameter checks */ |
||||
BUG_ON(dev == NULL); |
||||
BUG_ON(addr > MII_ADDRESS_MAX); |
||||
BUG_ON(reg > MII_REGISTER_MAX); |
||||
|
||||
/*
|
||||
* Save the current SelfCTL register value. Set MAC to suppress |
||||
* preamble bits. Wait for any previous MII command to complete |
||||
* before issuing the new command. |
||||
*/ |
||||
self_ctl = readl(&mac->selfctl); |
||||
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE) |
||||
writel(self_ctl & ~(1 << 8), &mac->selfctl); |
||||
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */ |
||||
|
||||
while (readl(&mac->miists) & MIISTS_BUSY) |
||||
; /* noop */ |
||||
|
||||
/* Issue the MII 'write' command. Wait for the command to complete. */ |
||||
writel((uint32_t)value, &mac->miidata); |
||||
writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg, |
||||
&mac->miicmd); |
||||
while (readl(&mac->miists) & MIISTS_BUSY) |
||||
; /* noop */ |
||||
|
||||
/* Restore the saved SelfCTL value and return. */ |
||||
writel(self_ctl, &mac->selfctl); |
||||
|
||||
ret = 0; |
||||
/* Fall through */ |
||||
|
||||
debug("-ep93xx_miiphy_write"); |
||||
return ret; |
||||
} |
||||
#endif /* defined(CONFIG_MII) */ |
||||
@ -0,0 +1,144 @@ |
||||
/*
|
||||
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> |
||||
* |
||||
* Copyright (C) 2004, 2005 |
||||
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _EP93XX_ETH_H |
||||
#define _EP93XX_ETH_H |
||||
|
||||
#include <net.h> |
||||
|
||||
/**
|
||||
* #define this to dump device status and queue info during initialization and |
||||
* following errors. |
||||
*/ |
||||
#undef EP93XX_MAC_DEBUG |
||||
|
||||
/**
|
||||
* Number of descriptor and status entries in our RX queues. |
||||
* It must be power of 2 ! |
||||
*/ |
||||
#define NUMRXDESC PKTBUFSRX |
||||
|
||||
/**
|
||||
* Number of descriptor and status entries in our TX queues. |
||||
*/ |
||||
#define NUMTXDESC 1 |
||||
|
||||
/**
|
||||
* 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT) |
||||
*/ |
||||
#define TXSTARTMAX 944 |
||||
|
||||
/**
|
||||
* Receive descriptor queue entry |
||||
*/ |
||||
struct rx_descriptor { |
||||
uint32_t word1; |
||||
uint32_t word2; |
||||
}; |
||||
|
||||
/**
|
||||
* Receive status queue entry |
||||
*/ |
||||
struct rx_status { |
||||
uint32_t word1; |
||||
uint32_t word2; |
||||
}; |
||||
|
||||
#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01) |
||||
#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01) |
||||
#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF) |
||||
|
||||
/**
|
||||
* Transmit descriptor queue entry |
||||
*/ |
||||
struct tx_descriptor { |
||||
uint32_t word1; |
||||
uint32_t word2; |
||||
}; |
||||
|
||||
#define TX_DESC_EOF (1 << 31) |
||||
|
||||
/**
|
||||
* Transmit status queue entry |
||||
*/ |
||||
struct tx_status { |
||||
uint32_t word1; |
||||
}; |
||||
|
||||
#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01) |
||||
#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01) |
||||
|
||||
/**
|
||||
* Transmit descriptor queue |
||||
*/ |
||||
struct tx_descriptor_queue { |
||||
struct tx_descriptor *base; |
||||
struct tx_descriptor *current; |
||||
struct tx_descriptor *end; |
||||
}; |
||||
|
||||
/**
|
||||
* Transmit status queue |
||||
*/ |
||||
struct tx_status_queue { |
||||
struct tx_status *base; |
||||
volatile struct tx_status *current; |
||||
struct tx_status *end; |
||||
}; |
||||
|
||||
/**
|
||||
* Receive descriptor queue |
||||
*/ |
||||
struct rx_descriptor_queue { |
||||
struct rx_descriptor *base; |
||||
struct rx_descriptor *current; |
||||
struct rx_descriptor *end; |
||||
}; |
||||
|
||||
/**
|
||||
* Receive status queue |
||||
*/ |
||||
struct rx_status_queue { |
||||
struct rx_status *base; |
||||
volatile struct rx_status *current; |
||||
struct rx_status *end; |
||||
}; |
||||
|
||||
/**
|
||||
* EP93xx MAC private data structure |
||||
*/ |
||||
struct ep93xx_priv { |
||||
struct rx_descriptor_queue rx_dq; |
||||
struct rx_status_queue rx_sq; |
||||
void *rx_buffer[NUMRXDESC]; |
||||
|
||||
struct tx_descriptor_queue tx_dq; |
||||
struct tx_status_queue tx_sq; |
||||
|
||||
struct mac_regs *regs; |
||||
}; |
||||
|
||||
#endif |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,145 @@ |
||||
/*
|
||||
* Memory Setup stuff - taken from blob memsetup.S |
||||
* |
||||
* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) |
||||
* |
||||
* based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC)) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef AT91_H |
||||
#define AT91_H |
||||
|
||||
typedef struct at91_emac { |
||||
u32 ctl; |
||||
u32 cfg; |
||||
u32 sr; |
||||
u32 tar; |
||||
u32 tcr; |
||||
u32 tsr; |
||||
u32 rbqp; |
||||
u32 reserved0; |
||||
u32 rsr; |
||||
u32 isr; |
||||
u32 ier; |
||||
u32 idr; |
||||
u32 imr; |
||||
u32 man; |
||||
u32 reserved1[2]; |
||||
u32 fra; |
||||
u32 scol; |
||||
u32 mocl; |
||||
u32 ok; |
||||
u32 seqe; |
||||
u32 ale; |
||||
u32 dte; |
||||
u32 lcol; |
||||
u32 ecol; |
||||
u32 cse; |
||||
u32 tue; |
||||
u32 cde; |
||||
u32 elr; |
||||
u32 rjb; |
||||
u32 usf; |
||||
u32 sqee; |
||||
u32 drfc; |
||||
u32 reserved2[3]; |
||||
u32 hsh; |
||||
u32 hsl; |
||||
u32 sh1l; |
||||
u32 sa1h; |
||||
u32 sa2l; |
||||
u32 sa2h; |
||||
u32 sa3l; |
||||
u32 sa3h; |
||||
u32 sa4l; |
||||
u32 sa4h; |
||||
} at91_emac_t; |
||||
|
||||
#define AT91_EMAC_CTL_LB 0x0001 |
||||
#define AT91_EMAC_CTL_LBL 0x0002 |
||||
#define AT91_EMAC_CTL_RE 0x0004 |
||||
#define AT91_EMAC_CTL_TE 0x0008 |
||||
#define AT91_EMAC_CTL_MPE 0x0010 |
||||
#define AT91_EMAC_CTL_CSR 0x0020 |
||||
#define AT91_EMAC_CTL_ISR 0x0040 |
||||
#define AT91_EMAC_CTL_WES 0x0080 |
||||
#define AT91_EMAC_CTL_BP 0x1000 |
||||
|
||||
#define AT91_EMAC_CFG_SPD 0x0001 |
||||
#define AT91_EMAC_CFG_FD 0x0002 |
||||
#define AT91_EMAC_CFG_BR 0x0004 |
||||
#define AT91_EMAC_CFG_CAF 0x0010 |
||||
#define AT91_EMAC_CFG_NBC 0x0020 |
||||
#define AT91_EMAC_CFG_MTI 0x0040 |
||||
#define AT91_EMAC_CFG_UNI 0x0080 |
||||
#define AT91_EMAC_CFG_BIG 0x0100 |
||||
#define AT91_EMAC_CFG_EAE 0x0200 |
||||
#define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF |
||||
#define AT91_EMAC_CFG_MCLK_8 0x0000 |
||||
#define AT91_EMAC_CFG_MCLK_16 0x0400 |
||||
#define AT91_EMAC_CFG_MCLK_32 0x0800 |
||||
#define AT91_EMAC_CFG_MCLK_64 0x0C00 |
||||
#define AT91_EMAC_CFG_RTY 0x1000 |
||||
#define AT91_EMAC_CFG_RMII 0x2000 |
||||
|
||||
#define AT91_EMAC_SR_LINK 0x0001 |
||||
#define AT91_EMAC_SR_MDIO 0x0002 |
||||
#define AT91_EMAC_SR_IDLE 0x0004 |
||||
|
||||
#define AT91_EMAC_TCR_LEN(x) (x & 0x7FF) |
||||
#define AT91_EMAC_TCR_NCRC 0x8000 |
||||
|
||||
#define AT91_EMAC_TSR_OVR 0x0001 |
||||
#define AT91_EMAC_TSR_COL 0x0002 |
||||
#define AT91_EMAC_TSR_RLE 0x0004 |
||||
#define AT91_EMAC_TSR_TXIDLE 0x0008 |
||||
#define AT91_EMAC_TSR_BNQ 0x0010 |
||||
#define AT91_EMAC_TSR_COMP 0x0020 |
||||
#define AT91_EMAC_TSR_UND 0x0040 |
||||
|
||||
#define AT91_EMAC_RSR_BNA 0x0001 |
||||
#define AT91_EMAC_RSR_REC 0x0002 |
||||
#define AT91_EMAC_RSR_OVR 0x0004 |
||||
|
||||
/* ISR, IER, IDR, IMR use the same bits */ |
||||
#define AT91_EMAC_IxR_DONE 0x0001 |
||||
#define AT91_EMAC_IxR_RCOM 0x0002 |
||||
#define AT91_EMAC_IxR_RBNA 0x0004 |
||||
#define AT91_EMAC_IxR_TOVR 0x0008 |
||||
#define AT91_EMAC_IxR_TUND 0x0010 |
||||
#define AT91_EMAC_IxR_RTRY 0x0020 |
||||
#define AT91_EMAC_IxR_TBRE 0x0040 |
||||
#define AT91_EMAC_IxR_TCOM 0x0080 |
||||
#define AT91_EMAC_IxR_TIDLE 0x0100 |
||||
#define AT91_EMAC_IxR_LINK 0x0200 |
||||
#define AT91_EMAC_IxR_ROVR 0x0400 |
||||
#define AT91_EMAC_IxR_HRESP 0x0800 |
||||
|
||||
#define AT91_EMAC_MAN_DATA_MASK 0xFFFF |
||||
#define AT91_EMAC_MAN_CODE_802_3 0x00020000 |
||||
#define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18) |
||||
#define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23) |
||||
#define AT91_EMAC_MAN_RW_R 0x20000000 |
||||
#define AT91_EMAC_MAN_RW_W 0x10000000 |
||||
#define AT91_EMAC_MAN_HIGH 0x40000000 |
||||
#define AT91_EMAC_MAN_LOW 0x80000000 |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue