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@ -2,12 +2,12 @@ |
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* File: include/asm-blackfin/mach-bf548/anomaly.h |
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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* |
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* Copyright (C) 2004-2007 Analog Devices Inc. |
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* Copyright (C) 2004-2008 Analog Devices Inc. |
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* Licensed under the GPL-2 or later. |
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*/ |
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/* This file shoule be up to date with:
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* - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
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* - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
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*/ |
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#ifndef _MACH_ANOMALY_H_ |
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@ -43,7 +43,7 @@ |
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#define ANOMALY_05000328 (__SILICON_REVISION__ < 1) |
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/* Synchronous Burst Flash Boot Mode Is Not Functional */ |
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#define ANOMALY_05000329 (__SILICON_REVISION__ < 1) |
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/* Host DMA Boot Mode Is Not Functional */ |
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/* Host DMA Boot Modes Are Not Functional */ |
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#define ANOMALY_05000330 (__SILICON_REVISION__ < 1) |
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/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */ |
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#define ANOMALY_05000334 (__SILICON_REVISION__ < 1) |
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@ -61,26 +61,90 @@ |
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#define ANOMALY_05000344 (__SILICON_REVISION__ < 1) |
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/* USB Calibration Value Is Not Intialized */ |
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#define ANOMALY_05000346 (__SILICON_REVISION__ < 1) |
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/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */ |
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/* Preboot Routine Incorrectly Alters Reset Value of USB Register */ |
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#define ANOMALY_05000347 (__SILICON_REVISION__ < 1) |
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/* Data Lost when Core Reads SDH Data FIFO */ |
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#define ANOMALY_05000349 (__SILICON_REVISION__ < 1) |
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/* PLL Status Register Is Inaccurate */ |
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#define ANOMALY_05000351 (__SILICON_REVISION__ < 1) |
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/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ |
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#define ANOMALY_05000353 (1) |
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
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#define ANOMALY_05000355 (__SILICON_REVISION__ < 1) |
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/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ |
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#define ANOMALY_05000356 (__SILICON_REVISION__ < 1) |
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
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#define ANOMALY_05000357 (1) |
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/* External Memory Read Access Hangs Core With PLL Bypass */ |
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#define ANOMALY_05000360 (1) |
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/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */ |
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#define ANOMALY_05000365 (1) |
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/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */ |
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#define ANOMALY_05000367 (__SILICON_REVISION__ < 1) |
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/* Addressing Conflict between Boot ROM and Asynchronous Memory */ |
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#define ANOMALY_05000369 (1) |
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/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ |
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#define ANOMALY_05000370 (__SILICON_REVISION__ < 1) |
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/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
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#define ANOMALY_05000371 (__SILICON_REVISION__ < 1) |
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#define ANOMALY_05000371 (1) |
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/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ |
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#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) |
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/* Mobile DDR Operation Not Functional */ |
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#define ANOMALY_05000377 (1) |
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/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ |
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#define ANOMALY_05000378 (1) |
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/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ |
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#define ANOMALY_05000379 (1) |
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/* 8-Bit NAND Flash Boot Mode Not Functional */ |
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#define ANOMALY_05000382 (__SILICON_REVISION__ < 1) |
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/* Some ATAPI Modes Are Not Functional */ |
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#define ANOMALY_05000383 (1) |
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/* Boot from OTP Memory Not Functional */ |
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#define ANOMALY_05000385 (__SILICON_REVISION__ < 1) |
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/* bfrom_SysControl() Firmware Routine Not Functional */ |
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#define ANOMALY_05000386 (__SILICON_REVISION__ < 1) |
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/* Programmable Preboot Settings Not Functional */ |
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#define ANOMALY_05000387 (__SILICON_REVISION__ < 1) |
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/* CRC32 Checksum Support Not Functional */ |
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#define ANOMALY_05000388 (__SILICON_REVISION__ < 1) |
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/* Reset Vector Must Not Be in SDRAM Memory Space */ |
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#define ANOMALY_05000389 (__SILICON_REVISION__ < 1) |
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/* Changed Meaning of BCODE Field in SYSCR Register */ |
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#define ANOMALY_05000390 (__SILICON_REVISION__ < 1) |
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/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */ |
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#define ANOMALY_05000391 (__SILICON_REVISION__ < 1) |
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/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ |
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#define ANOMALY_05000392 (__SILICON_REVISION__ < 1) |
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/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ |
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#define ANOMALY_05000393 (__SILICON_REVISION__ < 1) |
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/* Log Buffer Not Functional */ |
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#define ANOMALY_05000394 (__SILICON_REVISION__ < 1) |
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/* Hook Routine Not Functional */ |
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#define ANOMALY_05000395 (__SILICON_REVISION__ < 1) |
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/* Header Indirect Bit Not Functional */ |
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#define ANOMALY_05000396 (__SILICON_REVISION__ < 1) |
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/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ |
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#define ANOMALY_05000397 (__SILICON_REVISION__ < 1) |
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/* Lockbox SESR Disallows Certain User Interrupts */ |
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#define ANOMALY_05000404 (1) |
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/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ |
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#define ANOMALY_05000405 (1) |
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/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ |
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#define ANOMALY_05000406 (1) |
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/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ |
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#define ANOMALY_05000407 (1) |
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/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ |
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#define ANOMALY_05000408 (1) |
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/* Lockbox firmware leaves MDMA0 channel enabled */ |
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#define ANOMALY_05000409 (1) |
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/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ |
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#define ANOMALY_05000411 (1) |
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/* FIFO Boot Mode Is Not Functional */ |
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#define ANOMALY_05000412 (1) |
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/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ |
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#define ANOMALY_05000413 (1) |
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/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ |
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#define ANOMALY_05000414 (1) |
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/* Anomalies that don't exist on this proc */ |
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#define ANOMALY_05000125 (0) |
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@ -93,7 +157,9 @@ |
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#define ANOMALY_05000263 (0) |
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#define ANOMALY_05000266 (0) |
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#define ANOMALY_05000273 (0) |
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#define ANOMALY_05000307 (0) |
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#define ANOMALY_05000311 (0) |
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#define ANOMALY_05000323 (0) |
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#define ANOMALY_05000363 (0) |
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#endif |
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