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@ -101,7 +101,9 @@ int miiphy_read (unsigned char addr, unsigned char reg, |
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sta_reg = reg; /* reg address */ |
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/* set clock (50Mhz) and read flags */ |
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sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; |
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#ifdef CONFIG_PHY_CLK_FREQ |
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sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; |
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#endif |
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sta_reg = sta_reg | (addr << 5); /* Phy address */ |
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out32 (EMAC_STACR, sta_reg); |
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@ -157,7 +159,9 @@ int miiphy_write (unsigned char addr, unsigned char reg, |
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sta_reg = reg; /* reg address */ |
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/* set clock (50Mhz) and read flags */ |
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sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; |
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#ifdef CONFIG_PHY_CLK_FREQ |
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sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ |
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#endif |
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sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */ |
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memcpy (&sta_reg, &value, 2); /* put in data */ |
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