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@ -34,21 +34,21 @@ |
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*/ |
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
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#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ |
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/* ...and on a SYCAMORE board */ |
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
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#define CONFIG_WALNUT 1 /* ...on a WALNUT board */ |
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/* ...and on a SYCAMORE board */ |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
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#define CONFIG_PREBOOT "echo;" \ |
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#define CONFIG_PREBOOT "echo;" \ |
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo" |
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#undef CONFIG_BOOTARGS |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"netdev=eth0\0" \
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"hostname=walnut\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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@ -62,15 +62,15 @@ |
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"bootm $(kernel_addr)\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm $(kernel_addr) $(ramdisk_addr)\0" \
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"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
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"bootm\0" \
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"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/walnut/uImage\0" \
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"kernel_addr=fff80000\0" \
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"ramdisk_addr=fff80000\0" \
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"load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
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"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
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"cp.b 100000 fffc0000 40000;" \
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"cp.b 100000 fffc0000 40000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load;run update\0" \
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"" |
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@ -88,7 +88,7 @@ |
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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#define CONFIG_MII 1 /* MII PHY management */ |
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#define CONFIG_PHY_ADDR 1 /* PHY address */ |
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#define CONFIG_PHY_ADDR 1 /* PHY address */ |
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#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ |
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@ -105,7 +105,7 @@ |
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_SNTP ) |
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@ -122,9 +122,9 @@ |
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#define CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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@ -143,9 +143,9 @@ |
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* set Linux BASE_BAUD to 403200. |
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*/ |
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#undef CONFIG_SERIAL_SOFTWARE_FIFO |
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
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#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
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#define CFG_BASE_BAUD 691200 |
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ |
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#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
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#define CFG_BASE_BAUD 691200 |
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/* The following table includes the supported baudrates */ |
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#define CFG_BAUDRATE_TABLE \ |
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@ -154,10 +154,10 @@ |
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#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
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#define CONFIG_LOOPW 1 /* enable loopw command */ |
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#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
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#define CONFIG_LOOPW 1 /* enable loopw command */ |
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
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@ -168,7 +168,7 @@ |
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*----------------------------------------------------------------------- |
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*/ |
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
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#define CFG_I2C_SLAVE 0x7F |
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@ -176,24 +176,24 @@ |
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* PCI stuff |
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*----------------------------------------------------------------------- |
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*/ |
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
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#define PCI_HOST_FORCE 1 /* configure as pci host */ |
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
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#define CONFIG_PCI /* include pci support */ |
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
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#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
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/* resource configuration */ |
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
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#define PCI_HOST_FORCE 1 /* configure as pci host */ |
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
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#define CONFIG_PCI /* include pci support */ |
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
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#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
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/* resource configuration */ |
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
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#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ |
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ |
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ |
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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@ -209,10 +209,10 @@ |
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/*
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* Define here the location of the environment variables (FLASH or NVRAM). |
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* Note: DENX encourages to use redundant environment in FLASH. NVRAM is only |
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* supported for backward compatibility. |
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* supported for backward compatibility. |
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*/ |
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#if 1 |
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
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#else |
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#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
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#endif |
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@ -227,8 +227,8 @@ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ |
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#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ |
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
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@ -238,14 +238,14 @@ |
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
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#define CFG_FLASH_ADDR0 0x5555 |
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#define CFG_FLASH_ADDR1 0x2aaa |
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#define CFG_FLASH_WORD_SIZE unsigned char |
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#define CFG_FLASH_ADDR0 0x5555 |
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#define CFG_FLASH_ADDR1 0x2aaa |
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#define CFG_FLASH_WORD_SIZE unsigned char |
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#ifdef CFG_ENV_IS_IN_FLASH |
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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/* Address and size of Redundant Environment Sector */ |
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) |
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@ -280,44 +280,44 @@ |
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/* Memory Bank 0 (Flash Bank 0) initialization */ |
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#define CFG_EBC_PB0AP 0x9B015480 |
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#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB1AP 0x02815480 |
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#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB2AP 0x04815A80 |
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#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB3AP 0x01815280 |
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#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB7AP 0x01815280 |
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#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ |
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#define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ |
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/*-----------------------------------------------------------------------
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* External peripheral base address |
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*----------------------------------------------------------------------- |
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*/ |
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#define CFG_KEY_REG_BASE_ADDR 0xF0100000 |
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#define CFG_IR_REG_BASE_ADDR 0xF0200000 |
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#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 |
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#define CFG_KEY_REG_BASE_ADDR 0xF0100000 |
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#define CFG_IR_REG_BASE_ADDR 0xF0200000 |
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#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area |
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*/ |
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#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ |
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#define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */ |
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#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ |
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
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#define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */ |
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#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Definitions for Serial Presence Detect EEPROM address |
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* (to get SDRAM settings) |
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*/ |
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#define SPD_EEPROM_ADDRESS 0x50 |
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#define SPD_EEPROM_ADDRESS 0x50 |
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/*
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* Internal Definitions |
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Wolfgang Denk
19 years ago