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EXYNOS5: CLOCK: Add BPLL support

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This patch adds support for BPLL clock.

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
master
Rajeshwari Shinde 13 years ago committed by Albert ARIBAUD
parent 6071bcaec1
commit 10bc1a7f49
3 changed files with 24 additions and 7 deletions
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  1. 26
      arch/arm/cpu/armv7/exynos/clock.c
  2. 1
      arch/arm/include/asm/arch-exynos/clk.h
  3. 2
      arch/arm/include/asm/arch-exynos/clock.h

26
arch/arm/cpu/armv7/exynos/clock.c
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@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
struct exynos5_clock *clk = struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock(); (struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout; unsigned long r, m, p, s, k = 0, mask, fout;
unsigned int freq, pll_div2_sel, mpll_fout_sel; unsigned int freq, pll_div2_sel, fout_sel;
switch (pllreg) { switch (pllreg) {
case APLL: case APLL:
@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
r = readl(&clk->vpll_con0); r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1); k = readl(&clk->vpll_con1);
break; break;
case BPLL:
r = readl(&clk->bpll_con0);
break;
default: default:
printf("Unsupported PLL (%d)\n", pllreg); printf("Unsupported PLL (%d)\n", pllreg);
return 0; return 0;
@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
* MPLL_CON: MIDV [25:16] * MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16] * EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16]
* BPLL_CON: MIDV [25:16]
*/ */
if (pllreg == APLL || pllreg == MPLL) if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff; mask = 0x3ff;
else else
mask = 0x1ff; mask = 0x1ff;
@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
fout = m * (freq / (p * (1 << (s - 1)))); fout = m * (freq / (p * (1 << (s - 1))));
} }
/* According to the user manual, in EVT1 MPLL always gives /* According to the user manual, in EVT1 MPLL and BPLL always gives
* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/ * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
if (pllreg == MPLL) { if (pllreg == MPLL || pllreg == BPLL) {
pll_div2_sel = readl(&clk->pll_div2_sel); pll_div2_sel = readl(&clk->pll_div2_sel);
mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
switch (pllreg) {
case MPLL:
fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
& MPLL_FOUT_SEL_MASK; & MPLL_FOUT_SEL_MASK;
if (mpll_fout_sel == 0) break;
case BPLL:
fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
& BPLL_FOUT_SEL_MASK;
break;
}
if (fout_sel == 0)
fout /= 2; fout /= 2;
} }

1
arch/arm/include/asm/arch-exynos/clk.h
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@ -27,6 +27,7 @@
#define EPLL 2 #define EPLL 2
#define HPLL 3 #define HPLL 3
#define VPLL 4 #define VPLL 4
#define BPLL 5
unsigned long get_pll_clk(int pllreg); unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void); unsigned long get_arm_clk(void);

2
arch/arm/include/asm/arch-exynos/clock.h
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@ -599,4 +599,6 @@ struct exynos5_clock {
#define MPLL_FOUT_SEL_SHIFT 4 #define MPLL_FOUT_SEL_SHIFT 4
#define MPLL_FOUT_SEL_MASK 0x1 #define MPLL_FOUT_SEL_MASK 0x1
#define BPLL_FOUT_SEL_SHIFT 0
#define BPLL_FOUT_SEL_MASK 0x1
#endif #endif

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