Merge branch 'master' of /home/wd/git/u-boot/custodians

* 'master' of /home/wd/git/u-boot/custodians:
  powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND
  arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning
  drivers/qe/uec.c: Fix GCC 4.6 build warning
  drivers/usb/host/ehci-fsl.c: Fix GCC 4.6 build warning
  drivers/net/fm/fm.c: Fix GCC 4.6 build warning
  board/sbc8560/sbc8560.c: Fix GCC 4.6 build warning
  board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning
  board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning
  board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning
  board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning
  board/freescale/common/pixis.c: Fix GCC 4.6 build warning
  board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning
  phylib: Enable AR8021 phy support
  powerpc/85xx: Set max alloc length to 10MB on P1022DS
  powerpc/mpc85xx: Set SYSCLK to the required frequency
  powerpc/85xx: Fix NAND SPL support
  powerpc/85xx: Fix MPC8572DS NAND build
  fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399
  powerpc/85xx: Add support for Book-E MMU Arch v2.0
  powerpc/85xx: Make inclusion of USB device fixup conditional
  powerpc/85xx: Fix warning for USB device-fixup
  powerpc/85xx: resize the boot page TLB before relocating CCSR
  powerpc/85xx: verify the current address of CCSR before relocating it
  powerpc/85xx: add some missing sync instructions in the CCSR relocation code
  powerpc/85xx: fix some comments in the CCSR relocation code
  powerpc/85xx: fix definition of MAS register macros
  powerpc/mpc8548cds: Fix network initialization
  powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129
  powerpc/QorIQ: fix network frame manager TBI PHY address settings

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -103,6 +103,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 	puts("Work-around for Erratum NMG_LBC103 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
+#endif
 	return 0;
 }
 

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -317,7 +317,6 @@ int cpu_init_r(void)
 	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;
 	uint svr, ver;
-	uint l2srbar;
 	u32 l2siz_field;
 
 	svr = get_svr();
@@ -385,8 +384,8 @@ int cpu_init_r(void)
 
 	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 		puts("already enabled");
-		l2srbar = l2cache->l2srbar0;
 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
+		u32 l2srbar = l2cache->l2srbar0;
 		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
 			l2srbar = CONFIG_SYS_INIT_L2_ADDR;

arch/powerpc/cpu/mpc85xx/cpu_init_early.c

@@ -71,7 +71,7 @@ void cpu_init_early_f(void)
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
-	u32  *l2srbar, *dst, *src;
+	u32  *dst, *src;
 	void (*setup_ifc_sram)(void);
 #endif
 
@@ -137,7 +137,7 @@ void cpu_init_early_f(void)
 	dst = (u32 *) SRAM_BASE_ADDR;
 	src = (u32 *) setup_ifc;
 	for (i = 0; i < 1024; i++)
-		*l2srbar++ = *src++;
+		*dst++ = *src++;
 
 	setup_ifc_sram();
 

arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c

@@ -495,7 +495,6 @@ void fsl_serdes_init(void)
 	int cfg;
 	serdes_corenet_t *srds_regs;
 	int lane, bank, idx;
-	enum srds_prtcl lane_prtcl;
 	int have_bank[SRDS_MAX_BANK] = {};
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	u32 serdes8_devdisr = 0;
@@ -507,6 +506,7 @@ void fsl_serdes_init(void)
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 	int need_serdes_a001;	/* TRUE == need work-around for SERDES A001 */
 #endif
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char *buf = NULL;
 
@@ -516,6 +516,7 @@ void fsl_serdes_init(void)
 	 */
 	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 		buf = buffer;
+#endif
 
 	/* Is serdes enabled at all? */
 	if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -617,7 +618,10 @@ void fsl_serdes_init(void)
 		}
 	}
 
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl;
+
 		idx = serdes_get_lane_idx(lane);
 		lane_prtcl = serdes_get_prtcl(cfg, lane);
 
@@ -729,6 +733,7 @@ void fsl_serdes_init(void)
 
 #endif
 	}
+#endif
 
 #ifdef DEBUG
 	puts("\n");

arch/powerpc/cpu/mpc85xx/start.S

@@ -319,6 +319,55 @@ l2_disabled:
 #endif /* CONFIG_MPC8569 */
 
 /*
+ * Search for the TLB that covers the code we're executing, and shrink it
+ * so that it covers only this 4K page.  That will ensure that any other
+ * TLB we create won't interfere with it.  We assume that the TLB exists,
+ * which is why we don't check the Valid bit of MAS1.
+ *
+ * This is necessary, for example, when booting from the on-chip ROM,
+ * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
+ * If we don't shrink this TLB now, then we'll accidentally delete it
+ * in "purge_old_ccsr_tlb" below.
+ */
+	bl	nexti		/* Find our address */
+nexti:	mflr	r1		/* R1 = our PC */
+	li	r2, 0
+	mtspr	MAS6, r2	/* Assume the current PID and AS are 0 */
+	isync
+	msync
+	tlbsx	0, r1		/* This must succeed */
+
+	/* Set the size of the TLB to 4KB */
+	mfspr	r3, MAS1
+	li	r2, 0xF00
+	andc	r3, r3, r2	/* Clear the TSIZE bits */
+	ori	r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
+	mtspr	MAS1, r3
+
+	/*
+	 * Set the base address of the TLB to our PC.  We assume that
+	 * virtual == physical.  We also assume that MAS2_EPN == MAS3_RPN.
+	 */
+	lis	r3, MAS2_EPN@h
+	ori	r3, r3, MAS2_EPN@l	/* R3 = MAS2_EPN */
+
+	and	r1, r1, r3	/* Our PC, rounded down to the nearest page */
+
+	mfspr	r2, MAS2
+	andc	r2, r2, r3
+	or	r2, r2, r1
+	mtspr	MAS2, r2	/* Set the EPN to our PC base address */
+
+	mfspr	r2, MAS3
+	andc	r2, r2, r3
+	or	r2, r2, r1
+	mtspr	MAS3, r2	/* Set the RPN to our PC base address */
+
+	isync
+	msync
+	tlbwe
+
+/*
  * Relocate CCSR, if necessary.  We relocate CCSR if (obviously) the default
  * location is not where we want it.  This typically happens on a 36-bit
  * system, where we want to move CCSR to near the top of 36-bit address space.
@@ -352,6 +401,8 @@ purge_old_ccsr_tlb:
 
 	li	r1, 0
 	mtspr	MAS6, r1	/* Search the current address space and PID */
+	isync
+	msync
 	tlbsx	0, r8
 	mfspr	r1, MAS1
 	andis.  r2, r1, MAS1_VALID@h	/* Check for the Valid bit */
@@ -359,6 +410,8 @@ purge_old_ccsr_tlb:
 
 	rlwinm	r1, r1, 0, 1, 31	/* Clear Valid bit */
 	mtspr	MAS1, r1
+	isync
+	msync
 	tlbwe
 1:
 
@@ -387,7 +440,7 @@ create_ccsr_new_tlb:
 	tlbwe
 
 	/*
-	 * Create a TLB for the old location of CCSR.  Register R9 is reserved
+	 * Create a TLB for the current location of CCSR.  Register R9 is reserved
 	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
 	 */
 create_ccsr_old_tlb:
@@ -407,6 +460,33 @@ create_ccsr_old_tlb:
 	msync
 	tlbwe
 
+	/*
+	 * We have a TLB for what we think is the current (old) CCSR.  Let's
+	 * verify that, otherwise we won't be able to move it.
+	 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
+	 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
+	 */
+verify_old_ccsr:
+	lis     r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
+	ori     r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
+#ifdef CONFIG_FSL_CORENET
+	lwz	r1, 4(r9)		/* CCSRBARL */
+#else
+	lwz	r1, 0(r9)		/* CCSRBAR, shifted right by 12 */
+	slwi	r1, r1, 12
+#endif
+
+	cmpl	0, r0, r1
+
+	/*
+	 * If the value we read from CCSRBARL is not what we expect, then
+	 * enter an infinite loop.  This will at least allow a debugger to
+	 * halt execution and examine TLBs, etc.  There's no point in going
+	 * on.
+	 */
+infinite_debug_loop:
+	bne	infinite_debug_loop
+
 #ifdef CONFIG_FSL_CORENET
 
 #define CCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
@@ -446,7 +526,7 @@ create_temp_law:
 	 */
 read_old_ccsrbar:
 	lwz	r0, 0(r9)	/* CCSRBARH */
-	lwz	r0, 4(r9)	/* CCSRBARH */
+	lwz	r0, 4(r9)	/* CCSRBARL */
 	isync
 
 	/*

arch/powerpc/cpu/mpc85xx/tlb.c

@@ -172,7 +172,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
 
 void disable_tlb(u8 esel)
 {
-	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+	u32 _mas0, _mas1, _mas2, _mas3;
 
 	free_tlb_cam(esel);
 
@@ -180,14 +180,13 @@ void disable_tlb(u8 esel)
 	_mas1 = 0;
 	_mas2 = 0;
 	_mas3 = 0;
-	_mas7 = 0;
 
 	mtspr(MAS0, _mas0);
 	mtspr(MAS1, _mas1);
 	mtspr(MAS2, _mas2);
 	mtspr(MAS3, _mas3);
 #ifdef CONFIG_ENABLE_36BIT_PHYS
-	mtspr(MAS7, _mas7);
+	mtspr(MAS7, 0);
 #endif
 	asm volatile("isync;msync;tlbwe;isync");
 
@@ -252,16 +251,20 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 	unsigned int tlb_size;
 	unsigned int wimge = 0;
 	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
-	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+	unsigned int max_cam;
 	u64 size, memsize = (u64)memsize_in_meg << 20;
 
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
 	wimge = CONFIG_SYS_PPC_DDR_WIMGE;
 #endif
 	size = min(memsize, CONFIG_MAX_MEM_MAPPED);
-
+	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
 		/* Convert (4^max) kB to (2^max) bytes */
-	max_cam = max_cam * 2 + 10;
+		max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+	} else {
+		/* Convert (2^max) kB to (2^max) bytes */
+		max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+	}
 
 	for (i = 0; size && i < 8; i++) {
 		int ram_tlb_index = find_free_tlbcam();

arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c

@@ -672,7 +672,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		rcw_en = 1;
 		ap_en = popts->ap_en;
 	} else {
-		rcw_en = 0;
 		ap_en = 0;
 	}
 
@@ -702,9 +701,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((obc_cfg & 0x1) << 6)
 		| ((ap_en & 0x1) << 5)
 		| ((d_init & 0x1) << 4)
-#ifdef CONFIG_FSL_DDR3
 		| ((rcw_en & 0x1) << 2)
-#endif
 		| ((md_en & 0x1) << 0)
 		);
 	debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
@@ -745,7 +742,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 
 #ifdef CONFIG_FSL_DDR3
 	if (unq_mrs_en) {	/* unique mode registers are supported */
-		for (i = 1; i < 4; i++) {
+		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 			if (popts->rtt_override)
 				rtt_wr = popts->rtt_wr_override_value;
 			else
@@ -944,7 +941,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 
 	if (unq_mrs_en) {	/* unique mode registers are supported */
-		for (i = 1; i < 4; i++) {
+		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 			if (popts->rtt_override)
 				rtt = popts->rtt_override_value;
 			else

arch/powerpc/cpu/mpc8xxx/ddr/options.c

@@ -483,7 +483,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	unsigned int i;
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char *buf = NULL;
+#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 	const struct dynamic_odt *pdodt = odt_unknown;
+#endif
 	ulong ddr_freq;
 
 	/*
@@ -493,6 +495,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 		buf = buffer;
 
+#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 	/* Chip select options. */
 	if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 		switch (pdimm[0].n_ranks) {
@@ -546,6 +549,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			break;
 		}
 	}
+#endif
 
 	/* Pick chip-select local options. */
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {

arch/powerpc/cpu/mpc8xxx/fdt.c

@@ -87,13 +87,12 @@ void ft_fixup_num_cores(void *blob) {
 #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
-				const char *phy_type)
+				const char *phy_type, int start_offset)
 {
 	const char *compat = "fsl-usb2-dr";
 	const char *prop_mode = "dr_mode";
 	const char *prop_type = "phy_type";
-	static int start_offset = -1;
 	int node_offset;
 	int err;
 
@@ -102,7 +101,7 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
 	if (node_offset < 0) {
 		printf("WARNING: could not find compatible node %s: %s.\n",
 			compat, fdt_strerror(node_offset));
-		return;
+		return -1;
 	}
 
 	if (mode) {
@@ -121,16 +120,18 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
 			       prop_type, compat, fdt_strerror(err));
 	}
 
-	start_offset = node_offset;
+	return node_offset;
 }
 
 void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 {
 	const char *modes[] = { "host", "peripheral", "otg" };
-	const char *phys[] = { "ulpi", "umti" };
+	const char *phys[] = { "ulpi", "utmi" };
 	const char *mode = NULL;
 	const char *phy_type = NULL;
 	char usb1_defined = 0;
+	int usb_mode_off = -1;
+	int usb_phy_off = -1;
 	char str[5];
 	int i, j;
 
@@ -153,11 +154,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 				}
 			}
 			if (mode_idx >= 0)
-				fdt_fixup_usb_mode_phy_type(blob,
+				usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
-					modes[mode_idx], NULL);
+					modes[mode_idx], NULL, usb_mode_off);
 			if (phy_idx >= 0)
-				fdt_fixup_usb_mode_phy_type(blob,
+				usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
-					NULL, phys[phy_idx]);
+					NULL, phys[phy_idx], usb_phy_off);
 			if (!strcmp(str, "usb1"))
 				usb1_defined = 1;
 			if (mode_idx < 0 && phy_idx < 0)
@@ -165,11 +166,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 		}
 	}
 	if (!usb1_defined) {
+		int usb_off = -1;
 		mode = getenv("usb_dr_mode");
 		phy_type = getenv("usb_phy_type");
 		if (!mode && !phy_type)
 			return;
-		fdt_fixup_usb_mode_phy_type(blob, mode, phy_type);
+		fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
 	}
 }
 #endif /* CONFIG_HAS_FSL_DR_USB */

arch/powerpc/cpu/mpc8xxx/fsl_lbc.c

@@ -107,7 +107,7 @@ void init_early_memctl_regs(void)
 void upmconfig(uint upm, uint *table, uint size)
 {
 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	int i, mdr, mad, old_mad = 0;
+	int i, mad, old_mad = 0;
 	u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
 	u32 msel = BR_UPMx_TO_MSEL(upm);
 	u32 *mxmr = &lbc->mamr + upm;
@@ -138,7 +138,7 @@ void upmconfig(uint upm, uint *table, uint size)
 	for (i = 0; i < size; i++) {
 		out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
 		out_be32(&lbc->mdr, table[i]);
-		mdr = in_be32(&lbc->mdr);
+		(void)in_be32(&lbc->mdr);
 		*dummy = 0;
 		do {
 			mad = in_be32(mxmr) & MxMR_MAD_MSK;

arch/powerpc/include/asm/config_mpc85xx.h

@@ -64,6 +64,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1

arch/powerpc/include/asm/mmu.h

@@ -392,17 +392,17 @@ extern void print_bats(void);
  */
 
 #define MAS0_TLBSEL_MSK	0x30000000
-#define MAS0_TLBSEL(x)	((x << 28) & MAS0_TLBSEL_MSK)
+#define MAS0_TLBSEL(x)	(((x) << 28) & MAS0_TLBSEL_MSK)
 #define MAS0_ESEL_MSK	0x0FFF0000
-#define MAS0_ESEL(x)	((x << 16) & MAS0_ESEL_MSK)
+#define MAS0_ESEL(x)	(((x) << 16) & MAS0_ESEL_MSK)
 #define MAS0_NV(x)	((x) & 0x00000FFF)
 
 #define MAS1_VALID	0x80000000
 #define MAS1_IPROT	0x40000000
-#define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
+#define MAS1_TID(x)	(((x) << 16) & 0x3FFF0000)
 #define MAS1_TS		0x00001000
-#define MAS1_TSIZE(x)	((x << 8) & 0x00000F00)
+#define MAS1_TSIZE(x)	(((x) << 8) & 0x00000F00)
-#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10)))
+#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10))
 
 #define MAS2_EPN	0xFFFFF000
 #define MAS2_X0		0x00000040

arch/powerpc/include/asm/processor.h

@@ -513,7 +513,13 @@
 
 #define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
 #define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
+#define SPRN_TLB0PS	0x158	/* TLB 0 Page Size Register */
+#define SPRN_TLB1PS	0x159	/* TLB 1 Page Size Register */
 #define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
+#define SPRN_MMUCFG	0x3F7	/* MMU Configuration Register */
+#define MMUCFG_MAVN	0x00000003	/* MMU Architecture Version Number */
+#define MMUCFG_MAVN_V1	0x00000000	/* v1.0 */
+#define MMUCFG_MAVN_V2	0x00000001	/* v2.0 */
 #define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
 #define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
 #define SPRN_MAS2	0x272	/* MMU Assist Register 2 */

board/freescale/common/cds_pci_ft.c

@@ -28,13 +28,12 @@
 #if defined(CONFIG_OF_BOARD_SETUP)
 static void cds_pci_fixup(void *blob)
 {
-	int node, tmp[2];
+	int node;
 	const char *path;
 	int len, slot, i;
 	u32 *map = NULL;
 
 	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
 	if (node >= 0) {
 		path = fdt_getprop(blob, node, "pci0", NULL);
 		if (path) {

board/freescale/common/ics307_clk.c

@@ -31,12 +31,81 @@
 #include "pixis.h"
 #endif
 
+/* define for SYS CLK or CLK1Frequency */
+#define TTL		1
+#define CLK2		0
+#define CRYSTAL		0
+#define MAX_VDW		(511 + 8)
+#define MAX_RDW		(127 + 2)
+#define MIN_VDW		(4 + 8)
+#define MIN_RDW		(1 + 2)
+#define NUM_OD_SETTING	8
+/*
+ * These defines cover the industrial temperature range part,
+ * for commercial, change below to 400000 and 55000, respectively
+ */
+#define MAX_VCO		360000
+#define MIN_VCO		60000
+
 /* decode S[0-2] to Output Divider (OD) */
 static u8 ics307_s_to_od[] = {
 	10, 2, 8, 4, 5, 7, 3, 6
 };
 
 /*
+ * Find one solution to generate required frequency for SYSCLK
+ * out_freq: KHz, required frequency to the SYSCLK
+ * the result will be retuned with component RDW, VDW, OD, TTL,
+ * CLK2 and crystal
+ */
+unsigned long ics307_sysclk_calculator(unsigned long out_freq)
+{
+	const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+	unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
+	unsigned long tmp_out, diff, result = 0;
+	int found = 0;
+
+	for (odp = 0; odp < NUM_OD_SETTING; odp++) {
+		od = ics307_s_to_od[odp];
+		if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
+			continue;
+		for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
+			/* Calculate the VDW */
+			vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
+			if (vdw > MAX_VDW)
+				vdw = MAX_VDW;
+			if (vdw < MIN_VDW)
+				continue;
+			/* Calculate the temp out frequency */
+			tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
+			diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out);
+			/*
+			 * calculate the percent, the precision is 1/1000
+			 * If greater than 1/1000, continue
+			 * otherwise, we think the solution is we required
+			 */
+			if (diff * 1000 / out_freq > 1)
+				continue;
+			else {
+				s_vdw = vdw;
+				s_rdw = rdw;
+				s_odp = odp;
+				found = 1;
+				break;
+			}
+		}
+	}
+
+	if (found)
+		result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
+			CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
+
+	debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
+			ics307_s_to_od[s_odp]);
+	return result;
+}
+
+/*
  * Calculate frequency being generated by ICS307-02 clock chip based upon
  * the control bytes being programmed into it.
  */

board/freescale/common/ics307_clk.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,8 +23,10 @@
 #define __ICS_CLK_H_	1
 
 #ifndef __ASSEMBLY__
+
 extern unsigned long get_board_sys_clk(void);
 extern unsigned long get_board_ddr_clk(void);
+extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
 #endif
 
 #endif	/* __ICS_CLK_H_ */

board/freescale/common/ngpixis.c

@@ -156,9 +156,29 @@ static void pixis_dump_regs(void)
 }
 #endif
 
+void pixis_sysclk_set(unsigned long sysclk)
+{
+	unsigned long freq_word;
+	u8 sclk0, sclk1, sclk2;
+
+	freq_word = ics307_sysclk_calculator(sysclk);
+	sclk2 = freq_word & 0xff;
+	sclk1 = (freq_word >> 8) & 0xff;
+	sclk0 = (freq_word >> 16) & 0xff;
+
+	/* set SYSCLK enable bit */
+	PIXIS_WRITE(vcfgen0, 0x01);
+
+	/* SYSCLK to required frequency */
+	PIXIS_WRITE(sclk[0], sclk0);
+	PIXIS_WRITE(sclk[1], sclk1);
+	PIXIS_WRITE(sclk[2], sclk2);
+}
+
 int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	unsigned int i;
+	unsigned long sysclk;
 	char *p_altbank = NULL;
 #ifdef DEBUG
 	char *p_dump = NULL;
@@ -182,6 +202,12 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			continue;
 		}
 #endif
+		if (strcmp(argv[i], "sysclk") == 0) {
+			sysclk = simple_strtoul(argv[i + 1], NULL, 0);
+			i += 1;
+			pixis_sysclk_set(sysclk);
+			continue;
+		}
 
 		unknown_param = argv[i];
 	}
@@ -219,4 +245,5 @@ U_BOOT_CMD(
 #ifdef DEBUG
 	"pixis_reset dump - display the PIXIS registers\n"
 #endif
+	"pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n"
 	);

board/freescale/common/pixis.c

@@ -380,7 +380,7 @@ static unsigned long strfractoint(char *strptr)
 {
 	int i, j;
 	int mulconst;
-	int intarr_len, no_dec = 0;
+	int no_dec = 0;
 	unsigned long intval = 0, decval = 0;
 	char intarr[3], decarr[3];
 
@@ -399,8 +399,6 @@ static unsigned long strfractoint(char *strptr)
 		i++;
 	}
 
-	/* Assign length of integer part to intarr_len. */
-	intarr_len = i;
 	intarr[i] = '\0';
 
 	if (no_dec) {

board/freescale/corenet_ds/eth_hydra.c

@@ -377,7 +377,6 @@ void fdt_fixup_board_enet(void *fdt)
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
-	struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
 	struct fsl_pq_mdio_info dtsec_mdio_info;
 	struct tgec_mdio_info tgec_mdio_info;
 	unsigned int i, slot;
@@ -387,13 +386,6 @@ int board_eth_init(bd_t *bis)
 
 	initialize_lane_to_slot();
 
-	/*
-	 * Set TBIPA on FM1@DTSEC1.  This is needed for configurations
-	 * where FM1@DTSEC1 isn't used directly, since it provides
-	 * MDIO for other ports.
-	 */
-	out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
 	/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
 	setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
 

board/freescale/corenet_ds/eth_p4080.c

@@ -301,7 +301,6 @@ int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
 	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-	struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
 	int i;
 	struct fsl_pq_mdio_info dtsec_mdio_info;
 	struct tgec_mdio_info tgec_mdio_info;
@@ -327,13 +326,6 @@ int board_eth_init(bd_t *bis)
 		SLOT5, /* 17 - Bank 3:D */
 	};
 
-	/*
-	 * Set TBIPA on FM1@DTSEC1.  This is needed for configurations
-	 * where FM1@DTSEC1 isn't used directly, since it provides
-	 * MDIO for other ports.
-	 */
-	out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
 	/* Initialize the mdio_mux array so we can recognize empty elements */
 	for (i = 0; i < NUM_FM_PORTS; i++)
 		mdio_mux[i] = EMI_NONE;

board/freescale/mpc8548cds/mpc8548cds.c

@@ -33,6 +33,9 @@
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <tsec.h>
+#include <fsl_mdio.h>
+#include <netdev.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
@@ -81,12 +84,10 @@ local_bus_init(void)
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
-	uint lbc_hz;
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	gur->lbiuiplldcr1 = 0x00078080;
 	if (clkdiv == 16) {
@@ -115,7 +116,6 @@ void lbc_sdram_init(void)
 	uint idx;
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-	uint cpu_board_rev;
 	uint lsdmr_common;
 
 	puts("LBC SDRAM: ");
@@ -137,7 +137,6 @@ void lbc_sdram_init(void)
 	/*
 	 * MPC8548 uses "new" 15-16 style addressing.
 	 */
-	cpu_board_rev = get_cpu_board_revision();
 	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 	lsdmr_common |= LSDMR_BSMA1516;
 
@@ -287,7 +286,7 @@ void pci_init_board(void)
 	fsl_pcie_init_board(first_free_busno);
 }
 
-int last_stage_init(void)
+void configure_rgmii(void)
 {
 	unsigned short temp;
 
@@ -295,29 +294,77 @@ int last_stage_init(void)
 	/* This is needed to get the RGMII working for the 1.3+
 	 * CDS cards */
 	if (get_board_version() ==  0x13) {
-		miiphy_write(CONFIG_TSEC1_NAME,
+		miiphy_write(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 29, 18);
 
-		miiphy_read(CONFIG_TSEC1_NAME,
+		miiphy_read(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 30, &temp);
 
 		temp = (temp & 0xf03f);
 		temp |= 2 << 9;		/* 36 ohm */
 		temp |= 2 << 6;		/* 39 ohm */
 
-		miiphy_write(CONFIG_TSEC1_NAME,
+		miiphy_write(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 30, temp);
 
-		miiphy_write(CONFIG_TSEC1_NAME,
+		miiphy_write(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 29, 3);
 
-		miiphy_write(CONFIG_TSEC1_NAME,
+		miiphy_write(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 30, 0x8000);
 	}
 
+	return;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	/* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
+	if (get_board_version() >= 0x13) {
+		SET_STD_TSEC_INFO(tsec_info[num], 3);
+		tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+		num++;
+	}
+#endif
+#ifdef CONFIG_TSEC4
+	/* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
+	if (get_board_version() >= 0x13) {
+		SET_STD_TSEC_INFO(tsec_info[num], 4);
+		tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+		num++;
+	}
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+
 		return 0;
 	}
 
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+	configure_rgmii();
+
+	return pci_eth_init(bis);
+}
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_pci_setup(void *blob, bd_t *bd)

board/freescale/mpc8568mds/mpc8568mds.c

@@ -147,12 +147,10 @@ local_bus_init(void)
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
-	uint lbc_hz;
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	gur->lbiuiplldcr1 = 0x00078080;
 	if (clkdiv == 16) {
@@ -302,6 +300,7 @@ pib_init(void)
 	i2c_write(0x27, 0x3, 1, &val8, 1);
 
 	asm("eieio");
+	i2c_set_bus_num(orig_i2c_bus);
 }
 
 #ifdef CONFIG_PCI

board/freescale/mpc8569mds/mpc8569mds.c

@@ -303,12 +303,10 @@ local_bus_init(void)
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
-	uint lbc_hz;
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
 	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	out_be32(&gur->lbiuiplldcr1, 0x00078080);
 	if (clkdiv == 16)

board/freescale/mpc8572ds/tlb.c

@@ -58,6 +58,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
+#ifndef CONFIG_NAND_SPL
 	/* *I*G* - PCI */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -76,6 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
 
 	/* *I*G - NAND */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,

board/freescale/p1010rdb/p1010rdb.c

@@ -275,7 +275,9 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
+#if defined(CONFIG_HAS_FSL_DR_USB)
 	fdt_fixup_dr_usb(blob, bd);
+#endif
 
        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
 	if (cpu->soc_ver == SVR_P1014 || cpu->soc_ver == SVR_P1014_E) {

board/freescale/p1_p2_rdb/p1_p2_rdb.c

@@ -264,7 +264,9 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
+#if defined(CONFIG_HAS_FSL_DR_USB)
 	fdt_fixup_dr_usb(blob, bd);
+#endif
 
 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 	/* Delete eLBC node as it is muxed with USB2 controller */

board/freescale/p1_p2_rdb_pc/law.c

@@ -25,15 +25,17 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifndef CONFIG_NAND_SPL
 	SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_NAND_BASE_PHYS
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
-#endif
 #ifdef CONFIG_VSC7385_ENET
 	SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
+#endif
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+#endif
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c

@@ -444,6 +444,9 @@ void ft_board_setup(void *blob, bd_t *bd)
 	fdt_board_fixup_qe_pins(blob);
 #endif
 #endif
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
 	fdt_fixup_dr_usb(blob, bd);
+#endif
 }
 #endif

board/freescale/p2041rdb/eth.c

@@ -139,7 +139,6 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_FMAN_ENET
-	struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
 	struct fsl_pq_mdio_info dtsec_mdio_info;
 	struct tgec_mdio_info tgec_mdio_info;
 	unsigned int i, slot;
@@ -149,13 +148,6 @@ int board_eth_init(bd_t *bis)
 
 	initialize_lane_to_slot();
 
-	/*
-	 * Set TBIPA on FM1@DTSEC1.  This is needed for configurations
-	 * where FM1@DTSEC1 isn't used directly, since it provides
-	 * MDIO for other ports.
-	 */
-	out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
-
 	dtsec_mdio_info.regs =
 		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;

board/sbc8548/sbc8548.c

@@ -77,12 +77,10 @@ local_bus_init(void)
 	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
 	uint clkdiv;
-	uint lbc_hz;
 	sys_info_t sysinfo;
 
 	get_sys_info(&sysinfo);
 	clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
-	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	out_be32(&gur->lbiuiplldcr1, 0x00078080);
 	if (clkdiv == 16) {

board/sbc8560/sbc8560.c

@@ -348,7 +348,7 @@ phys_size_t fixed_sdram(void)
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	int node, tmp[2];
+	int node;
 #ifdef CONFIG_PCI
 	const char *path;
 #endif
@@ -356,7 +356,6 @@ ft_board_setup(void *blob, bd_t *bd)
 	ft_cpu_setup(blob, bd);
 
 	node = fdt_path_offset(blob, "/aliases");
-	tmp[0] = 0;
 	if (node >= 0) {
 #ifdef CONFIG_PCI
 		path = fdt_getprop(blob, node, "pci0", NULL);

drivers/net/fm/fm.c

@@ -395,7 +395,6 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 	int dev = CONFIG_SYS_MMC_ENV_DEV;
 	void *addr = malloc(CONFIG_SYS_FMAN_FW_LENGTH);
 	u32 cnt = CONFIG_SYS_FMAN_FW_LENGTH / 512;
-	u32 n;
 	u32 blk = CONFIG_SYS_QE_FW_IN_MMC / 512;
 	struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
 
@@ -405,7 +404,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 		printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
 				dev, blk, cnt);
 		mmc_init(mmc);
-		n = mmc->block_dev.block_read(dev, blk, cnt, addr);
+		(void)mmc->block_dev.block_read(dev, blk, cnt, addr);
 		/* flush cache after read */
 		flush_cache((ulong)addr, cnt * 512);
 	}

drivers/net/tsec.c

@@ -19,6 +19,7 @@
 #include <tsec.h>
 #include <fsl_mdio.h>
 #include <asm/errno.h>
+#include <asm/processor.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -43,6 +44,9 @@ static RTXBD rtx __attribute__ ((aligned(8)));
 #error "rtx must be 64-bit aligned"
 #endif
 
+static int tsec_send(struct eth_device *dev,
+	volatile void *packet, int length);
+
 /* Default initializations for TSEC controllers. */
 
 static struct tsec_info_struct tsec_info[] = {
@@ -236,6 +240,87 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
 			(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
 }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+/*
+ * When MACCFG1[Rx_EN] is enabled during system boot as part
+ * of the eTSEC port initialization sequence,
+ * the eTSEC Rx logic may not be properly initialized.
+ */
+void redundant_init(struct eth_device *dev)
+{
+	struct tsec_private *priv = dev->priv;
+	tsec_t *regs = priv->regs;
+	uint t, count = 0;
+	int fail = 1;
+	static const u8 pkt[] = {
+		0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
+		0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
+		0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
+		0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
+		0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
+		0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
+		0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
+		0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
+		0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
+		0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+		0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
+		0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+		0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
+		0x71, 0x72};
+
+	/* Enable promiscuous mode */
+	setbits_be32(&regs->rctrl, 0x8);
+	/* Enable loopback mode */
+	setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
+	/* Enable transmit and receive */
+	setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
+
+	/* Tell the DMA it is clear to go */
+	setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
+	out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
+	out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
+	clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+
+	do {
+		tsec_send(dev, (void *)pkt, sizeof(pkt));
+
+		/* Wait for buffer to be received */
+		for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) {
+			if (t >= 10 * TOUT_LOOP) {
+				printf("%s: tsec: rx error\n", dev->name);
+				break;
+			}
+		}
+
+		if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt)))
+			fail = 0;
+
+		rtx.rxbd[rxIdx].length = 0;
+		rtx.rxbd[rxIdx].status =
+		    RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+		rxIdx = (rxIdx + 1) % PKTBUFSRX;
+
+		if (in_be32(&regs->ievent) & IEVENT_BSY) {
+			out_be32(&regs->ievent, IEVENT_BSY);
+			out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
+		}
+		if (fail) {
+			printf("loopback recv packet error!\n");
+			clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
+			udelay(1000);
+			setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
+		}
+	} while ((count++ < 4) && (fail == 1));
+
+	if (fail)
+		panic("eTSEC init fail!\n");
+	/* Disable promiscuous mode */
+	clrbits_be32(&regs->rctrl, 0x8);
+	/* Disable loopback mode */
+	clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
+}
+#endif
+
 /* Set up the buffers and their descriptors, and bring up the
  * interface
  */
@@ -248,6 +333,9 @@ static void startup_tsec(struct eth_device *dev)
 	/* reset the indices to zero */
 	rxIdx = 0;
 	txIdx = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+	uint svr;
+#endif
 
 	/* Point to the buffer descriptors */
 	out_be32(&regs->tbase, (unsigned int)(&rtx.txbd[txIdx]));
@@ -269,6 +357,11 @@ static void startup_tsec(struct eth_device *dev)
 	}
 	rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+	svr = get_svr();
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+		redundant_init(dev);
+#endif
 	/* Enable Transmit and Receive */
 	setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
 

drivers/qe/uec.c

@@ -264,13 +264,10 @@ static int uec_open(uec_private_t *uec, comm_dir_e mode)
 
 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
 {
-	ucc_fast_private_t	*uccf;
-
 	if (!uec || !uec->uccf) {
 		printf("%s: No handle passed.\n", __FUNCTION__);
 		return -EINVAL;
 	}
-	uccf = uec->uccf;
 
 	/* check if the UCC number is in range. */
 	if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
@@ -325,7 +322,6 @@ static int uec_set_mac_if_mode(uec_private_t *uec,
 		phy_interface_t if_mode, int speed)
 {
 	phy_interface_t		enet_if_mode;
-	uec_info_t		*uec_info;
 	uec_t			*uec_regs;
 	u32			upsmr;
 	u32			maccfg2;
@@ -335,7 +331,6 @@ static int uec_set_mac_if_mode(uec_private_t *uec,
 		return -EINVAL;
 	}
 
-	uec_info = uec->uec_info;
 	uec_regs = uec->uec_regs;
 	enet_if_mode = if_mode;
 
@@ -516,12 +511,10 @@ bus_fail:
 static void adjust_link(struct eth_device *dev)
 {
 	uec_private_t		*uec = (uec_private_t *)dev->priv;
-	uec_t			*uec_regs;
 	struct uec_mii_info	*mii_info = uec->mii_info;
 
 	extern void change_phy_interface_mode(struct eth_device *dev,
 				 phy_interface_t mode, int speed);
-	uec_regs = uec->uec_regs;
 
 	if (mii_info->link) {
 		/* Now we make sure that we can be in full duplex mode.

drivers/usb/host/ehci-fsl.c

@@ -40,11 +40,13 @@
 int ehci_hcd_init(void)
 {
 	struct usb_ehci *ehci;
-	char usb_phy[5];
 	const char *phy_type = NULL;
 	size_t len;
+#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+	char usb_phy[5];
 
 	usb_phy[0] = '\0';
+#endif
 
 	ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
 	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);

include/config_phylib_all_drivers.h

@@ -22,6 +22,7 @@
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_NATSEMI
 #define CONFIG_PHY_LXT
+#define CONFIG_PHY_ATHEROS
 
 #ifdef CONFIG_PHYLIB_10G
 #define CONFIG_PHY_TERANETICS

include/configs/MPC8536DS.h

@@ -131,7 +131,7 @@
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 

include/configs/MPC8548CDS.h

@@ -464,6 +464,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
+#define CONFIG_PHY_MARVELL
+
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC3_PHY_ADDR		2

include/configs/MPC8569MDS.h

@@ -108,7 +108,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR		0xe0000000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 

include/configs/MPC8572DS.h

@@ -115,7 +115,7 @@
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 

include/configs/P1022DS.h

@@ -173,7 +173,7 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
 /*
  * Serial Port

include/configs/P1_P2_RDB.h

@@ -151,7 +151,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR		0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
 
-#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
 

include/configs/p1_p2_rdb_pc.h

@@ -221,7 +221,7 @@
 
 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
        SPL code*/
-#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif