Tom Rini
10 years ago
commit
1131d4e22c
@ -1,9 +0,0 @@ |
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#
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# Copyright (C) 2014 Stefan Roese <sr@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = cpu.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
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@ -0,0 +1,24 @@ |
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#
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# Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_KIRKWOOD |
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obj-y = dram.o
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obj-y += gpio.o
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obj-y += timer.o
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else |
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obj-y = cpu.o
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obj-y += dram.o
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obj-y += gpio.o
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obj-y += mbus.o
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obj-y += timer.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
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obj-y += serdes/
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endif |
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@ -0,0 +1,15 @@ |
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if TARGET_DB_88F6820_GP |
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config SYS_BOARD |
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default "db-88f6820-gp" |
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config SYS_VENDOR |
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default "Marvell" |
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config SYS_SOC |
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default "mvebu" |
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config SYS_CONFIG_NAME |
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default "db-88f6820-gp" |
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endif |
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@ -0,0 +1,7 @@ |
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#
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# Copyright (C) 2015 Stefan Roese <sr@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := db-88f6820-gp.o
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@ -0,0 +1,16 @@ |
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-------- |
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WARNING: |
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-------- |
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This file should contain the bin_hdr generated by the original Marvell |
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U-Boot implementation. As this is currently not included in this |
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U-Boot version, we have added this placeholder, so that the U-Boot |
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image can be generated without errors. |
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If you have a known to be working bin_hdr for your board, then you |
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just need to replace this text file here with the binary header |
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and recompile U-Boot. |
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In a few weeks, mainline U-Boot will get support to generate the |
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bin_hdr with the DDR training code itself. By implementing this code |
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as SPL U-Boot. Then this file will not be needed any more and will |
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get removed. |
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@ -0,0 +1,103 @@ |
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/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <miiphy.h> |
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#include <asm/io.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define BIT(nr) (1UL << (nr)) |
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#define ETH_PHY_CTRL_REG 0 |
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#define ETH_PHY_CTRL_POWER_DOWN_BIT 11 |
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#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) |
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/*
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* Those values and defines are taken from the Marvell U-Boot version |
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* "u-boot-2013.01-2014_T3.0" |
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*/ |
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#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \ |
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(~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
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BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
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BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) |
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#define DB_GP_88F68XX_GPP_OUT_ENA_MID \ |
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(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
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BIT(16) | BIT(17) | BIT(18))) |
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#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0 |
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#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0 |
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#define DB_GP_88F68XX_GPP_POL_LOW 0x0 |
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#define DB_GP_88F68XX_GPP_POL_MID 0x0 |
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/* IO expander on Marvell GP board includes e.g. fan enabling */ |
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struct marvell_io_exp { |
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u8 chip; |
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u8 addr; |
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u8 val; |
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}; |
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static struct marvell_io_exp io_exp[] = { |
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{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */ |
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{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */ |
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{ 0x20, 2, 0x1D }, /* Output Data, register#0 */ |
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{ 0x20, 3, 0x18 }, /* Output Data, register#1 */ |
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{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */ |
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{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */ |
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{ 0x21, 2, 0x08 }, /* Output Data, register#0 */ |
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{ 0x21, 3, 0xC0 } /* Output Data, register#1 */ |
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}; |
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int board_early_init_f(void) |
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{ |
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/* Configure MPP */ |
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writel(0x11111111, MVEBU_MPP_BASE + 0x00); |
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writel(0x11111111, MVEBU_MPP_BASE + 0x04); |
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writel(0x11244011, MVEBU_MPP_BASE + 0x08); |
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writel(0x22222111, MVEBU_MPP_BASE + 0x0c); |
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writel(0x22200002, MVEBU_MPP_BASE + 0x10); |
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writel(0x30042022, MVEBU_MPP_BASE + 0x14); |
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writel(0x55550555, MVEBU_MPP_BASE + 0x18); |
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writel(0x00005550, MVEBU_MPP_BASE + 0x1c); |
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/* Set GPP Out value */ |
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writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); |
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writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); |
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/* Set GPP Polarity */ |
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writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); |
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writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); |
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/* Set GPP Out Enable */ |
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writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); |
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writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); |
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return 0; |
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} |
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int board_init(void) |
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{ |
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int i; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
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/* Init I2C IO expanders */ |
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for (i = 0; i < ARRAY_SIZE(io_exp); i++) |
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i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); |
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return 0; |
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} |
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int checkboard(void) |
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{ |
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puts("Board: Marvell DB-88F6820-GP\n"); |
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return 0; |
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} |
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@ -0,0 +1,12 @@ |
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# |
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# Copyright (C) 2014 Stefan Roese <sr@denx.de> |
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# |
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# Armada XP uses version 1 image format |
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VERSION 1 |
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# Boot Media configurations |
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BOOT_FROM spi |
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# Binary Header (bin_hdr) with DDR3 training code |
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BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068 |
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@ -0,0 +1,2 @@ |
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CONFIG_ARM=y |
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CONFIG_TARGET_DB_88F6820_GP=y |
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@ -0,0 +1,72 @@ |
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/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _CONFIG_DB_88F6820_GP_H |
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#define _CONFIG_DB_88F6820_GP_H |
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/*
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* High Level Configuration Options (easy to change) |
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*/ |
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#define CONFIG_ARMADA_XP /* SOC Family Name */ |
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#define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ |
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#define CONFIG_SYS_L2_PL310 |
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
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#define CONFIG_SYS_GENERIC_BOARD |
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#define CONFIG_DISPLAY_BOARDINFO_LATE |
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#define CONFIG_SYS_TEXT_BASE 0x04000000 |
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#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
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/*
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* Commands configuration |
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*/ |
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#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ |
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#include <config_cmd_default.h> |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_I2C |
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#define CONFIG_CMD_PING |
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#define CONFIG_CMD_SF |
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#define CONFIG_CMD_SPI |
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#define CONFIG_CMD_TFTPPUT |
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#define CONFIG_CMD_TIME |
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/* I2C */ |
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#define CONFIG_SYS_I2C |
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#define CONFIG_SYS_I2C_MVTWSI |
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
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#define CONFIG_SYS_I2C_SLAVE 0x0 |
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#define CONFIG_SYS_I2C_SPEED 100000 |
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/* SPI NOR flash default params, used by sf commands */ |
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#define CONFIG_SF_DEFAULT_SPEED 1000000 |
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 |
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#define CONFIG_SPI_FLASH_STMICRO |
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/* Environment in SPI NOR flash */ |
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#define CONFIG_ENV_IS_IN_SPI_FLASH |
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#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ |
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#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ |
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#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ |
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#define CONFIG_PHY_MARVELL /* there is a marvell phy */ |
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#define CONFIG_PHY_ADDR { 1, 0 } |
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#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII |
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ |
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#define CONFIG_SYS_ALT_MEMTEST |
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/*
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* mv-common.h should be defined after CMD configs since it used them |
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* to enable certain macros |
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*/ |
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#include "mv-common.h" |
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#endif /* _CONFIG_DB_88F6820_GP_H */ |
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