Merge git://git.denx.de/u-boot-marvell

arch/arm/Kconfig

@@ -102,6 +102,11 @@ config KIRKWOOD
 	bool "Marvell Kirkwood"
 	select CPU_ARM926EJS
 
+config TARGET_DB_88F6820_GP
+	bool "Support DB-88F6820-GP"
+	select CPU_V7
+	select SUPPORT_SPL
+
 config TARGET_DB_MV784MP_GP
 	bool "Support db-mv784mp-gp"
 	select CPU_V7
@@ -855,6 +860,7 @@ source "board/BuR/kwb/Kconfig"
 source "board/BuR/tseries/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
 source "board/Marvell/aspenite/Kconfig"
+source "board/Marvell/db-88f6820-gp/Kconfig"
 source "board/Marvell/db-mv784mp-gp/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/altera/socfpga/Kconfig"

arch/arm/Makefile

@@ -48,6 +48,7 @@ machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
 machine-$(CONFIG_KIRKWOOD)		+= kirkwood
+machine-$(CONFIG_ARMADA_XP)		+= mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
 machine-$(CONFIG_ARCH_NOMADIK)		+= nomadik
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
@@ -85,8 +86,8 @@ libs-y += arch/arm/imx-common/
 endif
 endif
 
-ifneq (,$(filter $(SOC), armada-xp kirkwood))
+ifneq (,$(filter $(SOC), kirkwood))
-libs-y += arch/arm/mvebu-common/
+libs-y += arch/arm/mach-mvebu/
 endif
 
 # deprecated

arch/arm/cpu/armv7/Makefile

@@ -38,7 +38,6 @@ obj-y += s5p-common/
 endif
 
 obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
-obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/

arch/arm/cpu/armv7/armada-xp/Makefile

@@ -1,9 +0,0 @@
-#
-# Copyright (C) 2014 Stefan Roese <sr@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= cpu.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o

arch/arm/mach-mvebu/Makefile

@@ -0,0 +1,24 @@
+#
+# Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_KIRKWOOD
+
+obj-y	= dram.o
+obj-y	+= gpio.o
+obj-y	+= timer.o
+
+else
+
+obj-y	= cpu.o
+obj-y	+= dram.o
+obj-y	+= gpio.o
+obj-y	+= mbus.o
+obj-y	+= timer.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
+
+obj-y	+= serdes/
+endif

arch/arm/mach-mvebu/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -40,6 +40,20 @@ void reset_cpu(unsigned long ignored)
 		;
 }
 
+int mvebu_soc_family(void)
+{
+	u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
+
+	if (devid == SOC_MV78460_ID)
+		return MVEBU_SOC_AXP;
+
+	if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
+	    devid == SOC_88F6828_ID)
+		return MVEBU_SOC_A38X;
+
+	return MVEBU_SOC_UNKNOWN;
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
@@ -52,23 +66,48 @@ int print_cpuinfo(void)
 	case SOC_MV78460_ID:
 		puts("MV78460-");
 		break;
-	default:
+	case SOC_88F6810_ID:
-		puts("Unknown-");
+		puts("MV88F6810-");
 		break;
-	}
+	case SOC_88F6820_ID:
-
+		puts("MV88F6820-");
-	switch (revid) {
-	case 1:
-		puts("A0\n");
 		break;
-	case 2:
+	case SOC_88F6828_ID:
-		puts("B0\n");
+		puts("MV88F6828-");
 		break;
 	default:
-		puts("??\n");
+		puts("Unknown-");
 		break;
 	}
 
+	if (mvebu_soc_family() == MVEBU_SOC_AXP) {
+		switch (revid) {
+		case 1:
+			puts("A0\n");
+			break;
+		case 2:
+			puts("B0\n");
+			break;
+		default:
+			printf("?? (%x)\n", revid);
+			break;
+		}
+	}
+
+	if (mvebu_soc_family() == MVEBU_SOC_A38X) {
+		switch (revid) {
+		case MV_88F68XX_Z1_ID:
+			puts("Z1\n");
+			break;
+		case MV_88F68XX_A0_ID:
+			puts("A0\n");
+			break;
+		default:
+			printf("?? (%x)\n", revid);
+			break;
+		}
+	}
+
 	return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
@@ -145,11 +184,13 @@ int arch_cpu_init(void)
 	 */
 	mvebu_mbus_probe(NULL, 0);
 
-	/*
+	if (mvebu_soc_family() == MVEBU_SOC_AXP) {
-	 * Now the SDRAM access windows can be reconfigured using
+		/*
-	 * the information in the SDRAM scratch pad registers
+		 * Now the SDRAM access windows can be reconfigured using
-	 */
+		 * the information in the SDRAM scratch pad registers
-	update_sdram_window_sizes();
+		 */
+		update_sdram_window_sizes();
+	}
 
 	/*
 	 * Finally the mbus windows can be configured with the
@@ -175,10 +216,22 @@ int arch_misc_init(void)
 #ifdef CONFIG_MVNETA
 int cpu_eth_init(bd_t *bis)
 {
-	mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
+	u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
-	mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
+			    MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
-	mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
+	u8 phy_addr[] = CONFIG_PHY_ADDR;
-	mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
+	int i;
+
+	/*
+	 * Only Armada XP supports all 4 ethernet interfaces. A38x has
+	 * slightly different base addresses for its 2-3 interfaces.
+	 */
+	if (mvebu_soc_family() != MVEBU_SOC_AXP) {
+		enet_base[1] = MVEBU_EGIGA2_BASE;
+		enet_base[2] = MVEBU_EGIGA3_BASE;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
+		mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
 
 	return 0;
 }
@@ -187,6 +240,9 @@ int cpu_eth_init(bd_t *bis)
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
+	/* Avoid problem with e.g. neta ethernet driver */
+	invalidate_dcache_all();
+
 	/* Enable D-cache. I-cache is already enabled in start.S */
 	dcache_enable();
 }

arch/arm/mach-mvebu/include/mach/config.h

@@ -9,15 +9,17 @@
 /*
  * This file should be included in board config header file.
  *
- * It supports common definitions for Armada XP platforms
+ * It supports common definitions for MVEBU platforms
  */
 
-#ifndef _ARMADA_XP_CONFIG_H
+#ifndef _MVEBU_CONFIG_H
-#define _ARMADA_XP_CONFIG_H
+#define _MVEBU_CONFIG_H
 
 #include <asm/arch/soc.h>
 
+#if defined(CONFIG_ARMADA_XP)
 #define MV88F78X60 /* for the DDR training bin_hdr code */
+#endif
 
 #define CONFIG_SYS_CACHELINE_SIZE	32
 
@@ -33,8 +35,6 @@
 /* Add target to build it automatically upon "make" */
 #ifdef CONFIG_SPL
 #define CONFIG_BUILD_TARGET	"u-boot-spl.kwb"
-#else
-#define CONFIG_BUILD_TARGET	"u-boot.kwb"
 #endif
 
 /* end of 16M scrubbed by training in bootrom */
@@ -83,4 +83,9 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 #endif
 
-#endif /* _ARMADA_XP_CONFIG_H */
+/* Common SPL configuration */
+#ifndef CONFIG_SPL_LDSCRIPT
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/mach-mvebu/u-boot-spl.lds"
+#endif
+
+#endif /* __MVEBU_CONFIG_H */

arch/arm/mach-mvebu/include/mach/cpu.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _ARMADA_XP_CPU_H
+#ifndef _MVEBU_CPU_H
-#define _ARMADA_XP_CPU_H
+#define _MVEBU_CPU_H
 
 #include <asm/system.h>
 
@@ -56,6 +56,12 @@ enum cpu_attrib {
 	CPU_ATTR_DEV_CS3 = 0x37,
 };
 
+enum {
+	MVEBU_SOC_AXP,
+	MVEBU_SOC_A38X,
+	MVEBU_SOC_UNKNOWN,
+};
+
 /*
  * Default Device Address MAP BAR values
  */
@@ -106,6 +112,7 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
 unsigned int mvebu_sdram_bs(enum memory_bank bank);
 void mvebu_sdram_size_adjust(enum memory_bank bank);
 int mvebu_mbus_probe(struct mbus_win windows[], int count);
+int mvebu_soc_family(void);
 
 /*
  * Highspeed SERDES PHY config init, ported from bin_hdr
@@ -120,4 +127,4 @@ int serdes_phy_config(void);
  */
 int ddr3_init(void);
 #endif /* __ASSEMBLY__ */
-#endif /* _ARMADA_XP_CPU_H */
+#endif /* _MVEBU_CPU_H */

arch/arm/mach-mvebu/include/mach/soc.h

@@ -8,10 +8,17 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef _ASM_ARCH_ARMADA_XP_H
+#ifndef _MVEBU_SOC_H
-#define _ASM_ARCH_ARMADA_XP_H
+#define _MVEBU_SOC_H
 
 #define SOC_MV78460_ID		0x7846
+#define SOC_88F6810_ID		0x6810
+#define SOC_88F6820_ID		0x6820
+#define SOC_88F6828_ID		0x6828
+
+/* A38x revisions */
+#define MV_88F68XX_Z1_ID	0x0
+#define MV_88F68XX_A0_ID	0x4
 
 /* TCLK Core Clock definition */
 #ifndef CONFIG_SYS_TCLK
@@ -25,6 +32,8 @@
 #define MVEBU_REGISTER(x)	(SOC_REGS_PHY_BASE + x)
 
 #define MVEBU_SDRAM_SCRATCH	(MVEBU_REGISTER(0x01504))
+#define MVEBU_L2_CACHE_BASE	(MVEBU_REGISTER(0x08000))
+#define CONFIG_SYS_PL310_BASE	MVEBU_L2_CACHE_BASE
 #define MVEBU_SPI_BASE		(MVEBU_REGISTER(0x10600))
 #define MVEBU_TWSI_BASE		(MVEBU_REGISTER(0x11000))
 #define MVEBU_UART0_BASE	(MVEBU_REGISTER(0x12000))
@@ -46,12 +55,9 @@
 #define SDRAM_MAX_CS		4
 #define SDRAM_ADDR_MASK		0xFF000000
 
-/* Armada XP GbE controller has 4 ports */
+/* MVEBU CPU memory windows */
-#define MAX_MVNETA_DEVS		4
-
-/* Kirkwood CPU memory windows */
 #define MVCPU_WIN_CTRL_DATA	CPU_WIN_CTRL_DATA
 #define MVCPU_WIN_ENABLE	CPU_WIN_ENABLE
 #define MVCPU_WIN_DISABLE	CPU_WIN_DISABLE
 
-#endif /* _ASM_ARCH_ARMADA_XP_H */
+#endif /* _MVEBU_SOC_H */

arch/arm/mach-mvebu/mbus.c

@@ -341,9 +341,6 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
 			w = &mbus_dram_info.cs[cs++];
 			w->cs_index = i;
 			w->mbus_attr = 0xf & ~(1 << i);
-#if defined(CONFIG_ARMADA_XP)
-			w->mbus_attr |= ATTR_HW_COHERENCY;
-#endif
 			w->base = base & DDR_BASE_CS_LOW_MASK;
 			w->size = (size | ~DDR_SIZE_MASK) + 1;
 		}

board/Marvell/db-88f6820-gp/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_DB_88F6820_GP
+
+config SYS_BOARD
+	default "db-88f6820-gp"
+
+config SYS_VENDOR
+	default "Marvell"
+
+config SYS_SOC
+	default "mvebu"
+
+config SYS_CONFIG_NAME
+	default "db-88f6820-gp"
+
+endif

board/Marvell/db-88f6820-gp/Makefile

@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= db-88f6820-gp.o

board/Marvell/db-88f6820-gp/binary.0

@@ -0,0 +1,16 @@
+--------
+WARNING:
+--------
+This file should contain the bin_hdr generated by the original Marvell
+U-Boot implementation. As this is currently not included in this
+U-Boot version, we have added this placeholder, so that the U-Boot
+image can be generated without errors.
+
+If you have a known to be working bin_hdr for your board, then you
+just need to replace this text file here with the binary header
+and recompile U-Boot.
+
+In a few weeks, mainline U-Boot will get support to generate the
+bin_hdr with the DDR training code itself. By implementing this code
+as SPL U-Boot. Then this file will not be needed any more and will
+get removed.

board/Marvell/db-88f6820-gp/db-88f6820-gp.c

@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BIT(nr)				(1UL << (nr))
+
+#define ETH_PHY_CTRL_REG		0
+#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
+#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
+
+/*
+ * Those values and defines are taken from the Marvell U-Boot version
+ * "u-boot-2013.01-2014_T3.0"
+ */
+#define DB_GP_88F68XX_GPP_OUT_ENA_LOW					\
+	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
+	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
+	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
+#define DB_GP_88F68XX_GPP_OUT_ENA_MID					\
+	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
+	   BIT(16) | BIT(17) | BIT(18)))
+
+#define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
+#define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x0
+#define DB_GP_88F68XX_GPP_POL_LOW	0x0
+#define DB_GP_88F68XX_GPP_POL_MID	0x0
+
+/* IO expander on Marvell GP board includes e.g. fan enabling */
+struct marvell_io_exp {
+	u8 chip;
+	u8 addr;
+	u8 val;
+};
+
+static struct marvell_io_exp io_exp[] = {
+	{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
+	{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
+	{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
+	{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
+	{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
+	{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
+	{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
+	{ 0x21, 3, 0xC0 }  /* Output Data, register#1 */
+};
+
+int board_early_init_f(void)
+{
+	/* Configure MPP */
+	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
+	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
+	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
+	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
+	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
+	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
+	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
+	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
+
+	/* Set GPP Out value */
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+
+	/* Set GPP Polarity */
+	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
+	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
+
+	/* Set GPP Out Enable */
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	int i;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Init I2C IO expanders */
+	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
+		i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: Marvell DB-88F6820-GP\n");
+
+	return 0;
+}

board/Marvell/db-88f6820-gp/kwbimage.cfg

@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY board/Marvell/db-88f6820-gp/binary.0 0000005b 00000068

board/Marvell/db-mv784mp-gp/Kconfig

@@ -7,7 +7,7 @@ config SYS_VENDOR
 	default "Marvell"
 
 config SYS_SOC
-	default "armada-xp"
+	default "mvebu"
 
 config SYS_CONFIG_NAME
 	default "db-mv784mp-gp"

board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c

@@ -86,7 +86,8 @@ int checkboard(void)
 /* Configure and enable MV88E1545 PHY */
 void reset_phy(void)
 {
-	u16 devadr = CONFIG_PHY_BASE_ADDR;
+	u8 phy_addr[] = CONFIG_PHY_ADDR;
+	u16 devadr = phy_addr[0];
 	char *name = "neta0";
 	u16 reg;
 

board/maxbcm/Kconfig

@@ -4,7 +4,7 @@ config SYS_BOARD
 	default "maxbcm"
 
 config SYS_SOC
-	default "armada-xp"
+	default "mvebu"
 
 config SYS_CONFIG_NAME
 	default "maxbcm"

board/maxbcm/maxbcm.c

@@ -12,7 +12,7 @@
 #include <linux/mbus.h>
 
 #include "../drivers/ddr/mvebu/ddr3_hw_training.h"
-#include "../arch/arm/mvebu-common/serdes/high_speed_env_spec.h"
+#include "../arch/arm/mach-mvebu/serdes/high_speed_env_spec.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

configs/db-88f6820-gp_defconfig

@@ -0,0 +1,2 @@
+CONFIG_ARM=y
+CONFIG_TARGET_DB_88F6820_GP=y

drivers/ddr/mvebu/ddr3_axp.h

@@ -35,7 +35,7 @@
 
 #define ECC_SUPPORT
 #define NEW_FABRIC_TWSI_ADDR		0x4E
-#ifdef DB_784MP_GP
+#ifdef CONFIG_DB_784MP_GP
 #define BUS_WIDTH_ECC_TWSI_ADDR		0x4E
 #else
 #define BUS_WIDTH_ECC_TWSI_ADDR		0x4F

include/configs/db-88f6820-gp.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_DB_88F6820_GP_H
+#define _CONFIG_DB_88F6820_GP_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_ARMADA_XP		/* SOC Family Name */
+#define CONFIG_DB_88F6820_GP		/* Board target name for DDR training */
+
+#define CONFIG_SYS_L2_PL310
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define	CONFIG_SYS_TEXT_BASE	0x04000000
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		1000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define CONFIG_PHY_ADDR			{ 1, 0 }
+#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII
+#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#endif /* _CONFIG_DB_88F6820_GP_H */

include/configs/db-mv784mp-gp.h

@@ -53,7 +53,7 @@
 #define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
 
 #define CONFIG_PHY_MARVELL		/* there is a marvell phy */
-#define CONFIG_PHY_BASE_ADDR	0x10
+#define CONFIG_PHY_ADDR			{ 0x10, 0x11, 0x12, 0x13 }
 #define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_QSGMII
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 #define CONFIG_RESET_PHY_R
@@ -100,7 +100,6 @@
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"arch/arm/mvebu-common/u-boot-spl.lds"
 
 /* SPL related SPI defines */
 #define CONFIG_SPL_SPI_SUPPORT

include/configs/maxbcm.h

@@ -53,7 +53,7 @@
 #define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
 
 #define CONFIG_PHY_MARVELL		/* there is a marvell phy */
-#define CONFIG_PHY_BASE_ADDR	0x0
+#define CONFIG_PHY_ADDR			{ 0x0, 0x1, 0x2, 0x3 }
 #define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_SGMII
 #define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */
 #define CONFIG_RESET_PHY_R
@@ -100,7 +100,6 @@
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"arch/arm/mvebu-common/u-boot-spl.lds"
 
 /* SPL related SPI defines */
 #define CONFIG_SPL_SPI_SUPPORT

include/configs/mv-common.h

@@ -57,6 +57,7 @@
 					  115200,230400, 460800, 921600 }
 /* auto boot */
 #define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+#define CONFIG_PREBOOT
 
 /*
  * For booting Linux, the board info and command line data