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@ -29,8 +29,6 @@ |
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/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ |
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/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_SUPPORT_RAW_INITRD |
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#define CONFIG_SUPPORT_RAW_INITRD |
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/* Cache Definitions */ |
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/* Cache Definitions */ |
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@ -56,7 +54,6 @@ |
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/* Flat Device Tree Definitions */ |
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/* Flat Device Tree Definitions */ |
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#define CONFIG_OF_LIBFDT |
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#define CONFIG_OF_LIBFDT |
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/* SMP Spin Table Definitions */ |
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/* SMP Spin Table Definitions */ |
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#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP |
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#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP |
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#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) |
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#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) |
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@ -79,13 +76,6 @@ |
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#define V2M_BASE 0x80000000 |
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#define V2M_BASE 0x80000000 |
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/*
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* Physical addresses, offset from V2M_PA_CS0-3 |
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*/ |
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#define V2M_NOR0 (V2M_PA_CS0) |
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#define V2M_NOR1 (V2M_PA_CS4) |
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#define V2M_SRAM (V2M_PA_CS1) |
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/* Common peripherals relative to CS7. */ |
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/* Common peripherals relative to CS7. */ |
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#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) |
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#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) |
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#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) |
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#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) |
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@ -183,7 +173,6 @@ |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_DHCP |
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#define CONFIG_CMD_PXE |
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#define CONFIG_CMD_PXE |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_ENV |
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#define CONFIG_CMD_FLASH |
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#define CONFIG_CMD_IMI |
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#define CONFIG_CMD_IMI |
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#define CONFIG_CMD_LOADB |
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#define CONFIG_CMD_LOADB |
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#define CONFIG_CMD_MEMORY |
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#define CONFIG_CMD_MEMORY |
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@ -266,4 +255,27 @@ |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_SYS_MAXARGS 64 /* max command args */ |
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#define CONFIG_SYS_MAXARGS 64 /* max command args */ |
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/* Flash memory is available on the Juno board only */ |
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#ifndef CONFIG_TARGET_VEXPRESS64_JUNO |
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#define CONFIG_SYS_NO_FLASH |
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#else |
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#define CONFIG_CMD_FLASH |
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#define CONFIG_SYS_FLASH_CFI 1 |
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#define CONFIG_FLASH_CFI_DRIVER 1 |
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#define CONFIG_SYS_FLASH_BASE 0x08000000 |
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#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 |
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/* Timeout values in ticks */ |
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ |
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/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ |
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#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ |
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ |
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#endif |
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#endif /* __VEXPRESS_AEMV8A_H */ |
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#endif /* __VEXPRESS_AEMV8A_H */ |
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