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SPEAr : nand driver support for SPEAr SoCs

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SPEAr SoCs contain an FSMC controller which can be used to interface
with a range of memories eg. NAND, SRAM, NOR.
Currently, this driver supports interfacing FSMC with NAND memories

Signed-off-by: Vipin <vipin.kumar@st.com>
master
Vipin KUMAR 15 years ago committed by Tom Rix
parent a6e34f76c5
commit 165fa406ad
3 changed files with 182 additions and 0 deletions
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  1. 1
      drivers/mtd/nand/Makefile
  2. 124
      drivers/mtd/nand/spr_nand.c
  3. 57
      include/asm-arm/arch-spear/spr_nand.h

1
drivers/mtd/nand/Makefile
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@ -47,6 +47,7 @@ COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
endif endif

124
drivers/mtd/nand/spr_nand.c
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@ -0,0 +1,124 @@
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <nand.h>
#include <linux/mtd/nand_ecc.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spr_nand.h>
static struct fsmc_regs *const fsmc_regs_p =
(struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE;
static struct nand_ecclayout spear_nand_ecclayout = {
.eccbytes = 24,
.eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
.oobfree = {
{.offset = 8, .length = 8},
{.offset = 24, .length = 8},
{.offset = 40, .length = 8},
{.offset = 56, .length = 8},
{.offset = 72, .length = 8},
{.offset = 88, .length = 8},
{.offset = 104, .length = 8},
{.offset = 120, .length = 8}
}
};
static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
{
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
IO_ADDR_W = (ulong)this->IO_ADDR_W;
IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
if (ctrl & NAND_CLE)
IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
if (ctrl & NAND_NCE) {
writel(readl(&fsmc_regs_p->genmemctrl_pc) |
FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc);
} else {
writel(readl(&fsmc_regs_p->genmemctrl_pc) &
~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc);
}
this->IO_ADDR_W = (void *)IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int spear_read_hwecc(struct mtd_info *mtd,
const u_char *data, u_char ecc[3])
{
u_int ecc_tmp;
/* read the h/w ECC */
ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc);
ecc[0] = (u_char) (ecc_tmp & 0xFF);
ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8);
ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16);
return 0;
}
void spear_enable_hwecc(struct mtd_info *mtd, int mode)
{
writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80,
&fsmc_regs_p->genmemctrl_pc);
writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN,
&fsmc_regs_p->genmemctrl_pc);
writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN,
&fsmc_regs_p->genmemctrl_pc);
}
int spear_nand_init(struct nand_chip *nand)
{
writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
&fsmc_regs_p->genmemctrl_pc);
writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1,
&fsmc_regs_p->genmemctrl_pc);
writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
&fsmc_regs_p->genmemctrl_comm);
writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
&fsmc_regs_p->genmemctrl_attrib);
nand->options = 0;
nand->ecc.mode = NAND_ECC_HW;
nand->ecc.layout = &spear_nand_ecclayout;
nand->ecc.size = 512;
nand->ecc.bytes = 3;
nand->ecc.calculate = spear_read_hwecc;
nand->ecc.hwctl = spear_enable_hwecc;
nand->ecc.correct = nand_correct_data;
nand->cmd_ctrl = spear_nand_hwcontrol;
return 0;
}

57
include/asm-arm/arch-spear/spr_nand.h
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@ -0,0 +1,57 @@
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SPR_NAND_H__
#define __SPR_NAND_H__
struct fsmc_regs {
u32 reserved_1[0x10];
u32 genmemctrl_pc;
u32 reserved_2;
u32 genmemctrl_comm;
u32 genmemctrl_attrib;
u32 reserved_3;
u32 genmemctrl_ecc;
};
/* genmemctrl_pc register definitions */
#define FSMC_RESET (1 << 0)
#define FSMC_WAITON (1 << 1)
#define FSMC_ENABLE (1 << 2)
#define FSMC_DEVTYPE_NAND (1 << 3)
#define FSMC_DEVWID_8 (0 << 4)
#define FSMC_DEVWID_16 (1 << 4)
#define FSMC_ECCEN (1 << 6)
#define FSMC_ECCPLEN_512 (0 << 7)
#define FSMC_ECCPLEN_256 (1 << 7)
#define FSMC_TCLR_1 (1 << 9)
#define FSMC_TAR_1 (1 << 13)
/* genmemctrl_comm register definitions */
#define FSMC_TSET_0 (0 << 0)
#define FSMC_TWAIT_6 (6 << 8)
#define FSMC_THOLD_4 (4 << 16)
#define FSMC_THIZ_1 (1 << 24)
extern int spear_nand_init(struct nand_chip *nand);
#endif
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