@ -255,7 +255,7 @@ int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
if ( miiphy_read ( devname , addr , MII_PHYSID2 , & tmp ) ! = 0 ) {
debug ( " PHY ID register 2 read failed \n " ) ;
return ( - 1 ) ;
return - 1 ;
}
reg = tmp ;
@ -263,12 +263,12 @@ int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
if ( reg = = 0xFFFF ) {
/* No physical device present at this address */
return ( - 1 ) ;
return - 1 ;
}
if ( miiphy_read ( devname , addr , MII_PHYSID1 , & tmp ) ! = 0 ) {
debug ( " PHY ID register 1 read failed \n " ) ;
return ( - 1 ) ;
return - 1 ;
}
reg | = tmp < < 16 ;
debug ( " PHY_PHYIDR[1,2] @ 0x%x = 0x%08x \n " , addr , reg ) ;
@ -276,7 +276,7 @@ int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
* oui = ( reg > > 10 ) ;
* model = ( unsigned char ) ( ( reg > > 4 ) & 0x0000003F ) ;
* rev = ( unsigned char ) ( reg & 0x0000000F ) ;
return ( 0 ) ;
return 0 ;
}
/*****************************************************************************
@ -292,11 +292,11 @@ int miiphy_reset(const char *devname, unsigned char addr)
if ( miiphy_read ( devname , addr , MII_BMCR , & reg ) ! = 0 ) {
debug ( " PHY status read failed \n " ) ;
return ( - 1 ) ;
return - 1 ;
}
if ( miiphy_write ( devname , addr , MII_BMCR , reg | BMCR_RESET ) ! = 0 ) {
debug ( " PHY reset failed \n " ) ;
return ( - 1 ) ;
return - 1 ;
}
# ifdef CONFIG_PHY_RESET_DELAY
udelay ( CONFIG_PHY_RESET_DELAY ) ; /* Intel LXT971A needs this */
@ -315,12 +315,12 @@ int miiphy_reset(const char *devname, unsigned char addr)
udelay ( 1000 ) ;
}
if ( ( reg & 0x8000 ) = = 0 ) {
return ( 0 ) ;
return 0 ;
} else {
puts ( " PHY reset timed out \n " ) ;
return ( - 1 ) ;
return - 1 ;
}
return ( 0 ) ;
return 0 ;
}
/*****************************************************************************
@ -338,9 +338,9 @@ int miiphy_speed(const char *devname, unsigned char addr)
* Check for 1000 BASE - X . If it is supported , then assume that the speed
* is 1000.
*/
if ( miiphy_is_1000base_x ( devname , addr ) ) {
if ( miiphy_is_1000base_x ( devname , addr ) )
return _1000BASET ;
}
/*
* No 1000 BASE - X , so assume 1000 BASE - T / 100 BASE - TX / 10 BASE - T register set .
*/
@ -350,9 +350,9 @@ int miiphy_speed(const char *devname, unsigned char addr)
goto miiphy_read_failed ;
}
if ( btsr ! = 0xFFFF & &
( btsr & ( PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD ) ) ) {
( btsr & ( PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD ) ) )
return _1000BASET ;
}
# endif /* CONFIG_PHY_GIGE */
/* Check Basic Management Control Register first. */
@ -470,14 +470,14 @@ int miiphy_link(const char *devname, unsigned char addr)
( void ) miiphy_read ( devname , addr , MII_BMSR , & reg ) ;
if ( miiphy_read ( devname , addr , MII_BMSR , & reg ) ) {
puts ( " MII_BMSR read failed, assuming no link \n " ) ;
return ( 0 ) ;
return 0 ;
}
/* Determine if a link is active */
if ( ( reg & BMSR_LSTATUS ) ! = 0 ) {
return ( 1 ) ;
return 1 ;
} else {
return ( 0 ) ;
return 0 ;
}
}
# endif