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imx: mx6q DDR3 init: Fix RST_to_CKE

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MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC
specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded
as 0x23 for the bit-field MMDC1_MDOR[5:0].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
master
Benoît Thébaudeau 12 years ago committed by Stefano Babic
parent ada02b8463
commit 1791b1f97f
1 changed files with 1 additions and 1 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg

2
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
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@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2
DATA 4 0x021b0030 0x005A1021
DATA 4 0x021b0030 0x005A1023
DATA 4 0x021b0008 0x09444040
DATA 4 0x021b0004 0x00025576
DATA 4 0x021b0040 0x00000027

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