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@ -10,27 +10,25 @@ |
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#include <common.h> |
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#include <net.h> |
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#include <config.h> |
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#include <dm.h> |
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#include <console.h> |
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#include <malloc.h> |
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#include <asm/io.h> |
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#include <phy.h> |
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#include <miiphy.h> |
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#include <fdtdec.h> |
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#include <asm-generic/errno.h> |
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#include <linux/kernel.h> |
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#undef DEBUG |
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DECLARE_GLOBAL_DATA_PTR; |
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#define ENET_ADDR_LENGTH 6 |
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/* EmacLite constants */ |
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#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */ |
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#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ |
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#define XEL_TSR_OFFSET 0x07FC /* Tx status */ |
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#define XEL_RSR_OFFSET 0x17FC /* Rx status */ |
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#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ |
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#define ETH_FCS_LEN 4 /* Octets in the FCS */ |
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/* Xmit complete */ |
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#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL |
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/* Xmit interrupt enable bit */ |
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#define XEL_TSR_XMIT_IE_MASK 0x00000008UL |
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/* Buffer is active, SW bit only */ |
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#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL |
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/* Program the MAC address */ |
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#define XEL_TSR_PROGRAM_MASK 0x00000002UL |
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/* define for programming the MAC address into the EMAC Lite */ |
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@ -46,14 +44,56 @@ |
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/* Recv interrupt enable bit */ |
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#define XEL_RSR_RECV_IE_MASK 0x00000008UL |
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/* MDIO Address Register Bit Masks */ |
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#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ |
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#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ |
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#define XEL_MDIOADDR_PHYADR_SHIFT 5 |
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#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ |
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/* MDIO Write Data Register Bit Masks */ |
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#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ |
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/* MDIO Read Data Register Bit Masks */ |
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#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ |
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/* MDIO Control Register Bit Masks */ |
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#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ |
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#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ |
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struct emaclite_regs { |
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u32 tx_ping; /* 0x0 - TX Ping buffer */ |
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u32 reserved1[504]; |
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u32 mdioaddr; /* 0x7e4 - MDIO Address Register */ |
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u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */ |
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u32 mdiord;/* 0x7ec - MDIO Read Data Register */ |
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u32 mdioctrl; /* 0x7f0 - MDIO Control Register */ |
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u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */ |
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u32 global_interrupt; /* 0x7f8 - Global interrupt enable */ |
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u32 tx_ping_tsr; /* 0x7fc - Tx status */ |
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u32 tx_pong; /* 0x800 - TX Pong buffer */ |
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u32 reserved2[508]; |
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u32 tx_pong_tplr; /* 0xff4 - Tx packet length */ |
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u32 reserved3; /* 0xff8 */ |
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u32 tx_pong_tsr; /* 0xffc - Tx status */ |
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u32 rx_ping; /* 0x1000 - Receive Buffer */ |
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u32 reserved4[510]; |
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u32 rx_ping_rsr; /* 0x17fc - Rx status */ |
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u32 rx_pong; /* 0x1800 - Receive Buffer */ |
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u32 reserved5[510]; |
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u32 rx_pong_rsr; /* 0x1ffc - Rx status */ |
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}; |
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struct xemaclite { |
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u32 nexttxbuffertouse; /* Next TX buffer to write to */ |
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u32 nextrxbuffertouse; /* Next RX buffer to read from */ |
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bool use_rx_pong_buffer_next; /* Next RX buffer to read from */ |
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u32 txpp; /* TX ping pong buffer */ |
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u32 rxpp; /* RX ping pong buffer */ |
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int phyaddr; |
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struct emaclite_regs *regs; |
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struct phy_device *phydev; |
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struct mii_dev *bus; |
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}; |
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static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ |
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static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */ |
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static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) |
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{ |
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@ -81,7 +121,7 @@ static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount) |
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*to8ptr++ = *from8ptr++; |
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} |
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static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) |
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static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount) |
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{ |
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u32 i; |
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u32 alignbuffer; |
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@ -107,42 +147,206 @@ static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount) |
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*to32ptr++ = alignbuffer; |
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} |
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static void emaclite_halt(struct eth_device *dev) |
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static int wait_for_bit(const char *func, u32 *reg, const u32 mask, |
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bool set, unsigned int timeout) |
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{ |
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u32 val; |
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unsigned long start = get_timer(0); |
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while (1) { |
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val = readl(reg); |
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if (!set) |
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val = ~val; |
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if ((val & mask) == mask) |
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return 0; |
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if (get_timer(start) > timeout) |
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break; |
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if (ctrlc()) { |
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puts("Abort\n"); |
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return -EINTR; |
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} |
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udelay(1); |
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} |
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", |
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func, reg, mask, set); |
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return -ETIMEDOUT; |
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} |
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static int mdio_wait(struct emaclite_regs *regs) |
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{ |
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debug("eth_halt\n"); |
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return wait_for_bit(__func__, ®s->mdioctrl, |
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XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000); |
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} |
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static int emaclite_init(struct eth_device *dev, bd_t *bis) |
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static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, |
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u16 *data) |
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{ |
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struct xemaclite *emaclite = dev->priv; |
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struct emaclite_regs *regs = emaclite->regs; |
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if (mdio_wait(regs)) |
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return 1; |
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u32 ctrl_reg = in_be32(®s->mdioctrl); |
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out_be32(®s->mdioaddr, XEL_MDIOADDR_OP_MASK | |
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((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); |
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out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); |
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if (mdio_wait(regs)) |
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return 1; |
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/* Read data */ |
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*data = in_be32(®s->mdiord); |
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return 0; |
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} |
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static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum, |
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u16 data) |
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{ |
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struct emaclite_regs *regs = emaclite->regs; |
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if (mdio_wait(regs)) |
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return 1; |
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/*
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* Write the PHY address, register number and clear the OP bit in the |
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* MDIO Address register and then write the value into the MDIO Write |
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* Data register. Finally, set the Status bit in the MDIO Control |
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* register to start a MDIO write transaction. |
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*/ |
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u32 ctrl_reg = in_be32(®s->mdioctrl); |
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out_be32(®s->mdioaddr, ~XEL_MDIOADDR_OP_MASK & |
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((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum)); |
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out_be32(®s->mdiowr, data); |
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out_be32(®s->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK); |
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if (mdio_wait(regs)) |
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return 1; |
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return 0; |
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} |
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static void emaclite_stop(struct udevice *dev) |
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{ |
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debug("eth_stop\n"); |
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} |
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/* Use MII register 1 (MII status register) to detect PHY */ |
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#define PHY_DETECT_REG 1 |
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/* Mask used to verify certain PHY features (or register contents)
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* in the register above: |
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* 0x1000: 10Mbps full duplex support |
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* 0x0800: 10Mbps half duplex support |
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* 0x0008: Auto-negotiation support |
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*/ |
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#define PHY_DETECT_MASK 0x1808 |
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static int setup_phy(struct udevice *dev) |
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{ |
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int i; |
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u16 phyreg; |
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struct xemaclite *emaclite = dev_get_priv(dev); |
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struct phy_device *phydev; |
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u32 supported = SUPPORTED_10baseT_Half | |
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SUPPORTED_10baseT_Full | |
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SUPPORTED_100baseT_Half | |
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SUPPORTED_100baseT_Full; |
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if (emaclite->phyaddr != -1) { |
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phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg); |
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if ((phyreg != 0xFFFF) && |
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { |
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/* Found a valid PHY address */ |
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debug("Default phy address %d is valid\n", |
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emaclite->phyaddr); |
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} else { |
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debug("PHY address is not setup correctly %d\n", |
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emaclite->phyaddr); |
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emaclite->phyaddr = -1; |
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} |
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} |
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if (emaclite->phyaddr == -1) { |
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/* detect the PHY address */ |
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for (i = 31; i >= 0; i--) { |
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phyread(emaclite, i, PHY_DETECT_REG, &phyreg); |
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if ((phyreg != 0xFFFF) && |
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) { |
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/* Found a valid PHY address */ |
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emaclite->phyaddr = i; |
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debug("emaclite: Found valid phy address, %d\n", |
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i); |
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break; |
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} |
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} |
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} |
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/* interface - look at tsec */ |
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phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev, |
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PHY_INTERFACE_MODE_MII); |
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/*
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* Phy can support 1000baseT but device NOT that's why phydev->supported |
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* must be setup for 1000baseT. phydev->advertising setups what speeds |
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* will be used for autonegotiation where 1000baseT must be disabled. |
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*/ |
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phydev->supported = supported | SUPPORTED_1000baseT_Half | |
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SUPPORTED_1000baseT_Full; |
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phydev->advertising = supported; |
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emaclite->phydev = phydev; |
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phy_config(phydev); |
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phy_startup(phydev); |
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if (!phydev->link) { |
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printf("%s: No link.\n", phydev->dev->name); |
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return 0; |
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} |
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/* Do not setup anything */ |
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return 1; |
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} |
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static int emaclite_start(struct udevice *dev) |
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{ |
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struct xemaclite *emaclite = dev_get_priv(dev); |
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struct eth_pdata *pdata = dev_get_platdata(dev); |
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struct emaclite_regs *regs = emaclite->regs; |
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debug("EmacLite Initialization Started\n"); |
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/*
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* TX - TX_PING & TX_PONG initialization |
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*/ |
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/* Restart PING TX */ |
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out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); |
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out_be32(®s->tx_ping_tsr, 0); |
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/* Copy MAC address */ |
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xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH); |
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xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping, |
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ENET_ADDR_LENGTH); |
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/* Set the length */ |
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out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); |
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out_be32(®s->tx_ping_tplr, ENET_ADDR_LENGTH); |
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/* Update the MAC address in the EMAC Lite */ |
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out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR); |
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out_be32(®s->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR); |
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/* Wait for EMAC Lite to finish with the MAC address update */ |
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while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) & |
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while ((in_be32 (®s->tx_ping_tsr) & |
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XEL_TSR_PROG_MAC_ADDR) != 0) |
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; |
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if (emaclite->txpp) { |
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/* The same operation with PONG TX */ |
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out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0); |
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xemaclite_alignedwrite(dev->enetaddr, dev->iobase + |
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XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH); |
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out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH); |
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out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, |
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XEL_TSR_PROG_MAC_ADDR); |
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while ((in_be32 (dev->iobase + XEL_TSR_OFFSET + |
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XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0) |
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out_be32(®s->tx_pong_tsr, 0); |
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xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong, |
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ENET_ADDR_LENGTH); |
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out_be32(®s->tx_pong_tplr, ENET_ADDR_LENGTH); |
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out_be32(®s->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR); |
|
|
|
|
while ((in_be32(®s->tx_pong_tsr) & |
|
|
|
|
XEL_TSR_PROG_MAC_ADDR) != 0) |
|
|
|
|
; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
@ -150,52 +354,48 @@ static int emaclite_init(struct eth_device *dev, bd_t *bis) |
|
|
|
|
* RX - RX_PING & RX_PONG initialization |
|
|
|
|
*/ |
|
|
|
|
/* Write out the value to flush the RX buffer */ |
|
|
|
|
out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK); |
|
|
|
|
out_be32(®s->rx_ping_rsr, XEL_RSR_RECV_IE_MASK); |
|
|
|
|
|
|
|
|
|
if (emaclite->rxpp) |
|
|
|
|
out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET, |
|
|
|
|
XEL_RSR_RECV_IE_MASK); |
|
|
|
|
out_be32(®s->rx_pong_rsr, XEL_RSR_RECV_IE_MASK); |
|
|
|
|
|
|
|
|
|
out_be32(®s->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK); |
|
|
|
|
if (in_be32(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) |
|
|
|
|
if (!setup_phy(dev)) |
|
|
|
|
return -1; |
|
|
|
|
|
|
|
|
|
debug("EmacLite Initialization complete\n"); |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
static int xemaclite_txbufferavailable(struct eth_device *dev) |
|
|
|
|
static int xemaclite_txbufferavailable(struct xemaclite *emaclite) |
|
|
|
|
{ |
|
|
|
|
u32 reg; |
|
|
|
|
u32 txpingbusy; |
|
|
|
|
u32 txpongbusy; |
|
|
|
|
struct xemaclite *emaclite = dev->priv; |
|
|
|
|
u32 tmp; |
|
|
|
|
struct emaclite_regs *regs = emaclite->regs; |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Read the other buffer register |
|
|
|
|
* and determine if the other buffer is available |
|
|
|
|
*/ |
|
|
|
|
reg = in_be32 (dev->iobase + |
|
|
|
|
emaclite->nexttxbuffertouse + 0); |
|
|
|
|
txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == |
|
|
|
|
XEL_TSR_XMIT_BUSY_MASK); |
|
|
|
|
|
|
|
|
|
reg = in_be32 (dev->iobase + |
|
|
|
|
(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0); |
|
|
|
|
txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) == |
|
|
|
|
XEL_TSR_XMIT_BUSY_MASK); |
|
|
|
|
tmp = ~in_be32(®s->tx_ping_tsr); |
|
|
|
|
if (emaclite->txpp) |
|
|
|
|
tmp |= ~in_be32(®s->tx_pong_tsr); |
|
|
|
|
|
|
|
|
|
return !(txpingbusy && txpongbusy); |
|
|
|
|
return !(tmp & XEL_TSR_XMIT_BUSY_MASK); |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
static int emaclite_send(struct eth_device *dev, void *ptr, int len) |
|
|
|
|
static int emaclite_send(struct udevice *dev, void *ptr, int len) |
|
|
|
|
{ |
|
|
|
|
u32 reg; |
|
|
|
|
u32 baseaddress; |
|
|
|
|
struct xemaclite *emaclite = dev->priv; |
|
|
|
|
struct xemaclite *emaclite = dev_get_priv(dev); |
|
|
|
|
struct emaclite_regs *regs = emaclite->regs; |
|
|
|
|
|
|
|
|
|
u32 maxtry = 1000; |
|
|
|
|
|
|
|
|
|
if (len > PKTSIZE) |
|
|
|
|
len = PKTSIZE; |
|
|
|
|
|
|
|
|
|
while (!xemaclite_txbufferavailable(dev) && maxtry) { |
|
|
|
|
while (xemaclite_txbufferavailable(emaclite) && maxtry) { |
|
|
|
|
udelay(10); |
|
|
|
|
maxtry--; |
|
|
|
|
} |
|
|
|
|
@ -203,58 +403,40 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) |
|
|
|
|
if (!maxtry) { |
|
|
|
|
printf("Error: Timeout waiting for ethernet TX buffer\n"); |
|
|
|
|
/* Restart PING TX */ |
|
|
|
|
out_be32 (dev->iobase + XEL_TSR_OFFSET, 0); |
|
|
|
|
out_be32(®s->tx_ping_tsr, 0); |
|
|
|
|
if (emaclite->txpp) { |
|
|
|
|
out_be32 (dev->iobase + XEL_TSR_OFFSET + |
|
|
|
|
XEL_BUFFER_OFFSET, 0); |
|
|
|
|
out_be32(®s->tx_pong_tsr, 0); |
|
|
|
|
} |
|
|
|
|
return -1; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
/* Determine the expected TX buffer address */ |
|
|
|
|
baseaddress = (dev->iobase + emaclite->nexttxbuffertouse); |
|
|
|
|
|
|
|
|
|
/* Determine if the expected buffer address is empty */ |
|
|
|
|
reg = in_be32 (baseaddress + XEL_TSR_OFFSET); |
|
|
|
|
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) |
|
|
|
|
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) |
|
|
|
|
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { |
|
|
|
|
|
|
|
|
|
if (emaclite->txpp) |
|
|
|
|
emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET; |
|
|
|
|
|
|
|
|
|
debug("Send packet from 0x%x\n", baseaddress); |
|
|
|
|
reg = in_be32(®s->tx_ping_tsr); |
|
|
|
|
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { |
|
|
|
|
debug("Send packet from tx_ping buffer\n"); |
|
|
|
|
/* Write the frame to the buffer */ |
|
|
|
|
xemaclite_alignedwrite(ptr, baseaddress, len); |
|
|
|
|
out_be32 (baseaddress + XEL_TPLR_OFFSET,(len & |
|
|
|
|
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO))); |
|
|
|
|
reg = in_be32 (baseaddress + XEL_TSR_OFFSET); |
|
|
|
|
xemaclite_alignedwrite(ptr, ®s->tx_ping, len); |
|
|
|
|
out_be32(®s->tx_ping_tplr, len & |
|
|
|
|
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)); |
|
|
|
|
reg = in_be32(®s->tx_ping_tsr); |
|
|
|
|
reg |= XEL_TSR_XMIT_BUSY_MASK; |
|
|
|
|
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) |
|
|
|
|
reg |= XEL_TSR_XMIT_ACTIVE_MASK; |
|
|
|
|
out_be32 (baseaddress + XEL_TSR_OFFSET, reg); |
|
|
|
|
out_be32(®s->tx_ping_tsr, reg); |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
if (emaclite->txpp) { |
|
|
|
|
/* Switch to second buffer */ |
|
|
|
|
baseaddress ^= XEL_BUFFER_OFFSET; |
|
|
|
|
/* Determine if the expected buffer address is empty */ |
|
|
|
|
reg = in_be32 (baseaddress + XEL_TSR_OFFSET); |
|
|
|
|
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) |
|
|
|
|
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET) |
|
|
|
|
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) { |
|
|
|
|
debug("Send packet from 0x%x\n", baseaddress); |
|
|
|
|
reg = in_be32(®s->tx_pong_tsr); |
|
|
|
|
if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) { |
|
|
|
|
debug("Send packet from tx_pong buffer\n"); |
|
|
|
|
/* Write the frame to the buffer */ |
|
|
|
|
xemaclite_alignedwrite(ptr, baseaddress, len); |
|
|
|
|
out_be32 (baseaddress + XEL_TPLR_OFFSET, (len & |
|
|
|
|
(XEL_TPLR_LENGTH_MASK_HI | |
|
|
|
|
XEL_TPLR_LENGTH_MASK_LO))); |
|
|
|
|
reg = in_be32 (baseaddress + XEL_TSR_OFFSET); |
|
|
|
|
xemaclite_alignedwrite(ptr, ®s->tx_pong, len); |
|
|
|
|
out_be32(®s->tx_pong_tplr, len & |
|
|
|
|
(XEL_TPLR_LENGTH_MASK_HI | |
|
|
|
|
XEL_TPLR_LENGTH_MASK_LO)); |
|
|
|
|
reg = in_be32(®s->tx_pong_tsr); |
|
|
|
|
reg |= XEL_TSR_XMIT_BUSY_MASK; |
|
|
|
|
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0) |
|
|
|
|
reg |= XEL_TSR_XMIT_ACTIVE_MASK; |
|
|
|
|
out_be32 (baseaddress + XEL_TSR_OFFSET, reg); |
|
|
|
|
out_be32(®s->tx_pong_tsr, reg); |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
@ -263,130 +445,188 @@ static int emaclite_send(struct eth_device *dev, void *ptr, int len) |
|
|
|
|
return -1; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
static int emaclite_recv(struct eth_device *dev) |
|
|
|
|
static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp) |
|
|
|
|
{ |
|
|
|
|
u32 length; |
|
|
|
|
u32 reg; |
|
|
|
|
u32 baseaddress; |
|
|
|
|
u32 length, first_read, reg, attempt = 0; |
|
|
|
|
void *addr, *ack; |
|
|
|
|
struct xemaclite *emaclite = dev->priv; |
|
|
|
|
struct emaclite_regs *regs = emaclite->regs; |
|
|
|
|
struct ethernet_hdr *eth; |
|
|
|
|
struct ip_udp_hdr *ip; |
|
|
|
|
|
|
|
|
|
try_again: |
|
|
|
|
if (!emaclite->use_rx_pong_buffer_next) { |
|
|
|
|
reg = in_be32(®s->rx_ping_rsr); |
|
|
|
|
debug("Testing data at rx_ping\n"); |
|
|
|
|
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { |
|
|
|
|
debug("Data found in rx_ping buffer\n"); |
|
|
|
|
addr = ®s->rx_ping; |
|
|
|
|
ack = ®s->rx_ping_rsr; |
|
|
|
|
} else { |
|
|
|
|
debug("Data not found in rx_ping buffer\n"); |
|
|
|
|
/* Pong buffer is not available - return immediately */ |
|
|
|
|
if (!emaclite->rxpp) |
|
|
|
|
return -1; |
|
|
|
|
|
|
|
|
|
baseaddress = dev->iobase + emaclite->nextrxbuffertouse; |
|
|
|
|
reg = in_be32 (baseaddress + XEL_RSR_OFFSET); |
|
|
|
|
debug("Testing data at address 0x%x\n", baseaddress); |
|
|
|
|
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { |
|
|
|
|
if (emaclite->rxpp) |
|
|
|
|
emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET; |
|
|
|
|
/* Try pong buffer if this is first attempt */ |
|
|
|
|
if (attempt++) |
|
|
|
|
return -1; |
|
|
|
|
emaclite->use_rx_pong_buffer_next = |
|
|
|
|
!emaclite->use_rx_pong_buffer_next; |
|
|
|
|
goto try_again; |
|
|
|
|
} |
|
|
|
|
} else { |
|
|
|
|
|
|
|
|
|
if (!emaclite->rxpp) { |
|
|
|
|
debug("No data was available - address 0x%x\n", |
|
|
|
|
baseaddress); |
|
|
|
|
return 0; |
|
|
|
|
reg = in_be32(®s->rx_pong_rsr); |
|
|
|
|
debug("Testing data at rx_pong\n"); |
|
|
|
|
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { |
|
|
|
|
debug("Data found in rx_pong buffer\n"); |
|
|
|
|
addr = ®s->rx_pong; |
|
|
|
|
ack = ®s->rx_pong_rsr; |
|
|
|
|
} else { |
|
|
|
|
baseaddress ^= XEL_BUFFER_OFFSET; |
|
|
|
|
reg = in_be32 (baseaddress + XEL_RSR_OFFSET); |
|
|
|
|
if ((reg & XEL_RSR_RECV_DONE_MASK) != |
|
|
|
|
XEL_RSR_RECV_DONE_MASK) { |
|
|
|
|
debug("No data was available - address 0x%x\n", |
|
|
|
|
baseaddress); |
|
|
|
|
return 0; |
|
|
|
|
} |
|
|
|
|
debug("Data not found in rx_pong buffer\n"); |
|
|
|
|
/* Try ping buffer if this is first attempt */ |
|
|
|
|
if (attempt++) |
|
|
|
|
return -1; |
|
|
|
|
emaclite->use_rx_pong_buffer_next = |
|
|
|
|
!emaclite->use_rx_pong_buffer_next; |
|
|
|
|
goto try_again; |
|
|
|
|
} |
|
|
|
|
} |
|
|
|
|
/* Get the length of the frame that arrived */ |
|
|
|
|
switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) & |
|
|
|
|
0xFFFF0000 ) >> 16) { |
|
|
|
|
case 0x806: |
|
|
|
|
length = 42 + 20; /* FIXME size of ARP */ |
|
|
|
|
debug("ARP Packet\n"); |
|
|
|
|
break; |
|
|
|
|
case 0x800: |
|
|
|
|
length = 14 + 14 + |
|
|
|
|
(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + |
|
|
|
|
0x10))) & 0xFFFF0000) >> 16); |
|
|
|
|
/* FIXME size of IP packet */ |
|
|
|
|
debug ("IP Packet\n"); |
|
|
|
|
break; |
|
|
|
|
default: |
|
|
|
|
debug("Other Packet\n"); |
|
|
|
|
length = PKTSIZE; |
|
|
|
|
break; |
|
|
|
|
|
|
|
|
|
/* Read all bytes for ARP packet with 32bit alignment - 48bytes */ |
|
|
|
|
first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4); |
|
|
|
|
xemaclite_alignedread(addr, etherrxbuff, first_read); |
|
|
|
|
|
|
|
|
|
/* Detect real packet size */ |
|
|
|
|
eth = (struct ethernet_hdr *)etherrxbuff; |
|
|
|
|
switch (ntohs(eth->et_protlen)) { |
|
|
|
|
case PROT_ARP: |
|
|
|
|
length = first_read; |
|
|
|
|
debug("ARP Packet %x\n", length); |
|
|
|
|
break; |
|
|
|
|
case PROT_IP: |
|
|
|
|
ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE); |
|
|
|
|
length = ntohs(ip->ip_len); |
|
|
|
|
length += ETHER_HDR_SIZE + ETH_FCS_LEN; |
|
|
|
|
debug("IP Packet %x\n", length); |
|
|
|
|
break; |
|
|
|
|
default: |
|
|
|
|
debug("Other Packet\n"); |
|
|
|
|
length = PKTSIZE; |
|
|
|
|
break; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET), |
|
|
|
|
etherrxbuff, length); |
|
|
|
|
/* Read the rest of the packet which is longer then first read */ |
|
|
|
|
if (length != first_read) |
|
|
|
|
xemaclite_alignedread(addr + first_read, |
|
|
|
|
etherrxbuff + first_read, |
|
|
|
|
length - first_read); |
|
|
|
|
|
|
|
|
|
/* Acknowledge the frame */ |
|
|
|
|
reg = in_be32 (baseaddress + XEL_RSR_OFFSET); |
|
|
|
|
reg = in_be32(ack); |
|
|
|
|
reg &= ~XEL_RSR_RECV_DONE_MASK; |
|
|
|
|
out_be32 (baseaddress + XEL_RSR_OFFSET, reg); |
|
|
|
|
out_be32(ack, reg); |
|
|
|
|
|
|
|
|
|
debug("Packet receive from 0x%x, length %dB\n", baseaddress, length); |
|
|
|
|
net_process_received_packet((uchar *)etherrxbuff, length); |
|
|
|
|
debug("Packet receive from 0x%p, length %dB\n", addr, length); |
|
|
|
|
*packetp = etherrxbuff; |
|
|
|
|
return length; |
|
|
|
|
|
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr, |
|
|
|
|
int txpp, int rxpp) |
|
|
|
|
static int emaclite_miiphy_read(struct mii_dev *bus, int addr, |
|
|
|
|
int devad, int reg) |
|
|
|
|
{ |
|
|
|
|
struct eth_device *dev; |
|
|
|
|
struct xemaclite *emaclite; |
|
|
|
|
u32 ret; |
|
|
|
|
u16 val = 0; |
|
|
|
|
|
|
|
|
|
dev = calloc(1, sizeof(*dev)); |
|
|
|
|
if (dev == NULL) |
|
|
|
|
return -1; |
|
|
|
|
ret = phyread(bus->priv, addr, reg, &val); |
|
|
|
|
debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret); |
|
|
|
|
return val; |
|
|
|
|
} |
|
|
|
|
|
|
|
|
|
emaclite = calloc(1, sizeof(struct xemaclite)); |
|
|
|
|
if (emaclite == NULL) { |
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free(dev); |
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return -1; |
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} |
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static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad, |
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int reg, u16 value) |
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{ |
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debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value); |
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return phywrite(bus->priv, addr, reg, value); |
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} |
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static int emaclite_probe(struct udevice *dev) |
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{ |
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struct xemaclite *emaclite = dev_get_priv(dev); |
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int ret; |
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dev->priv = emaclite; |
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emaclite->bus = mdio_alloc(); |
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emaclite->bus->read = emaclite_miiphy_read; |
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emaclite->bus->write = emaclite_miiphy_write; |
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emaclite->bus->priv = emaclite; |
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strcpy(emaclite->bus->name, "emaclite"); |
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emaclite->txpp = txpp; |
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emaclite->rxpp = rxpp; |
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ret = mdio_register(emaclite->bus); |
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if (ret) |
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return ret; |
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sprintf(dev->name, "Xelite.%lx", base_addr); |
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return 0; |
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} |
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dev->iobase = base_addr; |
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dev->init = emaclite_init; |
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dev->halt = emaclite_halt; |
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dev->send = emaclite_send; |
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dev->recv = emaclite_recv; |
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static int emaclite_remove(struct udevice *dev) |
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{ |
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struct xemaclite *emaclite = dev_get_priv(dev); |
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eth_register(dev); |
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free(emaclite->phydev); |
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mdio_unregister(emaclite->bus); |
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mdio_free(emaclite->bus); |
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return 1; |
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return 0; |
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} |
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#if CONFIG_IS_ENABLED(OF_CONTROL) |
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int xilinx_emaclite_of_init(const void *blob) |
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static const struct eth_ops emaclite_ops = { |
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.start = emaclite_start, |
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.send = emaclite_send, |
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.recv = emaclite_recv, |
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.stop = emaclite_stop, |
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}; |
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static int emaclite_ofdata_to_platdata(struct udevice *dev) |
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|
|
{ |
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struct eth_pdata *pdata = dev_get_platdata(dev); |
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struct xemaclite *emaclite = dev_get_priv(dev); |
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int offset = 0; |
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u32 ret = 0; |
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u32 reg; |
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do { |
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offset = fdt_node_offset_by_compatible(blob, offset, |
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"xlnx,xps-ethernetlite-1.00.a"); |
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if (offset != -1) { |
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reg = fdtdec_get_addr(blob, offset, "reg"); |
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if (reg != FDT_ADDR_T_NONE) { |
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u32 rxpp = fdtdec_get_int(blob, offset, |
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"xlnx,rx-ping-pong", 0); |
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u32 txpp = fdtdec_get_int(blob, offset, |
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"xlnx,tx-ping-pong", 0); |
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|
ret |= xilinx_emaclite_initialize(NULL, reg, |
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|
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txpp, rxpp); |
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|
|
} else { |
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debug("EMACLITE: Can't get base address\n"); |
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|
return -1; |
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|
|
} |
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|
|
} |
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|
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} while (offset != -1); |
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|
|
pdata->iobase = (phys_addr_t)dev_get_addr(dev); |
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|
|
emaclite->regs = (struct emaclite_regs *)pdata->iobase; |
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|
|
emaclite->phyaddr = -1; |
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|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, |
|
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|
|
"phy-handle"); |
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|
|
if (offset > 0) |
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|
|
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, |
|
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|
|
"reg", -1); |
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|
|
emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, |
|
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|
|
"xlnx,tx-ping-pong", 0); |
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|
|
emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, |
|
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|
|
"xlnx,rx-ping-pong", 0); |
|
|
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|
|
|
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|
|
return ret; |
|
|
|
|
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs, |
|
|
|
|
emaclite->phyaddr, emaclite->txpp, emaclite->rxpp); |
|
|
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|
|
return 0; |
|
|
|
|
} |
|
|
|
|
#endif |
|
|
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|
|
|
|
|
|
static const struct udevice_id emaclite_ids[] = { |
|
|
|
|
{ .compatible = "xlnx,xps-ethernetlite-1.00.a" }, |
|
|
|
|
{ } |
|
|
|
|
}; |
|
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(emaclite) = { |
|
|
|
|
.name = "emaclite", |
|
|
|
|
.id = UCLASS_ETH, |
|
|
|
|
.of_match = emaclite_ids, |
|
|
|
|
.ofdata_to_platdata = emaclite_ofdata_to_platdata, |
|
|
|
|
.probe = emaclite_probe, |
|
|
|
|
.remove = emaclite_remove, |
|
|
|
|
.ops = &emaclite_ops, |
|
|
|
|
.priv_auto_alloc_size = sizeof(struct xemaclite), |
|
|
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata), |
|
|
|
|
}; |
|
|
|
|
|
Tom Rini
9 years ago