Conflicts: arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>master
Stefano Babic
10 years ago
commit
1cad23c5f4
@ -1,19 +0,0 @@ |
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#
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# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
|
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# version 2, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
|
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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# more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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USE_PRIVATE_LIBGCC = yes
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@ -1,7 +0,0 @@ |
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#
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# (C) Copyright 2010-2013
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# NVIDIA Corporation <www.nvidia.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#/
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USE_PRIVATE_LIBGCC = yes
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@ -1,10 +0,0 @@ |
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#
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# (C) Copyright 2010,2011
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# NVIDIA Corporation <www.nvidia.com>
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#
|
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# (C) Copyright 2002
|
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# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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USE_PRIVATE_LIBGCC = yes
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@ -1,19 +0,0 @@ |
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#
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# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
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#
|
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# (C) Copyright 2002
|
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# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
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#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
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# under the terms and conditions of the GNU General Public License,
|
||||
# version 2, as published by the Free Software Foundation.
|
||||
#
|
||||
# This program is distributed in the hope it will be useful, but WITHOUT
|
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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# more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
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#
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USE_PRIVATE_LIBGCC = yes
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@ -1,6 +1,6 @@ |
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SECTION 0x0 BOOTABLE |
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TAG LAST |
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LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin |
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LOAD 0x1000 spl/u-boot-spl.bin |
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CALL 0x1000 0x0 |
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LOAD 0x40002000 OBJTREE/u-boot.bin |
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LOAD 0x40002000 u-boot.bin |
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CALL 0x40002000 0x0 |
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@ -1,8 +1,8 @@ |
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SECTION 0x0 BOOTABLE |
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TAG LAST |
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LOAD 0x1000 OBJTREE/spl/u-boot-spl.bin |
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LOAD 0x1000 spl/u-boot-spl.bin |
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LOAD IVT 0x8000 0x1000 |
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CALL HAB 0x8000 0x0 |
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LOAD 0x40002000 OBJTREE/u-boot.bin |
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LOAD 0x40002000 u-boot.bin |
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LOAD IVT 0x8000 0x40002000 |
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CALL HAB 0x8000 0x0 |
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@ -0,0 +1,138 @@ |
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/* |
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* Samsung's Exynos4 SoC common device tree source |
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* |
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* Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/include/ "skeleton.dtsi" |
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/ { |
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serial@13800000 { |
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compatible = "samsung,exynos4210-uart"; |
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reg = <0x13800000 0x3c>; |
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id = <0>; |
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}; |
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serial@13810000 { |
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compatible = "samsung,exynos4210-uart"; |
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reg = <0x13810000 0x3c>; |
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id = <1>; |
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}; |
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serial@13820000 { |
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compatible = "samsung,exynos4210-uart"; |
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reg = <0x13820000 0x3c>; |
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id = <2>; |
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}; |
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serial@13830000 { |
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compatible = "samsung,exynos4210-uart"; |
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reg = <0x13830000 0x3c>; |
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id = <3>; |
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}; |
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serial@13840000 { |
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compatible = "samsung,exynos4210-uart"; |
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reg = <0x13840000 0x3c>; |
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id = <4>; |
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}; |
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i2c@13860000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,s3c2440-i2c"; |
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interrupts = <0 0 0>; |
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}; |
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i2c@13870000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,s3c2440-i2c"; |
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interrupts = <1 1 0>; |
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}; |
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i2c@13880000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,s3c2440-i2c"; |
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interrupts = <2 2 0>; |
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}; |
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i2c@13890000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,s3c2440-i2c"; |
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interrupts = <3 3 0>; |
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}; |
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i2c@138a0000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,s3c2440-i2c"; |
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interrupts = <4 4 0>; |
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}; |
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i2c@138b0000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,s3c2440-i2c"; |
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interrupts = <5 5 0>; |
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}; |
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i2c@138c0000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,s3c2440-i2c"; |
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interrupts = <6 6 0>; |
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}; |
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i2c@138d0000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,s3c2440-i2c"; |
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interrupts = <7 7 0>; |
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}; |
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sdhci@12510000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,exynos-mmc"; |
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reg = <0x12510000 0x1000>; |
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interrupts = <0 75 0>; |
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}; |
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sdhci@12520000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,exynos-mmc"; |
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reg = <0x12520000 0x1000>; |
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interrupts = <0 76 0>; |
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}; |
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sdhci@12530000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,exynos-mmc"; |
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reg = <0x12530000 0x1000>; |
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interrupts = <0 77 0>; |
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}; |
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sdhci@12540000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "samsung,exynos-mmc"; |
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reg = <0x12540000 0x1000>; |
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interrupts = <0 78 0>; |
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}; |
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gpio: gpio { |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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@ -0,0 +1,45 @@ |
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/* |
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* Samsung's Exynos4210 based Origen board device tree source |
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* |
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* Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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/include/ "skeleton.dtsi" |
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/include/ "exynos4.dtsi" |
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/ { |
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model = "Insignal Origen evaluation board based on Exynos4210"; |
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compatible = "insignal,origen", "samsung,exynos4210"; |
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chosen { |
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bootargs =""; |
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}; |
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aliases { |
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serial0 = "/serial@13800000"; |
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console = "/serial@13820000"; |
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mmc2 = "sdhci@12530000"; |
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}; |
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sdhci@12510000 { |
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status = "disabled"; |
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}; |
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sdhci@12520000 { |
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status = "disabled"; |
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}; |
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sdhci@12530000 { |
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samsung,bus-width = <4>; |
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samsung,timing = <1 2 3>; |
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cd-gpios = <&gpio 0x2008002 0>; |
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}; |
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sdhci@12540000 { |
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status = "disabled"; |
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}; |
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}; |
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@ -0,0 +1,120 @@ |
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/* |
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* Samsung's Exynos4210 based Trats board device tree source |
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* |
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* Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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/include/ "exynos4.dtsi" |
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/ { |
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model = "Samsung Trats based on Exynos4210"; |
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compatible = "samsung,trats", "samsung,exynos4210"; |
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config { |
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samsung,dsim-device-name = "s6e8ax0"; |
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}; |
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aliases { |
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i2c0 = "/i2c@13860000"; |
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i2c1 = "/i2c@13870000"; |
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i2c2 = "/i2c@13880000"; |
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i2c3 = "/i2c@13890000"; |
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i2c4 = "/i2c@138a0000"; |
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i2c5 = "/i2c@138b0000"; |
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i2c6 = "/i2c@138c0000"; |
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i2c7 = "/i2c@138d0000"; |
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serial0 = "/serial@13800000"; |
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console = "/serial@13820000"; |
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mmc0 = "sdhci@12510000"; |
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mmc2 = "sdhci@12530000"; |
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}; |
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fimd@11c00000 { |
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compatible = "samsung,exynos-fimd"; |
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reg = <0x11c00000 0xa4>; |
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samsung,vl-freq = <60>; |
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samsung,vl-col = <720>; |
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samsung,vl-row = <1280>; |
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samsung,vl-width = <720>; |
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samsung,vl-height = <1280>; |
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samsung,vl-clkp = <0>; |
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samsung,vl-oep = <0>; |
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samsung,vl-hsp = <1>; |
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samsung,vl-vsp = <1>; |
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samsung,vl-dp = <1>; |
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samsung,vl-bpix = <4>; |
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samsung,vl-hspw = <5>; |
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samsung,vl-hbpd = <10>; |
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samsung,vl-hfpd = <10>; |
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samsung,vl-vspw = <2>; |
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samsung,vl-vbpd = <1>; |
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samsung,vl-vfpd = <13>; |
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samsung,vl-cmd-allow-len = <0xf>; |
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samsung,winid = <3>; |
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samsung,power-on-delay = <30>; |
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samsung,interface-mode = <1>; |
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samsung,mipi-enabled = <1>; |
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samsung,dp-enabled; |
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samsung,dual-lcd-enabled; |
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samsung,logo-on = <1>; |
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samsung,resolution = <0>; |
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samsung,rgb-mode = <0>; |
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}; |
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mipidsi@11c80000 { |
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compatible = "samsung,exynos-mipi-dsi"; |
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reg = <0x11c80000 0x5c>; |
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samsung,dsim-config-e-interface = <1>; |
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samsung,dsim-config-e-virtual-ch = <0>; |
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samsung,dsim-config-e-pixel-format = <7>; |
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samsung,dsim-config-e-burst-mode = <1>; |
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samsung,dsim-config-e-no-data-lane = <3>; |
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samsung,dsim-config-e-byte-clk = <0>; |
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samsung,dsim-config-hfp = <1>; |
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samsung,dsim-config-p = <3>; |
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samsung,dsim-config-m = <120>; |
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samsung,dsim-config-s = <1>; |
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samsung,dsim-config-pll-stable-time = <500>; |
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samsung,dsim-config-esc-clk = <20000000>; |
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samsung,dsim-config-stop-holding-cnt = <0x7ff>; |
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samsung,dsim-config-bta-timeout = <0xff>; |
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samsung,dsim-config-rx-timeout = <0xffff>; |
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samsung,dsim-device-id = <0xffffffff>; |
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samsung,dsim-device-bus-id = <0>; |
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samsung,dsim-device-reverse-panel = <1>; |
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}; |
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sdhci@12510000 { |
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samsung,bus-width = <8>; |
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samsung,timing = <1 3 3>; |
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pwr-gpios = <&gpio 0x2008002 0>; |
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}; |
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sdhci@12520000 { |
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status = "disabled"; |
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}; |
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sdhci@12530000 { |
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samsung,bus-width = <4>; |
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samsung,timing = <1 2 3>; |
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cd-gpios = <&gpio 0x20c6004 0>; |
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}; |
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sdhci@12540000 { |
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status = "disabled"; |
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}; |
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}; |
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@ -0,0 +1,83 @@ |
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/* |
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* Samsung's Exynos4210 based Universal C210 board device tree source |
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* |
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* Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/dts-v1/; |
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/include/ "exynos4.dtsi" |
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/ { |
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model = "Samsung Universal C210 based on Exynos4210 rev0"; |
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compatible = "samsung,universal_c210", "samsung,exynos4210"; |
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|
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aliases { |
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serial0 = "/serial@13800000"; |
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console = "/serial@13820000"; |
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mmc0 = "sdhci@12510000"; |
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mmc2 = "sdhci@12530000"; |
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}; |
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sdhci@12510000 { |
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samsung,bus-width = <8>; |
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samsung,timing = <1 3 3>; |
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pwr-gpios = <&gpio 0x2008002 0>; |
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}; |
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|
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sdhci@12520000 { |
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status = "disabled"; |
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}; |
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|
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sdhci@12530000 { |
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samsung,bus-width = <4>; |
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samsung,timing = <1 2 3>; |
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cd-gpios = <&gpio 0x20c6004 0>; |
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}; |
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|
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sdhci@12540000 { |
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status = "disabled"; |
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}; |
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|
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fimd@11c00000 { |
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compatible = "samsung,exynos-fimd"; |
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reg = <0x11c00000 0xa4>; |
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|
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samsung,vl-freq = <60>; |
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samsung,vl-col = <480>; |
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samsung,vl-row = <800>; |
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samsung,vl-width = <480>; |
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samsung,vl-height = <800>; |
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|
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samsung,vl-clkp = <0>; |
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samsung,vl-oep = <0>; |
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samsung,vl-hsp = <1>; |
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samsung,vl-vsp = <1>; |
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samsung,vl-dp = <1>; |
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samsung,vl-bpix = <4>; |
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|
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samsung,vl-hspw = <2>; |
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samsung,vl-hbpd = <16>; |
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samsung,vl-hfpd = <16>; |
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samsung,vl-vspw = <2>; |
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samsung,vl-vbpd = <8>; |
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samsung,vl-vfpd = <8>; |
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samsung,vl-cmd-allow-len = <0xf>; |
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|
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samsung,pclk_name = <1>; |
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samsung,sclk_div = <1>; |
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|
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samsung,winid = <0>; |
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samsung,power-on-delay = <10000>; |
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samsung,interface-mode = <1>; |
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samsung,mipi-enabled = <0>; |
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samsung,dp-enabled; |
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samsung,dual-lcd-enabled; |
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|
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samsung,logo-on = <1>; |
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samsung,resolution = <0>; |
||||
samsung,rgb-mode = <0>; |
||||
}; |
||||
}; |
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@ -0,0 +1,434 @@ |
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/* |
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* Samsung's Exynos4412 based Trats2 board device tree source |
||||
* |
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/dts-v1/; |
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/include/ "exynos4.dtsi" |
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|
||||
/ { |
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model = "Samsung Trats2 based on Exynos4412"; |
||||
compatible = "samsung,trats2", "samsung,exynos4412"; |
||||
|
||||
config { |
||||
samsung,dsim-device-name = "s6e8ax0"; |
||||
}; |
||||
|
||||
aliases { |
||||
i2c0 = "/i2c@13860000"; |
||||
i2c1 = "/i2c@13870000"; |
||||
i2c2 = "/i2c@13880000"; |
||||
i2c3 = "/i2c@13890000"; |
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i2c4 = "/i2c@138a0000"; |
||||
i2c5 = "/i2c@138b0000"; |
||||
i2c6 = "/i2c@138c0000"; |
||||
i2c7 = "/i2c@138d0000"; |
||||
serial0 = "/serial@13800000"; |
||||
console = "/serial@13820000"; |
||||
mmc0 = "sdhci@12510000"; |
||||
mmc2 = "sdhci@12530000"; |
||||
}; |
||||
|
||||
i2c@138d0000 { |
||||
samsung,i2c-sda-delay = <100>; |
||||
samsung,i2c-slave-addr = <0x10>; |
||||
samsung,i2c-max-bus-freq = <100000>; |
||||
status = "okay"; |
||||
|
||||
max77686_pmic@09 { |
||||
compatible = "maxim,max77686_pmic"; |
||||
interrupts = <7 0>; |
||||
reg = <0x09 0 0>; |
||||
#clock-cells = <1>; |
||||
|
||||
voltage-regulators { |
||||
ldo1_reg: ldo1 { |
||||
regulator-compatible = "LDO1"; |
||||
regulator-name = "VALIVE_1.0V_AP"; |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <1000000>; |
||||
regulator-always-on; |
||||
regulator-mem-on; |
||||
}; |
||||
|
||||
ldo2_reg: ldo2 { |
||||
regulator-compatible = "LDO2"; |
||||
regulator-name = "VM1M2_1.2V_AP"; |
||||
regulator-min-microvolt = <1200000>; |
||||
regulator-max-microvolt = <1200000>; |
||||
regulator-always-on; |
||||
regulator-mem-on; |
||||
}; |
||||
|
||||
ldo3_reg: ldo3 { |
||||
regulator-compatible = "LDO3"; |
||||
regulator-name = "VCC_1.8V_AP"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-always-on; |
||||
regulator-mem-on; |
||||
}; |
||||
|
||||
ldo4_reg: ldo4 { |
||||
regulator-compatible = "LDO4"; |
||||
regulator-name = "VCC_2.8V_AP"; |
||||
regulator-min-microvolt = <2800000>; |
||||
regulator-max-microvolt = <2800000>; |
||||
regulator-always-on; |
||||
regulator-mem-on; |
||||
}; |
||||
|
||||
ldo5_reg: ldo5 { |
||||
regulator-compatible = "LDO5"; |
||||
regulator-name = "VCC_1.8V_IO"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-always-on; |
||||
regulator-mem-on; |
||||
}; |
||||
|
||||
ldo6_reg: ldo6 { |
||||
regulator-compatible = "LDO6"; |
||||
regulator-name = "VMPLL_1.0V_AP"; |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <1000000>; |
||||
regulator-always-on; |
||||
regulator-mem-on; |
||||
}; |
||||
|
||||
ldo7_reg: ldo7 { |
||||
regulator-compatible = "LDO7"; |
||||
regulator-name = "VPLL_1.0V_AP"; |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <1000000>; |
||||
regulator-always-on; |
||||
regulator-mem-on; |
||||
}; |
||||
|
||||
ldo8_reg: ldo8 { |
||||
regulator-compatible = "LDO8"; |
||||
regulator-name = "VMIPI_1.0V"; |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <1000000>; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
ldo9_reg: ldo9 { |
||||
regulator-compatible = "LDO9"; |
||||
regulator-name = "CAM_ISP_MIPI_1.2V"; |
||||
regulator-min-microvolt = <1200000>; |
||||
regulator-max-microvolt = <1200000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo10_reg: ldo10 { |
||||
regulator-compatible = "LDO10"; |
||||
regulator-name = "VMIPI_1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
ldo11_reg: ldo11 { |
||||
regulator-compatible = "LDO11"; |
||||
regulator-name = "VABB1_1.95V"; |
||||
regulator-min-microvolt = <1950000>; |
||||
regulator-max-microvolt = <1950000>; |
||||
regulator-always-on; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
ldo12_reg: ldo12 { |
||||
regulator-compatible = "LDO12"; |
||||
regulator-name = "VUOTG_3.0V"; |
||||
regulator-min-microvolt = <3000000>; |
||||
regulator-max-microvolt = <3000000>; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
ldo13_reg: ldo13 { |
||||
regulator-compatible = "LDO13"; |
||||
regulator-name = "NFC_AVDD_1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo14_reg: ldo14 { |
||||
regulator-compatible = "LDO14"; |
||||
regulator-name = "VABB2_1.95V"; |
||||
regulator-min-microvolt = <1950000>; |
||||
regulator-max-microvolt = <1950000>; |
||||
regulator-always-on; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
ldo15_reg: ldo15 { |
||||
regulator-compatible = "LDO15"; |
||||
regulator-name = "VHSIC_1.0V"; |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <1000000>; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
ldo16_reg: ldo16 { |
||||
regulator-compatible = "LDO16"; |
||||
regulator-name = "VHSIC_1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
ldo17_reg: ldo17 { |
||||
regulator-compatible = "LDO17"; |
||||
regulator-name = "CAM_SENSOR_CORE_1.2V"; |
||||
regulator-min-microvolt = <1200000>; |
||||
regulator-max-microvolt = <1200000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo18_reg: ldo18 { |
||||
regulator-compatible = "LDO18"; |
||||
regulator-name = "CAM_ISP_SEN_IO_1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo19_reg: ldo19 { |
||||
regulator-compatible = "LDO19"; |
||||
regulator-name = "VT_CAM_1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo20_reg: ldo20 { |
||||
regulator-compatible = "LDO20"; |
||||
regulator-name = "VDDQ_PRE_1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo21_reg: ldo21 { |
||||
regulator-compatible = "LDO21"; |
||||
regulator-name = "VTF_2.8V"; |
||||
regulator-min-microvolt = <2800000>; |
||||
regulator-max-microvolt = <2800000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo22_reg: ldo22 { |
||||
regulator-compatible = "LDO22"; |
||||
regulator-name = "VMEM_VDD_2.8V"; |
||||
regulator-min-microvolt = <2800000>; |
||||
regulator-max-microvolt = <2800000>; |
||||
regulator-always-on; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
ldo23_reg: ldo23 { |
||||
regulator-compatible = "LDO23"; |
||||
regulator-name = "TSP_AVDD_3.3V"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo24_reg: ldo24 { |
||||
regulator-compatible = "LDO24"; |
||||
regulator-name = "TSP_VDD_1.8V"; |
||||
regulator-min-microvolt = <1800000>; |
||||
regulator-max-microvolt = <1800000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo25_reg: ldo25 { |
||||
regulator-compatible = "LDO25"; |
||||
regulator-name = "LCD_VCC_3.3V"; |
||||
regulator-min-microvolt = <2800000>; |
||||
regulator-max-microvolt = <2800000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
ldo26_reg: ldo26 { |
||||
regulator-compatible = "LDO26"; |
||||
regulator-name = "MOTOR_VCC_3.0V"; |
||||
regulator-min-microvolt = <3000000>; |
||||
regulator-max-microvolt = <3000000>; |
||||
regulator-mem-idle; |
||||
}; |
||||
|
||||
buck1_reg: buck1 { |
||||
regulator-compatible = "BUCK1"; |
||||
regulator-name = "vdd_mif"; |
||||
regulator-min-microvolt = <850000>; |
||||
regulator-max-microvolt = <1100000>; |
||||
regulator-always-on; |
||||
regulator-boot-on; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
buck2_reg: buck2 { |
||||
regulator-compatible = "BUCK2"; |
||||
regulator-name = "vdd_arm"; |
||||
regulator-min-microvolt = <850000>; |
||||
regulator-max-microvolt = <1500000>; |
||||
regulator-always-on; |
||||
regulator-boot-on; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
buck3_reg: buck3 { |
||||
regulator-compatible = "BUCK3"; |
||||
regulator-name = "vdd_int"; |
||||
regulator-min-microvolt = <850000>; |
||||
regulator-max-microvolt = <1150000>; |
||||
regulator-always-on; |
||||
regulator-boot-on; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
buck4_reg: buck4 { |
||||
regulator-compatible = "BUCK4"; |
||||
regulator-name = "vdd_g3d"; |
||||
regulator-min-microvolt = <850000>; |
||||
regulator-max-microvolt = <1150000>; |
||||
regulator-boot-on; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
buck5_reg: buck5 { |
||||
regulator-compatible = "BUCK5"; |
||||
regulator-name = "VMEM_1.2V_AP"; |
||||
regulator-min-microvolt = <1200000>; |
||||
regulator-max-microvolt = <1200000>; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
buck6_reg: buck6 { |
||||
regulator-compatible = "BUCK6"; |
||||
regulator-name = "VCC_SUB_1.35V"; |
||||
regulator-min-microvolt = <1350000>; |
||||
regulator-max-microvolt = <1350000>; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
buck7_reg: buck7 { |
||||
regulator-compatible = "BUCK7"; |
||||
regulator-name = "VCC_SUB_2.0V"; |
||||
regulator-min-microvolt = <2000000>; |
||||
regulator-max-microvolt = <2000000>; |
||||
regulator-always-on; |
||||
}; |
||||
|
||||
buck8_reg: buck8 { |
||||
regulator-compatible = "BUCK8"; |
||||
regulator-name = "VMEM_VDDF_3.0V"; |
||||
regulator-min-microvolt = <2850000>; |
||||
regulator-max-microvolt = <2850000>; |
||||
regulator-always-on; |
||||
regulator-mem-off; |
||||
}; |
||||
|
||||
buck9_reg: buck9 { |
||||
regulator-compatible = "BUCK9"; |
||||
regulator-name = "CAM_ISP_CORE_1.2V"; |
||||
regulator-min-microvolt = <1000000>; |
||||
regulator-max-microvolt = <1200000>; |
||||
regulator-mem-off; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
fimd@11c00000 { |
||||
compatible = "samsung,exynos-fimd"; |
||||
reg = <0x11c00000 0xa4>; |
||||
|
||||
samsung,vl-freq = <60>; |
||||
samsung,vl-col = <720>; |
||||
samsung,vl-row = <1280>; |
||||
samsung,vl-width = <720>; |
||||
samsung,vl-height = <1280>; |
||||
|
||||
samsung,vl-clkp = <0>; |
||||
samsung,vl-oep = <0>; |
||||
samsung,vl-hsp = <1>; |
||||
samsung,vl-vsp = <1>; |
||||
samsung,vl-dp = <1>; |
||||
samsung,vl-bpix = <4>; |
||||
|
||||
samsung,vl-hspw = <5>; |
||||
samsung,vl-hbpd = <10>; |
||||
samsung,vl-hfpd = <10>; |
||||
samsung,vl-vspw = <2>; |
||||
samsung,vl-vbpd = <1>; |
||||
samsung,vl-vfpd = <13>; |
||||
samsung,vl-cmd-allow-len = <0xf>; |
||||
|
||||
samsung,winid = <0>; |
||||
samsung,power-on-delay = <30>; |
||||
samsung,interface-mode = <1>; |
||||
samsung,mipi-enabled = <1>; |
||||
samsung,dp-enabled; |
||||
samsung,dual-lcd-enabled; |
||||
|
||||
samsung,logo-on = <1>; |
||||
samsung,resolution = <0>; |
||||
samsung,rgb-mode = <0>; |
||||
}; |
||||
|
||||
mipidsi@11c80000 { |
||||
compatible = "samsung,exynos-mipi-dsi"; |
||||
reg = <0x11c80000 0x5c>; |
||||
|
||||
samsung,dsim-config-e-interface = <1>; |
||||
samsung,dsim-config-e-virtual-ch = <0>; |
||||
samsung,dsim-config-e-pixel-format = <7>; |
||||
samsung,dsim-config-e-burst-mode = <1>; |
||||
samsung,dsim-config-e-no-data-lane = <3>; |
||||
samsung,dsim-config-e-byte-clk = <0>; |
||||
samsung,dsim-config-hfp = <1>; |
||||
|
||||
samsung,dsim-config-p = <3>; |
||||
samsung,dsim-config-m = <120>; |
||||
samsung,dsim-config-s = <1>; |
||||
|
||||
samsung,dsim-config-pll-stable-time = <500>; |
||||
samsung,dsim-config-esc-clk = <20000000>; |
||||
samsung,dsim-config-stop-holding-cnt = <0x7ff>; |
||||
samsung,dsim-config-bta-timeout = <0xff>; |
||||
samsung,dsim-config-rx-timeout = <0xffff>; |
||||
|
||||
samsung,dsim-device-id = <0xffffffff>; |
||||
samsung,dsim-device-bus-id = <0>; |
||||
|
||||
samsung,dsim-device-reverse-panel = <1>; |
||||
}; |
||||
|
||||
sdhci@12510000 { |
||||
samsung,bus-width = <8>; |
||||
samsung,timing = <1 3 3>; |
||||
pwr-gpios = <&gpio 0x2004002 0>; |
||||
}; |
||||
|
||||
sdhci@12520000 { |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
sdhci@12530000 { |
||||
samsung,bus-width = <4>; |
||||
samsung,timing = <1 2 3>; |
||||
cd-gpios = <&gpio 0x20C6004 0>; |
||||
}; |
||||
|
||||
sdhci@12540000 { |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
@ -1,48 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> |
||||
* Rohit Choraria <rohitkc@ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __ASM_ARCH_OMAP_GPMC_H |
||||
#define __ASM_ARCH_OMAP_GPMC_H |
||||
|
||||
/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */ |
||||
#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\ |
||||
.eccbytes = 32,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
|
||||
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
|
||||
28, 29, 30, 31, 32, 33},\
|
||||
.oobfree = {\
|
||||
{.offset = 34,\
|
||||
.length = 30 } } \
|
||||
} |
||||
|
||||
#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ |
||||
.eccbytes = 56,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
|
||||
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
|
||||
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
|
||||
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
|
||||
52, 53, 54, 55, 56, 57},\
|
||||
.oobfree = {\
|
||||
{.offset = 58,\
|
||||
.length = 6 } } \
|
||||
} |
||||
|
||||
#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\ |
||||
.eccbytes = 104,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
|
||||
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
|
||||
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
|
||||
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
|
||||
52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
|
||||
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
|
||||
76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
|
||||
88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
|
||||
100, 101, 102, 103, 104, 105},\
|
||||
.oobfree = {\
|
||||
{.offset = 106,\
|
||||
.length = 8 } } \
|
||||
} |
||||
#endif /* __ASM_ARCH_OMAP_GPMC_H */ |
||||
@ -1,36 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> |
||||
* Rohit Choraria <rohitkc@ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __ASM_ARCH_OMAP_GPMC_H |
||||
#define __ASM_ARCH_OMAP_GPMC_H |
||||
|
||||
/*
|
||||
* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library. |
||||
* The OOB layout was first defined by linx kernel in commit |
||||
* 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause |
||||
* we want to be compatible. |
||||
*/ |
||||
#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ |
||||
.eccbytes = 56,\
|
||||
.eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\
|
||||
23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\
|
||||
37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\
|
||||
51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\
|
||||
.oobfree = {\
|
||||
{.offset = 2,\
|
||||
.length = 10 } } \
|
||||
} |
||||
|
||||
/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ |
||||
#define NET_LAN9221_GPMC_CONFIG1 0x00001000 |
||||
#define NET_LAN9221_GPMC_CONFIG2 0x00060700 |
||||
#define NET_LAN9221_GPMC_CONFIG3 0x00020201 |
||||
#define NET_LAN9221_GPMC_CONFIG4 0x06000700 |
||||
#define NET_LAN9221_GPMC_CONFIG5 0x0006090A |
||||
#define NET_LAN9221_GPMC_CONFIG6 0x87030000 |
||||
#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c |
||||
|
||||
#endif /* __ASM_ARCH_OMAP_GPMC_H */ |
||||
@ -1,87 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> |
||||
* Rohit Choraria <rohitkc@ti.com> |
||||
* |
||||
* (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __ASM_OMAP_GPMC_H |
||||
#define __ASM_OMAP_GPMC_H |
||||
|
||||
#include <asm/arch/omap_gpmc.h> |
||||
|
||||
#define GPMC_BUF_EMPTY 0 |
||||
#define GPMC_BUF_FULL 1 |
||||
|
||||
#define ECCCLEAR (0x1 << 8) |
||||
#define ECCRESULTREG1 (0x1 << 0) |
||||
#define ECCSIZE512BYTE 0xFF |
||||
#define ECCSIZE1 (ECCSIZE512BYTE << 22) |
||||
#define ECCSIZE0 (ECCSIZE512BYTE << 12) |
||||
#define ECCSIZE0SEL (0x000 << 0) |
||||
|
||||
/* Generic ECC Layouts */ |
||||
/* Large Page x8 NAND device Layout */ |
||||
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT |
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\ |
||||
.eccbytes = 12,\
|
||||
.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
|
||||
9, 10, 11, 12},\
|
||||
.oobfree = {\
|
||||
{.offset = 13,\
|
||||
.length = 51 } } \
|
||||
} |
||||
#endif |
||||
|
||||
/* Large Page x16 NAND device Layout */ |
||||
#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT |
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\ |
||||
.eccbytes = 12,\
|
||||
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13},\
|
||||
.oobfree = {\
|
||||
{.offset = 14,\
|
||||
.length = 50 } } \
|
||||
} |
||||
#endif |
||||
|
||||
/* Small Page x8 NAND device Layout */ |
||||
#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT |
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\ |
||||
.eccbytes = 3,\
|
||||
.eccpos = {1, 2, 3},\
|
||||
.oobfree = {\
|
||||
{.offset = 4,\
|
||||
.length = 12 } } \
|
||||
} |
||||
#endif |
||||
|
||||
/* Small Page x16 NAND device Layout */ |
||||
#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT |
||||
#define GPMC_NAND_HW_ECC_LAYOUT {\ |
||||
.eccbytes = 3,\
|
||||
.eccpos = {2, 3, 4},\
|
||||
.oobfree = {\
|
||||
{.offset = 5,\
|
||||
.length = 11 } } \
|
||||
} |
||||
#endif |
||||
|
||||
enum omap_ecc { |
||||
/* 1-bit ECC calculation by Software, Error detection by Software */ |
||||
OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ |
||||
/* 1-bit ECC calculation by GPMC, Error detection by Software */ |
||||
/* ECC layout compatible to legacy ROMCODE. */ |
||||
OMAP_ECC_HAM1_CODE_HW, |
||||
/* 4-bit ECC calculation by GPMC, Error detection by Software */ |
||||
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, |
||||
/* 4-bit ECC calculation by GPMC, Error detection by ELM */ |
||||
OMAP_ECC_BCH4_CODE_HW, |
||||
/* 8-bit ECC calculation by GPMC, Error detection by Software */ |
||||
OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, |
||||
/* 8-bit ECC calculation by GPMC, Error detection by ELM */ |
||||
OMAP_ECC_BCH8_CODE_HW, |
||||
}; |
||||
|
||||
#endif /* __ASM_OMAP_GPMC_H */ |
||||
@ -1,39 +0,0 @@ |
||||
/*
|
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
/* Size defintions
|
||||
* Copyright (C) ARM Limited 1998. All rights reserved. |
||||
*/ |
||||
|
||||
#ifndef __sizes_h |
||||
#define __sizes_h 1 |
||||
|
||||
/* handy sizes */ |
||||
#define SZ_1K 0x00000400 |
||||
#define SZ_4K 0x00001000 |
||||
#define SZ_8K 0x00002000 |
||||
#define SZ_16K 0x00004000 |
||||
#define SZ_32K 0x00008000 |
||||
#define SZ_64K 0x00010000 |
||||
#define SZ_128K 0x00020000 |
||||
#define SZ_256K 0x00040000 |
||||
#define SZ_512K 0x00080000 |
||||
|
||||
#define SZ_1M 0x00100000 |
||||
#define SZ_2M 0x00200000 |
||||
#define SZ_4M 0x00400000 |
||||
#define SZ_8M 0x00800000 |
||||
#define SZ_16M 0x01000000 |
||||
#define SZ_31M 0x01F00000 |
||||
#define SZ_32M 0x02000000 |
||||
#define SZ_64M 0x04000000 |
||||
#define SZ_128M 0x08000000 |
||||
#define SZ_256M 0x10000000 |
||||
#define SZ_512M 0x20000000 |
||||
|
||||
#define SZ_1G 0x40000000 |
||||
#define SZ_2G 0x80000000 |
||||
|
||||
#endif |
||||
|
||||
/* END */ |
||||
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