Stout is an entry level development board based on R-Car H2 SoC (R8A7790) This commit supports the following peripherals: - SCIFA, I2C, Ethernet, QSPI, SDHI0/2, CPLD Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
Vladimir Barinov
10 years ago
committed by
Nobuhiro Iwamatsu
parent
b8f91e2c92
commit
21871138b7
@ -0,0 +1,12 @@ |
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if TARGET_STOUT |
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config SYS_BOARD |
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default "stout" |
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config SYS_VENDOR |
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default "renesas" |
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config SYS_CONFIG_NAME |
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default "stout" |
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endif |
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@ -0,0 +1,6 @@ |
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STOUT BOARD |
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M: Cogent Embedded, Inc. <source@cogentembedded.com> |
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S: Maintained |
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F: board/renesas/stout/ |
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F: include/configs/stout.h |
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F: configs/stout_defconfig |
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@ -0,0 +1,11 @@ |
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#
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# board/renesas/stout/Makefile
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#
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# Copyright (C) 2015 Renesas Electronics Europe GmbH
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# Copyright (C) 2015 Renesas Electronics Corporation
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# Copyright (C) 2015 Cogent Embedded, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-y := stout.o cpld.o qos.o ../rcar-gen2-common/common.o
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@ -0,0 +1,167 @@ |
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/*
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* Stout board CPLD access support |
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* |
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* Copyright (C) 2015 Renesas Electronics Europe GmbH |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* Copyright (C) 2015 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#include "cpld.h" |
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#define SCLK GPIO_GP_3_24 |
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#define SSTBZ GPIO_GP_3_25 |
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#define MOSI GPIO_GP_3_26 |
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#define MISO GPIO_GP_3_27 |
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#define CPLD_ADDR_MODE 0x00 /* RW */ |
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#define CPLD_ADDR_MUX 0x01 /* RW */ |
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#define CPLD_ADDR_HDMI 0x02 /* RW */ |
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#define CPLD_ADDR_DIPSW 0x08 /* R */ |
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#define CPLD_ADDR_RESET 0x80 /* RW */ |
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#define CPLD_ADDR_VERSION 0xFF /* R */ |
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static u32 cpld_read(u8 addr) |
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{ |
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int i; |
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u32 data = 0; |
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for (i = 0; i < 8; i++) { |
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gpio_set_value(MOSI, addr & 0x80); /* MSB first */ |
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gpio_set_value(SCLK, 1); |
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addr <<= 1; |
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gpio_set_value(SCLK, 0); |
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} |
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gpio_set_value(MOSI, 0); /* READ */ |
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gpio_set_value(SSTBZ, 0); |
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gpio_set_value(SCLK, 1); |
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gpio_set_value(SCLK, 0); |
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gpio_set_value(SSTBZ, 1); |
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for (i = 0; i < 32; i++) { |
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gpio_set_value(SCLK, 1); |
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data <<= 1; |
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data |= gpio_get_value(MISO); /* MSB first */ |
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gpio_set_value(SCLK, 0); |
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} |
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return data; |
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} |
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static void cpld_write(u8 addr, u32 data) |
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{ |
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int i; |
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for (i = 0; i < 32; i++) { |
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gpio_set_value(MOSI, data & (1 << 31)); /* MSB first */ |
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gpio_set_value(SCLK, 1); |
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data <<= 1; |
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gpio_set_value(SCLK, 0); |
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} |
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for (i = 0; i < 8; i++) { |
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gpio_set_value(MOSI, addr & 0x80); /* MSB first */ |
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gpio_set_value(SCLK, 1); |
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addr <<= 1; |
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gpio_set_value(SCLK, 0); |
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} |
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gpio_set_value(MOSI, 1); /* WRITE */ |
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gpio_set_value(SSTBZ, 0); |
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gpio_set_value(SCLK, 1); |
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gpio_set_value(SCLK, 0); |
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gpio_set_value(SSTBZ, 1); |
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} |
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/* LSI pin pull-up control */ |
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#define PUPR3 0xe606010C |
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#define PUPR3_SD3_DAT1 (1 << 27) |
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void cpld_init(void) |
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{ |
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u32 val; |
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/* PULL-UP on MISO line */ |
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val = readl(PUPR3); |
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val |= PUPR3_SD3_DAT1; |
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writel(val, PUPR3); |
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gpio_request(SCLK, NULL); |
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gpio_request(SSTBZ, NULL); |
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gpio_request(MOSI, NULL); |
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gpio_request(MISO, NULL); |
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gpio_direction_output(SCLK, 0); |
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gpio_direction_output(SSTBZ, 1); |
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gpio_direction_output(MOSI, 0); |
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gpio_direction_input(MISO); |
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/* dummy read */ |
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cpld_read(CPLD_ADDR_VERSION); |
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printf("CPLD version: 0x%08x\n", |
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cpld_read(CPLD_ADDR_VERSION)); |
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printf("H2 Mode setting (MD0..28): 0x%08x\n", |
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cpld_read(CPLD_ADDR_MODE)); |
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printf("Multiplexer settings: 0x%08x\n", |
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cpld_read(CPLD_ADDR_MUX)); |
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printf("HDMI setting: 0x%08x\n", |
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cpld_read(CPLD_ADDR_HDMI)); |
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printf("DIPSW (SW3): 0x%08x\n", |
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cpld_read(CPLD_ADDR_DIPSW)); |
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#ifdef CONFIG_SH_SDHI |
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/* switch MUX to SD0 */ |
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val = cpld_read(CPLD_ADDR_MUX); |
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val &= ~MUX_MSK_SD0; |
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val |= MUX_VAL_SD0; |
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cpld_write(CPLD_ADDR_MUX, val); |
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#endif |
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} |
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static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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u32 addr, val; |
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if (argc < 3) |
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return CMD_RET_USAGE; |
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addr = simple_strtoul(argv[2], NULL, 16); |
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if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE || |
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addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_HDMI || |
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addr == CPLD_ADDR_DIPSW || addr == CPLD_ADDR_RESET)) { |
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printf("cpld invalid addr\n"); |
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return CMD_RET_USAGE; |
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} |
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if (argc == 3 && strcmp(argv[1], "read") == 0) { |
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printf("0x%x\n", cpld_read(addr)); |
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} else if (argc == 4 && strcmp(argv[1], "write") == 0) { |
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val = simple_strtoul(argv[3], NULL, 16); |
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if (addr == CPLD_ADDR_MUX) { |
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/* never mask SCIFA0 console */ |
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val &= ~MUX_MSK_SCIFA0_USB; |
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val |= MUX_VAL_SCIFA0_USB; |
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} |
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cpld_write(addr, val); |
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} |
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return 0; |
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} |
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U_BOOT_CMD( |
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cpld, 4, 1, do_cpld, |
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"CPLD access", |
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"read addr\n" |
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"cpld write addr val\n" |
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); |
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void reset_cpu(ulong addr) |
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{ |
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cpld_write(CPLD_ADDR_RESET, 1); |
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} |
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@ -0,0 +1,183 @@ |
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/*
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* Stout board CPLD definition |
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* |
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* Copyright (C) 2015 Renesas Electronics Europe GmbH |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* Copyright (C) 2015 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef _CPLD_H_ |
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#define _CPLD_H_ |
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/* power-up behaviour */ |
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#define MODE_MSK_FREE_RUN 0x00000001 |
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#define MODE_VAL_FREE_RUN 0x00000000 |
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#define MODE_MSK_STEP_UP 0x00000001 |
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#define MODE_VAL_STEP_UP 0x00000000 |
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/* boot source */ |
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#define MODE_MSK_BOOT_SQPI_16KB_FAST 0x0000000E |
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#define MODE_VAL_BOOT_SQPI_16KB_FAST 0x00000004 |
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#define MODE_MSK_BOOT_SQPI_16KB_SLOW 0x0000000E |
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#define MODE_VAL_BOOT_SQPI_16KB_SLOW 0x00000008 |
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#define MODE_MSK_BOOT_SQPI_4KB_SLOW 0x0000000E |
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#define MODE_VAL_BOOT_SQPI_4KB_SLOW 0x0000000C |
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/* booting CPU */ |
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#define MODE_MSK_BOOT_CA15 0x000000C0 |
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#define MODE_VAL_BOOT_CA15 0x00000000 |
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#define MODE_MSK_BOOT_CA7 0x000000C0 |
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#define MODE_VAL_BOOT_CA7 0x00000040 |
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#define MODE_MSK_BOOT_SH4 0x000000C0 |
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#define MODE_VAL_BOOT_SH4 0x000000C0 |
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/* JTAG connection */ |
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#define MODE_MSK_JTAG_CORESIGHT 0xC0301C00 |
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#define MODE_VAL_JTAG_CORESIGHT 0x00200000 |
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#define MODE_MSK_JTAG_SH4 0xC0301C00 |
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#define MODE_VAL_JTAG_SH4 0x00300000 |
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/* DDR3 (PLL) speed */ |
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#define MODE_MSK_DDR3_1600 0x00080000 |
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#define MODE_VAL_DDR3_1600 0x00000000 |
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#define MODE_MSK_DDR3_1333 0x00080000 |
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#define MODE_VAL_DDR3_1333 0x00080000 |
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/* ComboPhy0 mode */ |
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#define MODE_MSK_PHY0_SATA0 0x01000000 |
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#define MODE_VAL_PHY0_SATA0 0x00000000 |
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#define MODE_MSK_PHY0_PCIE 0x01000000 |
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#define MODE_VAL_PHY0_PCIE 0x01000000 |
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/* ComboPhy1 mode */ |
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#define MODE_MSK_PHY1_SATA1 0x00800000 |
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#define MODE_VAL_PHY1_SATA1 0x00000000 |
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#define MODE_MSK_PHY1_USB3 0x00800000 |
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#define MODE_VAL_PHY1_USB3 0x00800000 |
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/*
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* Illegal multiplexer combinations. |
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* MUX Conflicts |
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* name with any one of |
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* VIN0_BT656 VIN0_full, SD2 |
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* VIN0_full VIN0_BT656, SD2, AVB, VIN2_(all) |
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* VIN1_BT656 VIN1_(others), SD0 |
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* VIN1_10bit VIN1_(others), SD0, VIN3_with*, I2C1 |
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* VIN1_12bit VIN1_(others), SD0, VIN3_with*, I2C1, SCIFA0_(all) |
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* VIN2_BT656 VIN0_full, VIN2_(others), AVB, |
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* VIN2_withSYNC VIN0_full, VIN2_(others), AVB, I2C1, SCIFA0_(all), |
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* VIN3_with* |
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* VIN2_withFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all) |
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* VIN2_withSYNCandFIELD VIN0_full, VIN2_(others), AVB, SQPI_(all), I2C1, |
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* SCIFA0_(all), VIN3_with* |
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* VIN3_BT656 VIN3_(others), IRQ3 |
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* VIN3_withFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC, |
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* VIN2_withSYNCandFIELD, VIN1_10bit |
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* VIN3_withSYNCandFIELD VIN3_(others), IRQ3, VIN1_12bit, VIN2_withSYNC, |
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* VIN2_withSYNCandFIELD, VIN1_10bit, I2C1 |
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* AVB VIN0_full, VIN2_(all) |
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* QSPI_ONBOARD VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_COMEXPRESS |
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* QSPI_COMEXPRESS VIN2_withFIELD, VIN2_withSYNCandFIELD, QSPI_ONBOARD |
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* I2C1 VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, |
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* VIN3_withSYNCandFIELD |
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* IRQ3 VIN3_(all) |
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* SCIFA0_USB VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, |
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* SCIFA0_COMEXPRESS |
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* SCIFA0_COMEXPRESS VIN1_12bit, VIN2_withSYNC, VIN2_withSYNCandFIELD, |
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* SCIFA0_USB |
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* SCIFA2 PWM210 |
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* ETH_ONBOARD ETH_COMEXPRESS |
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* ETH_COMEXPRESS ETH_ONBOARD |
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* SD0 VIN1_(all) |
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* SD2 VIN0_(all) |
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* PWM210 SCIFA2 |
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*/ |
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/* connected to COM Express connector and CN6 for camera, BT656 only */ |
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#define MUX_MSK_VIN0_BT656 0x00001001 |
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#define MUX_VAL_VIN0_BT656 0x00000000 |
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/* connected to COM Express connector and CN6 for camera, all modes */ |
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#define MUX_MSK_VIN0_full 0x00001007 |
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#define MUX_VAL_VIN0_full 0x00000002 |
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/* connected to COM Express connector, BT656 only */ |
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#define MUX_MSK_VIN1_BT656 0x00000801 |
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#define MUX_VAL_VIN1_BT656 0x00000800 |
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/* connected to COM Express connector, all 10-bit modes */ |
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#define MUX_MSK_VIN1_10bit 0x00000821 |
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#define MUX_VAL_VIN1_10bit 0x00000800 |
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/* connected to COM Express connector, all 12-bit modes */ |
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#define MUX_MSK_VIN1_12bit 0x000008A1 |
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#define MUX_VAL_VIN1_12bit 0x00000880 |
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/* connected to COM Express connector, BT656 only */ |
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#define MUX_MSK_VIN2_BT656 0x00000007 |
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#define MUX_VAL_VIN2_BT656 0x00000006 |
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/* connected to COM Express connector, modes with sync signals */ |
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#define MUX_MSK_VIN2_withSYNC 0x000000A7 |
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#define MUX_VAL_VIN2_withSYNC 0x00000086 |
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/* connected to COM Express connector, modes with field, clken signals */ |
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#define MUX_MSK_VIN2_withFIELD 0x0000000F |
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#define MUX_VAL_VIN2_withFIELD 0x0000000E |
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/* connected to COM Express connector, modes with sync, field, clken signals */ |
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#define MUX_MSK_VIN2_withSYNCandFIELD 0x000000AF |
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#define MUX_VAL_VIN2_withSYNCandFIELD 0x0000008E |
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/* connected to COM Express connector, BT656 only */ |
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#define MUX_MSK_VIN3_BT656 0x00000101 |
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#define MUX_VAL_VIN3_BT656 0x00000100 |
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/* connected to COM Express connector, modes with field, clken signals */ |
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#define MUX_MSK_VIN3_withFIELD 0x00000121 |
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#define MUX_VAL_VIN3_withFIELD 0x00000120 |
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/* connected to COM Express connector, modes with sync, field, clken signals */ |
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#define MUX_MSK_VIN3_withSYNCandFIELD 0x00000161 |
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#define MUX_VAL_VIN3_withSYNCandFIELD 0x00000120 |
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/* connected to COM Express connector (RGMII) */ |
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#define MUX_MSK_AVB 0x00000003 |
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#define MUX_VAL_AVB 0x00000000 |
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/* connected to on-board QSPI flash */ |
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#define MUX_MSK_QSPI_ONBOARD 0x00000019 |
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#define MUX_VAL_QSPI_ONBOARD 0x00000000 |
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/* connected to COM Express connector */ |
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#define MUX_MSK_QSPI_COMEXPRESS 0x00000019 |
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#define MUX_VAL_QSPI_COMEXPRESS 0x00000010 |
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/* connected to COM Express connector and PMIC */ |
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#define MUX_MSK_I2C1 0x00000061 |
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#define MUX_VAL_I2C1 0x00000060 |
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/* connected to HDMI driver */ |
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#define MUX_MSK_IRQ3 0x00000101 |
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#define MUX_VAL_IRQ3 0x00000000 |
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/* connected to USB/FTDI */ |
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#define MUX_MSK_SCIFA0_USB 0x00004081 |
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#define MUX_VAL_SCIFA0_USB 0x00004000 |
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/* connected to COM Express connector */ |
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#define MUX_MSK_SCIFA0_COMEXPRESS 0x00004081 |
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#define MUX_VAL_SCIFA0_COMEXPRESS 0x00000000 |
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/* connected to COM Express connector */ |
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#define MUX_MSK_SCIFA2 0x00002001 |
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#define MUX_VAL_SCIFA2 0x00000000 |
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/* connected to on-board 10/100 Phy */ |
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#define MUX_MSK_ETH_ONBOARD 0x00000600 |
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#define MUX_VAL_ETH_ONBOARD 0x00000000 |
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/* connected to COM Express connector (RMII) */ |
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#define MUX_MSK_ETH_COMEXPRESS 0x00000600 |
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#define MUX_VAL_ETH_COMEXPRESS 0x00000400 |
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/* connected to on-board MicroSD slot */ |
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#define MUX_MSK_SD0 0x00000801 |
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#define MUX_VAL_SD0 0x00000000 |
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/* connected to COM Express connector */ |
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#define MUX_MSK_SD2 0x00001001 |
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#define MUX_VAL_SD2 0x00001000 |
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/* connected to COM Express connector */ |
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#define MUX_MSK_PWM210 0x00002001 |
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#define MUX_VAL_PWM210 0x00002000 |
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#define HDMI_MSK 0x07 |
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#define HDMI_OFF 0x00 |
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#define HDMI_ONBOARD 0x07 |
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#define HDMI_COMEXPRESS 0x05 |
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#define HDMI_ONBOARD_NODDC 0x03 |
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#define HDMI_COMEXPRESS_NODDC 0x01 |
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void cpld_init(void); |
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#endif /* _CPLD_H_ */ |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,14 @@ |
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/*
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* Copyright (C) 2015 Renesas Electronics Europe GmbH |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* Copyright (C) 2015 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#ifndef __QOS_H__ |
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#define __QOS_H__ |
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void qos_init(void); |
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#endif |
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@ -0,0 +1,232 @@ |
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/*
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* board/renesas/stout/stout.c |
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* This file is Stout board support. |
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* |
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* Copyright (C) 2015 Renesas Electronics Europe GmbH |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* Copyright (C) 2015 Cogent Embedded, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <netdev.h> |
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#include <dm.h> |
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#include <dm/platform_data/serial_sh.h> |
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#include <asm/processor.h> |
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#include <asm/mach-types.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/rmobile.h> |
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#include <asm/arch/rcar-mstp.h> |
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#include <asm/arch/mmc.h> |
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#include <asm/arch/sh_sdhi.h> |
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#include <miiphy.h> |
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#include <i2c.h> |
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#include <mmc.h> |
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#include "qos.h" |
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#include "cpld.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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#define CLK2MHZ(clk) (clk / 1000 / 1000) |
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void s_init(void) |
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{ |
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
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/* Watchdog init */ |
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writel(0xA5A5A500, &rwdt->rwtcsra); |
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writel(0xA5A5A500, &swdt->swtcsra); |
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/* CPU frequency setting. Set to 1.4GHz */ |
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if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { |
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u32 stat = 0; |
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u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) |
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<< PLL0_STC_BIT; |
||||
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); |
||||
|
||||
do { |
||||
stat = readl(PLLECR) & PLL0ST; |
||||
} while (stat == 0x0); |
||||
} |
||||
|
||||
/* QoS(Quality-of-Service) Init */ |
||||
qos_init(); |
||||
} |
||||
|
||||
#define TMU0_MSTP125 (1 << 25) |
||||
#define SCIFA0_MSTP204 (1 << 4) |
||||
#define SDHI0_MSTP314 (1 << 14) |
||||
#define SDHI2_MSTP312 (1 << 12) |
||||
#define ETHER_MSTP813 (1 << 13) |
||||
|
||||
#define MSTPSR3 0xE6150048 |
||||
#define SMSTPCR3 0xE615013C |
||||
|
||||
#define SD2CKCR 0xE6150078 |
||||
#define SD2_97500KHZ 0x7 |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
/* TMU0 */ |
||||
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
||||
/* SCIFA0 */ |
||||
mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204); |
||||
/* ETHER */ |
||||
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); |
||||
/* SDHI0,2 */ |
||||
mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); |
||||
|
||||
/*
|
||||
* SD0 clock is set to 97.5MHz by default. |
||||
* Set SD2 to the 97.5MHz as well. |
||||
*/ |
||||
writel(SD2_97500KHZ, SD2CKCR); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
||||
|
||||
/* Init PFC controller */ |
||||
r8a7790_pinmux_init(); |
||||
|
||||
cpld_init(); |
||||
|
||||
#ifdef CONFIG_SH_ETHER |
||||
/* ETHER Enable */ |
||||
gpio_request(GPIO_FN_ETH_CRS_DV, NULL); |
||||
gpio_request(GPIO_FN_ETH_RX_ER, NULL); |
||||
gpio_request(GPIO_FN_ETH_RXD0, NULL); |
||||
gpio_request(GPIO_FN_ETH_RXD1, NULL); |
||||
gpio_request(GPIO_FN_ETH_LINK, NULL); |
||||
gpio_request(GPIO_FN_ETH_REF_CLK, NULL); |
||||
gpio_request(GPIO_FN_ETH_MDIO, NULL); |
||||
gpio_request(GPIO_FN_ETH_TXD1, NULL); |
||||
gpio_request(GPIO_FN_ETH_TX_EN, NULL); |
||||
gpio_request(GPIO_FN_ETH_MAGIC, NULL); |
||||
gpio_request(GPIO_FN_ETH_TXD0, NULL); |
||||
gpio_request(GPIO_FN_ETH_MDC, NULL); |
||||
gpio_request(GPIO_FN_IRQ1, NULL); |
||||
|
||||
gpio_request(GPIO_GP_3_31, NULL); /* PHY_RST */ |
||||
gpio_direction_output(GPIO_GP_3_31, 0); |
||||
mdelay(20); |
||||
gpio_set_value(GPIO_GP_3_31, 1); |
||||
udelay(1); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#define CXR24 0xEE7003C0 /* MAC address high register */ |
||||
#define CXR25 0xEE7003C8 /* MAC address low register */ |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int ret = -ENODEV; |
||||
|
||||
#ifdef CONFIG_SH_ETHER |
||||
u32 val; |
||||
unsigned char enetaddr[6]; |
||||
|
||||
ret = sh_eth_initialize(bis); |
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
||||
return ret; |
||||
|
||||
/* Set Mac address */ |
||||
val = enetaddr[0] << 24 | enetaddr[1] << 16 | |
||||
enetaddr[2] << 8 | enetaddr[3]; |
||||
writel(val, CXR24); |
||||
|
||||
val = enetaddr[4] << 8 | enetaddr[5]; |
||||
writel(val, CXR25); |
||||
#endif |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
/* Stout has KSZ8041NL/RNL */ |
||||
#define PHY_CONTROL1 0x1E |
||||
#define PHY_LED_MODE 0xC0000 |
||||
#define PHY_LED_MODE_ACK 0x4000 |
||||
int board_phy_config(struct phy_device *phydev) |
||||
{ |
||||
int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); |
||||
ret &= ~PHY_LED_MODE; |
||||
ret |= PHY_LED_MODE_ACK; |
||||
ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_mmc_init(bd_t *bis) |
||||
{ |
||||
int ret = -ENODEV; |
||||
|
||||
#ifdef CONFIG_SH_SDHI |
||||
gpio_request(GPIO_FN_SD0_DAT0, NULL); |
||||
gpio_request(GPIO_FN_SD0_DAT1, NULL); |
||||
gpio_request(GPIO_FN_SD0_DAT2, NULL); |
||||
gpio_request(GPIO_FN_SD0_DAT3, NULL); |
||||
gpio_request(GPIO_FN_SD0_CLK, NULL); |
||||
gpio_request(GPIO_FN_SD0_CMD, NULL); |
||||
gpio_request(GPIO_FN_SD0_CD, NULL); |
||||
gpio_request(GPIO_FN_SD2_DAT0, NULL); |
||||
gpio_request(GPIO_FN_SD2_DAT1, NULL); |
||||
gpio_request(GPIO_FN_SD2_DAT2, NULL); |
||||
gpio_request(GPIO_FN_SD2_DAT3, NULL); |
||||
gpio_request(GPIO_FN_SD2_CLK, NULL); |
||||
gpio_request(GPIO_FN_SD2_CMD, NULL); |
||||
gpio_request(GPIO_FN_SD2_CD, NULL); |
||||
|
||||
/* SDHI0 - needs CPLD mux setup */ |
||||
gpio_request(GPIO_GP_3_30, NULL); |
||||
gpio_direction_output(GPIO_GP_3_30, 1); /* VLDO3=3.3V */ |
||||
gpio_request(GPIO_GP_5_24, NULL); |
||||
gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ |
||||
|
||||
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, |
||||
SH_SDHI_QUIRK_16BIT_BUF); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* SDHI2 - needs CPLD mux setup */ |
||||
gpio_request(GPIO_GP_3_29, NULL); |
||||
gpio_direction_output(GPIO_GP_3_29, 1); /* VLDO4=3.3V */ |
||||
gpio_request(GPIO_GP_5_25, NULL); |
||||
gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ |
||||
|
||||
ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); |
||||
#endif |
||||
return ret; |
||||
} |
||||
|
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
const struct rmobile_sysinfo sysinfo = { |
||||
CONFIG_RMOBILE_BOARD_STRING |
||||
}; |
||||
|
||||
static const struct sh_serial_platdata serial_platdata = { |
||||
.base = SCIFA0_BASE, |
||||
.type = PORT_SCIFA, |
||||
.clk = CONFIG_MP_CLK_FREQ, |
||||
}; |
||||
|
||||
U_BOOT_DEVICE(stout_serials) = { |
||||
.name = "serial_sh", |
||||
.platdata = &serial_platdata, |
||||
}; |
||||
@ -0,0 +1,21 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_RMOBILE=y |
||||
CONFIG_TARGET_STOUT=y |
||||
# CONFIG_CMD_BDI is not set |
||||
# CONFIG_CMD_CONSOLE is not set |
||||
# CONFIG_CMD_BOOTD is not set |
||||
# CONFIG_CMD_IMI is not set |
||||
# CONFIG_CMD_IMLS is not set |
||||
# CONFIG_CMD_XIMG is not set |
||||
# CONFIG_CMD_ENV_EXISTS is not set |
||||
# CONFIG_CMD_LOADB is not set |
||||
# CONFIG_CMD_FLASH is not set |
||||
# CONFIG_CMD_FPGA is not set |
||||
# CONFIG_CMD_ECHO is not set |
||||
# CONFIG_CMD_ITEST is not set |
||||
# CONFIG_CMD_SOURCE is not set |
||||
# CONFIG_CMD_SETEXPR is not set |
||||
# CONFIG_CMD_MISC is not set |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_BAR=y |
||||
CONFIG_SH_SDHI=y |
||||
@ -0,0 +1,112 @@ |
||||
/*
|
||||
* include/configs/stout.h |
||||
* This file is Stout board configuration. |
||||
* |
||||
* Copyright (C) 2015 Renesas Electronics Europe GmbH |
||||
* Copyright (C) 2015 Renesas Electronics Corporation |
||||
* Copyright (C) 2015 Cogent Embedded, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#ifndef __STOUT_H |
||||
#define __STOUT_H |
||||
|
||||
#undef DEBUG |
||||
#define CONFIG_R8A7790 |
||||
#define CONFIG_RMOBILE_BOARD_STRING "Stout" |
||||
|
||||
#include "rcar-gen2-common.h" |
||||
|
||||
/* #define CONFIG_BOARD_LATE_INIT */ |
||||
|
||||
#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) |
||||
#define CONFIG_SYS_TEXT_BASE 0xB0000000 |
||||
#else |
||||
#define CONFIG_SYS_TEXT_BASE 0xE8080000 |
||||
#endif |
||||
|
||||
/* STACK */ |
||||
#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) |
||||
#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC |
||||
#else |
||||
#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC |
||||
#endif |
||||
#define STACK_AREA_SIZE 0xC000 |
||||
#define LOW_LEVEL_MERAM_STACK \ |
||||
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) |
||||
|
||||
/* MEMORY */ |
||||
#define RCAR_GEN2_SDRAM_BASE 0x40000000 |
||||
#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) |
||||
#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) |
||||
|
||||
/* SCIF */ |
||||
#define CONFIG_SCIF_CONSOLE |
||||
#define CONFIG_SCIF_A |
||||
|
||||
/* SPI */ |
||||
#define CONFIG_SPI |
||||
#define CONFIG_SH_QSPI |
||||
#define CONFIG_SPI_FLASH_SPANSION |
||||
#define CONFIG_SPI_FLASH_QUAD |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
/* SH Ether */ |
||||
#define CONFIG_SH_ETHER |
||||
#define CONFIG_SH_ETHER_USE_PORT 0 |
||||
#define CONFIG_SH_ETHER_PHY_ADDR 0x1 |
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII |
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 |
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK |
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE |
||||
#define CONFIG_PHYLIB |
||||
#define CONFIG_PHY_MICREL |
||||
#define CONFIG_BITBANGMII |
||||
#define CONFIG_BITBANGMII_MULTI |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C |
||||
#define CONFIG_SYS_I2C_RCAR |
||||
#define CONFIG_SYS_RCAR_I2C0_SPEED 400000 |
||||
#define CONFIG_SYS_RCAR_I2C1_SPEED 400000 |
||||
#define CONFIG_SYS_RCAR_I2C2_SPEED 400000 |
||||
#define CONFIG_SYS_RCAR_I2C3_SPEED 400000 |
||||
#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 |
||||
|
||||
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ |
||||
|
||||
/* Board Clock */ |
||||
#define RMOBILE_XTAL_CLK 20000000u |
||||
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK |
||||
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ |
||||
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) |
||||
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) |
||||
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) |
||||
#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) |
||||
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4 |
||||
|
||||
/* USB */ |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_RMOBILE |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
||||
#define CONFIG_USB_STORAGE |
||||
|
||||
/* MMC */ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
|
||||
/* Module stop status bits */ |
||||
/* INTC-RT */ |
||||
#define CONFIG_SMSTP0_ENA 0x00400000 |
||||
/* MSIF, SCIFA0 */ |
||||
#define CONFIG_SMSTP2_ENA 0x00002010 |
||||
/* INTC-SYS, IRQC */ |
||||
#define CONFIG_SMSTP4_ENA 0x00000180 |
||||
|
||||
/* SDHI */ |
||||
#define CONFIG_SH_SDHI_FREQ 97500000 |
||||
|
||||
#endif /* __STOUT_H */ |
||||
Loading…
Reference in new issue