Compared to the Armada 3700, the Armada 7K and 8K are much more on the high-end side: they use a dual Cortex-A72 or a quad Cortex-A72, as opposed to the Cortex-A53 for the Armada 3700. The Armada 7K and 8K also use a fairly unique architecture, internally they are composed of several components: - One AP (Application Processor), which contains the processor itself and a few core hardware blocks. The AP used in the Armada 7K and 8K is called AP806, and is available in two configurations: dual Cortex-A72 and quad Cortex-A72. - One or two CP (Communication Processor), which contain most of the I/O interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP, while the 8K family chips integrate two CPs, providing two times the number of I/O interfaces available in the CP. The CP used in the 7K and 8K is called CP110. All in all, this gives the following combinations: - Armada 7020, which is a dual Cortex-A72 with one CP - Armada 7040, which is a quad Cortex-A72 with one CP - Armada 8020, which is a dual Cortex-A72 with two CPs - Armada 8040, which is a quad Cortex-A72 with two CPs This patch adds basic support for this ARMv8 based SoC into U-Boot. Future patches will integrate other device drivers and board support, starting with the Marvell DB-88F7040 development board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>master
Stefan Roese
8 years ago
parent
1335483a69
commit
21b29fc64e
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <fdtdec.h> |
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#include <libfdt.h> |
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#include <asm/io.h> |
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#include <asm/system.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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#include <asm/armv8/mmu.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/*
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* On ARMv8, MBus is not configured in U-Boot. To enable compilation |
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* of the already implemented drivers, lets add a dummy version of |
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* this function so that linking does not fail. |
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*/ |
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const struct mbus_dram_target_info *mvebu_mbus_dram_info(void) |
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{ |
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return NULL; |
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} |
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/* DRAM init code ... */ |
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static const void *get_memory_reg_prop(const void *fdt, int *lenp) |
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{ |
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int offset; |
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offset = fdt_path_offset(fdt, "/memory"); |
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if (offset < 0) |
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return NULL; |
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return fdt_getprop(fdt, offset, "reg", lenp); |
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} |
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int dram_init(void) |
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{ |
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const void *fdt = gd->fdt_blob; |
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const fdt32_t *val; |
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int ac, sc, len; |
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ac = fdt_address_cells(fdt, 0); |
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sc = fdt_size_cells(fdt, 0); |
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if (ac < 0 || sc < 1 || sc > 2) { |
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printf("invalid address/size cells\n"); |
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return -EINVAL; |
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} |
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val = get_memory_reg_prop(fdt, &len); |
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if (len / sizeof(*val) < ac + sc) |
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return -EINVAL; |
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val += ac; |
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gd->ram_size = fdtdec_get_number(val, sc); |
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debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size); |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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const void *fdt = gd->fdt_blob; |
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const fdt32_t *val; |
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int ac, sc, cells, len, i; |
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val = get_memory_reg_prop(fdt, &len); |
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if (len < 0) |
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return; |
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ac = fdt_address_cells(fdt, 0); |
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sc = fdt_size_cells(fdt, 0); |
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if (ac < 1 || sc > 2 || sc < 1 || sc > 2) { |
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printf("invalid address/size cells\n"); |
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return; |
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} |
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cells = ac + sc; |
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len /= sizeof(*val); |
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for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells; |
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i++, len -= cells) { |
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gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac); |
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val += ac; |
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gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc); |
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val += sc; |
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debug("DRAM bank %d: start = %08lx, size = %08lx\n", |
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i, (unsigned long)gd->bd->bi_dram[i].start, |
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(unsigned long)gd->bd->bi_dram[i].size); |
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} |
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} |
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int arch_cpu_init(void) |
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{ |
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/* Nothing to do (yet) */ |
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return 0; |
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} |
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int arch_early_init_r(void) |
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{ |
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struct udevice *dev; |
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int ret; |
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/* Call the comphy code via the MISC uclass driver */ |
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ret = uclass_get_device(UCLASS_MISC, 0, &dev); |
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if (ret) { |
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debug("COMPHY init failed: %d\n", ret); |
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return -ENODEV; |
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} |
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/* Cause the SATA device to do its early init */ |
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uclass_first_device(UCLASS_AHCI, &dev); |
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return 0; |
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} |
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@ -0,0 +1,7 @@ |
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#
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# Copyright (C) 2016 Stefan Roese <sr@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = cpu.o
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@ -0,0 +1,64 @@ |
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <fdtdec.h> |
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#include <libfdt.h> |
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#include <asm/io.h> |
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#include <asm/system.h> |
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#include <asm/arch/cpu.h> |
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#include <asm/arch/soc.h> |
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#include <asm/armv8/mmu.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* Armada 7k/8k */ |
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#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000)) |
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#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84) |
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#define RFU_SW_RESET_OFFSET 0 |
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static struct mm_region mvebu_mem_map[] = { |
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{ |
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/* RAM */ |
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.phys = 0x0UL, |
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.virt = 0x0UL, |
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.size = 0x80000000UL, |
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
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PTE_BLOCK_INNER_SHARE |
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}, |
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{ |
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/* SRAM, MMIO regions - AP806 region */ |
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.phys = 0xf0000000UL, |
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.virt = 0xf0000000UL, |
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.size = 0x01000000UL, /* 16MiB internal registers */ |
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE |
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}, |
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{ |
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/* SRAM, MMIO regions - CP110 region */ |
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.phys = 0xf2000000UL, |
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.virt = 0xf2000000UL, |
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.size = 0x02000000UL, /* 32MiB internal registers */ |
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
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PTE_BLOCK_NON_SHARE |
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}, |
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{ |
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/* List terminator */ |
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0, |
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} |
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}; |
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struct mm_region *mem_map = mvebu_mem_map; |
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void reset_cpu(ulong ignored) |
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{ |
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u32 reg; |
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reg = readl(RFU_GLOBAL_SW_RST); |
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reg &= ~(1 << RFU_SW_RESET_OFFSET); |
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writel(reg, RFU_GLOBAL_SW_RST); |
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} |
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