Last user of this driver went away in May 2017 in commit
eb5ba3aefd
("i2c: Drop use of CONFIG_I2C_HARD").
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Heiko Schocher <hs@denx.de>
lime2-spi
parent
d70c79fa89
commit
2239690aca
@ -1,376 +0,0 @@ |
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
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* Copyright (C) 2012 Renesas Solutions Corp. |
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* |
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* NOTE: This driver should be converted to driver model before June 2017. |
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* Please see doc/driver-model/i2c-howto.txt for instructions. |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <asm/io.h> |
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struct sh_i2c { |
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u8 iccr1; |
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u8 iccr2; |
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u8 icmr; |
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u8 icier; |
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u8 icsr; |
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u8 sar; |
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u8 icdrt; |
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u8 icdrr; |
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u8 nf2cyc; |
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u8 __pad0; |
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u8 __pad1; |
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}; |
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static struct sh_i2c *base; |
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static u8 iccr1_cks, nf2cyc; |
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/* ICCR1 */ |
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#define SH_I2C_ICCR1_ICE (1 << 7) |
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#define SH_I2C_ICCR1_RCVD (1 << 6) |
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#define SH_I2C_ICCR1_MST (1 << 5) |
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#define SH_I2C_ICCR1_TRS (1 << 4) |
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#define SH_I2C_ICCR1_MTRS \ |
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(SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS) |
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/* ICCR1 */ |
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#define SH_I2C_ICCR2_BBSY (1 << 7) |
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#define SH_I2C_ICCR2_SCP (1 << 6) |
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#define SH_I2C_ICCR2_SDAO (1 << 5) |
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#define SH_I2C_ICCR2_SDAOP (1 << 4) |
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#define SH_I2C_ICCR2_SCLO (1 << 3) |
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#define SH_I2C_ICCR2_IICRST (1 << 1) |
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#define SH_I2C_ICIER_TIE (1 << 7) |
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#define SH_I2C_ICIER_TEIE (1 << 6) |
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#define SH_I2C_ICIER_RIE (1 << 5) |
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#define SH_I2C_ICIER_NAKIE (1 << 4) |
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#define SH_I2C_ICIER_STIE (1 << 3) |
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#define SH_I2C_ICIER_ACKE (1 << 2) |
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#define SH_I2C_ICIER_ACKBR (1 << 1) |
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#define SH_I2C_ICIER_ACKBT (1 << 0) |
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#define SH_I2C_ICSR_TDRE (1 << 7) |
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#define SH_I2C_ICSR_TEND (1 << 6) |
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#define SH_I2C_ICSR_RDRF (1 << 5) |
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#define SH_I2C_ICSR_NACKF (1 << 4) |
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#define SH_I2C_ICSR_STOP (1 << 3) |
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#define SH_I2C_ICSR_ALOVE (1 << 2) |
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#define SH_I2C_ICSR_AAS (1 << 1) |
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#define SH_I2C_ICSR_ADZ (1 << 0) |
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#define IRQ_WAIT 1000 |
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static void sh_i2c_send_stop(struct sh_i2c *base) |
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{ |
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clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP); |
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} |
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static int check_icsr_bits(struct sh_i2c *base, u8 bits) |
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{ |
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int i; |
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for (i = 0; i < IRQ_WAIT; i++) { |
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if (bits & readb(&base->icsr)) |
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return 0; |
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udelay(10); |
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} |
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return 1; |
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} |
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static int check_stop(struct sh_i2c *base) |
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{ |
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int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP); |
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clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); |
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return ret; |
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} |
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static int check_tend(struct sh_i2c *base, int stop) |
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{ |
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int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND); |
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if (stop) { |
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clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); |
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sh_i2c_send_stop(base); |
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} |
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clrbits_8(&base->icsr, SH_I2C_ICSR_TEND); |
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return ret; |
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} |
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static int check_tdre(struct sh_i2c *base) |
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{ |
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return check_icsr_bits(base, SH_I2C_ICSR_TDRE); |
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} |
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static int check_rdrf(struct sh_i2c *base) |
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{ |
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return check_icsr_bits(base, SH_I2C_ICSR_RDRF); |
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} |
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static int check_bbsy(struct sh_i2c *base) |
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{ |
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int i; |
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for (i = 0 ; i < IRQ_WAIT ; i++) { |
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if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2))) |
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return 0; |
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udelay(10); |
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} |
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return 1; |
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} |
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static int check_ackbr(struct sh_i2c *base) |
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{ |
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int i; |
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for (i = 0 ; i < IRQ_WAIT ; i++) { |
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if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier))) |
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return 0; |
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udelay(10); |
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} |
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return 1; |
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} |
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static void sh_i2c_reset(struct sh_i2c *base) |
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{ |
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setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST); |
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udelay(100); |
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clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST); |
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} |
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static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg) |
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{ |
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if (check_bbsy(base)) { |
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puts("i2c bus busy\n"); |
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goto fail; |
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} |
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setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); |
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clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); |
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writeb((id << 1), &base->icdrt); |
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if (check_tend(base, 0)) { |
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puts("TEND check fail...\n"); |
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goto fail; |
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} |
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if (check_ackbr(base)) { |
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check_tend(base, 0); |
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sh_i2c_send_stop(base); |
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goto fail; |
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} |
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writeb(reg, &base->icdrt); |
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if (check_tdre(base)) { |
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puts("TDRE check fail...\n"); |
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goto fail; |
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} |
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if (check_tend(base, 0)) { |
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puts("TEND check fail...\n"); |
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goto fail; |
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} |
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return 0; |
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fail: |
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return 1; |
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} |
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static int |
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i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size) |
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{ |
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int i; |
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if (i2c_set_addr(base, id, reg)) { |
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puts("Fail set slave address\n"); |
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return 1; |
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} |
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for (i = 0; i < size; i++) { |
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writeb(val[i], &base->icdrt); |
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check_tdre(base); |
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} |
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check_tend(base, 1); |
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check_stop(base); |
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udelay(100); |
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clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); |
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clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); |
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sh_i2c_reset(base); |
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return 0; |
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} |
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static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) |
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{ |
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u8 ret = 0; |
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if (i2c_set_addr(base, id, reg)) { |
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puts("Fail set slave address\n"); |
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goto fail; |
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} |
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clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); |
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writeb((id << 1) | 1, &base->icdrt); |
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if (check_tend(base, 0)) |
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puts("TDRE check fail...\n"); |
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clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST); |
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clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); |
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setbits_8(&base->icier, SH_I2C_ICIER_ACKBT); |
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setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD); |
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/* read data (dummy) */ |
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ret = readb(&base->icdrr); |
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if (check_rdrf(base)) { |
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puts("check RDRF error\n"); |
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goto fail; |
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} |
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clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); |
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udelay(1000); |
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sh_i2c_send_stop(base); |
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if (check_stop(base)) { |
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puts("check STOP error\n"); |
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goto fail; |
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} |
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clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); |
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clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); |
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/* data read */ |
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ret = readb(&base->icdrr); |
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fail: |
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clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD); |
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return ret; |
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} |
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#ifdef CONFIG_I2C_MULTI_BUS |
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static unsigned int current_bus; |
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/**
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* i2c_set_bus_num - change active I2C bus |
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* @bus: bus index, zero based |
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* @returns: 0 on success, non-0 on failure |
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*/ |
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int i2c_set_bus_num(unsigned int bus) |
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{ |
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switch (bus) { |
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case 0: |
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base = (void *)CONFIG_SH_I2C_BASE0; |
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break; |
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case 1: |
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base = (void *)CONFIG_SH_I2C_BASE1; |
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break; |
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default: |
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printf("Bad bus: %d\n", bus); |
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return -1; |
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} |
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current_bus = bus; |
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return 0; |
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} |
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/**
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* i2c_get_bus_num - returns index of active I2C bus |
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*/ |
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unsigned int i2c_get_bus_num(void) |
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{ |
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return current_bus; |
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} |
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#endif |
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void i2c_init(int speed, int slaveaddr) |
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{ |
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#ifdef CONFIG_I2C_MULTI_BUS |
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current_bus = 0; |
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#endif |
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base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; |
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if (speed == 400000) |
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iccr1_cks = 0x07; |
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else |
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iccr1_cks = 0x0F; |
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nf2cyc = 1; |
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/* Reset */ |
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sh_i2c_reset(base); |
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/* ICE enable and set clock */ |
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writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1); |
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writeb(nf2cyc, &base->nf2cyc); |
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} |
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/*
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* i2c_read: - Read multiple bytes from an i2c device |
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* |
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* The higher level routines take into account that this function is only |
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* called with len < page length of the device (see configuration file) |
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* |
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* @chip: address of the chip which is to be read |
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* @addr: i2c data address within the chip |
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* @alen: length of the i2c data address (1..2 bytes) |
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* @buffer: where to write the data |
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* @len: how much byte do we want to read |
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* @return: 0 in case of success |
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*/ |
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int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) |
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{ |
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int i = 0; |
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for (i = 0; i < len; i++) |
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buffer[i] = i2c_raw_read(base, chip, addr + i); |
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return 0; |
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} |
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/*
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* i2c_write: - Write multiple bytes to an i2c device |
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* |
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* The higher level routines take into account that this function is only |
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* called with len < page length of the device (see configuration file) |
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* |
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* @chip: address of the chip which is to be written |
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* @addr: i2c data address within the chip |
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* @alen: length of the i2c data address (1..2 bytes) |
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* @buffer: where to find the data to be written |
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* @len: how much byte do we want to read |
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* @return: 0 in case of success |
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*/ |
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int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) |
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{ |
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return i2c_raw_write(base, chip, addr, buffer, len); |
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} |
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/*
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* i2c_probe: - Test if a chip answers for a given i2c address |
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* |
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* @chip: address of the chip which is searched for |
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* @return: 0 if a chip was found, -1 otherwhise |
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*/ |
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int i2c_probe(u8 chip) |
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{ |
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u8 byte; |
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return i2c_read(chip, 0, 0, &byte, 1); |
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} |
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Loading…
Reference in new issue