@ -34,7 +34,7 @@
*/
# define CONFIG_SYS_TEXT_BASE 0x23f 00000
# define CONFIG_SYS_TEXT_BASE 0x210 00000
/* ARM asynchronous clock */
# define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
@ -168,4 +168,54 @@
# define CONFIG_SYS_MALLOC_LEN \
ROUND ( 3 * CONFIG_ENV_SIZE + 128 * 1024 , 0x1000 )
/* Defines for SPL */
# define CONFIG_SPL_FRAMEWORK
# define CONFIG_SPL_TEXT_BASE 0x0
# define CONFIG_SPL_MAX_SIZE (11 * 1024)
# define CONFIG_SPL_STACK (16 * 1024)
# define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
# define CONFIG_SPL_BSS_MAX_SIZE (3 * 1024)
# define CONFIG_SPL_LIBCOMMON_SUPPORT
# define CONFIG_SPL_LIBGENERIC_SUPPORT
# define CONFIG_SPL_SERIAL_SUPPORT
# define CONFIG_SPL_BOARD_INIT
# define CONFIG_SPL_GPIO_SUPPORT
# define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
# define CONFIG_SPL_NAND_SUPPORT
# define CONFIG_SYS_USE_NANDFLASH 1
# define CONFIG_SPL_NAND_DRIVERS
# define CONFIG_SPL_NAND_BASE
# define CONFIG_SPL_NAND_ECC
# define CONFIG_SPL_NAND_RAW_ONLY
# define CONFIG_SPL_NAND_SOFTECC
# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
# define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
# define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
# define CONFIG_SYS_NAND_5_ADDR_CYCLE
# define CONFIG_SYS_NAND_SIZE (256*1024*1024)
# define CONFIG_SYS_NAND_PAGE_SIZE 2048
# define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
# define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE )
# define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
# define CONFIG_SYS_NAND_ECCSIZE 256
# define CONFIG_SYS_NAND_ECCBYTES 3
# define CONFIG_SYS_NAND_OOBSIZE 64
# define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
48 , 49 , 50 , 51 , 52 , 53 , 54 , 55 , \
56 , 57 , 58 , 59 , 60 , 61 , 62 , 63 , }
# define CONFIG_SPL_ATMEL_SIZE
# define CONFIG_SYS_MASTER_CLOCK 132096000
# define AT91_PLL_LOCK_TIMEOUT 1000000
# define CONFIG_SYS_AT91_PLLA 0x202A3F01
# define CONFIG_SYS_MCKR 0x1300
# define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
# define CONFIG_SYS_AT91_PLLB 0x10193F05
# endif