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powerpc: ppc4xx: remove pcs440ep support

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This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Stefan Roese <sr@denx.de>
master
Masahiro Yamada 10 years ago committed by Tom Rini
parent c6999e5f85
commit 242836a893
11 changed files with 1 additions and 1930 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/powerpc/cpu/ppc4xx/Kconfig
  2. 9
      board/pcs440ep/Kconfig
  3. 6
      board/pcs440ep/MAINTAINERS
  4. 9
      board/pcs440ep/Makefile
  5. 23
      board/pcs440ep/config.mk
  6. 607
      board/pcs440ep/flash.c
  7. 56
      board/pcs440ep/init.S
  8. 755
      board/pcs440ep/pcs440ep.c
  9. 4
      configs/pcs440ep_defconfig
  10. 1
      doc/README.scrapyard
  11. 457
      include/configs/pcs440ep.h

4
arch/powerpc/cpu/ppc4xx/Kconfig
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@ -8,9 +8,6 @@ choice
prompt "Target select"
optional
config TARGET_PCS440EP
bool "Support pcs440ep"
config TARGET_SBC405
bool "Support sbc405"
@ -177,7 +174,6 @@ source "board/gdsys/intip/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
source "board/pcs440ep/Kconfig"
source "board/sbc405/Kconfig"
source "board/t3corp/Kconfig"
source "board/xes/xpedite1000/Kconfig"

9
board/pcs440ep/Kconfig
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@ -1,9 +0,0 @@
if TARGET_PCS440EP
config SYS_BOARD
default "pcs440ep"
config SYS_CONFIG_NAME
default "pcs440ep"
endif

6
board/pcs440ep/MAINTAINERS
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@ -1,6 +0,0 @@
PCS440EP BOARD
M: Stefan Roese <sr@denx.de>
S: Maintained
F: board/pcs440ep/
F: include/configs/pcs440ep.h
F: configs/pcs440ep_defconfig

9
board/pcs440ep/Makefile
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@ -1,9 +0,0 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = pcs440ep.o flash.o
extra-y += init.o

23
board/pcs440ep/config.mk
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@ -1,23 +0,0 @@
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
#
# PCS440EP board
#
# Check the U-Boot Image with a SHA1 checksum
ALL-y += u-boot.sha1
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif

607
board/pcs440ep/flash.c
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@ -1,607 +0,0 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#ifndef CONFIG_SYS_FLASH_READ0
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#endif
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*
* Functions
*/
static int write_word(flash_info_t *info, ulong dest, ulong data);
static ulong flash_get_size(vu_long *addr, flash_info_t *info);
unsigned long flash_init(void)
{
unsigned long size_b0, size_b1;
int i;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
base_b0 = FLASH_BASE0_PRELIM;
size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
base_b1 = FLASH_BASE1_PRELIM;
size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
return (size_b0 + size_b1);
}
void flash_print_info(flash_info_t *info)
{
int i;
int k;
int size;
int erased;
volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_STM: printf ("ST Micro"); break;
case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
case FLASH_MAN_MX: printf ("MXIC "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM040: printf ("AM29LV040B (4 Mbit, uniform sector size)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 M, top sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 M, bottom sector)\n");
break;
case FLASH_AMDL322T: printf ("AM29DL322T (32 M, top sector)\n");
break;
case FLASH_AMDL322B: printf ("AM29DL322B (32 M, bottom sector)\n");
break;
case FLASH_AMDL323T: printf ("AM29DL323T (32 M, top sector)\n");
break;
case FLASH_AMDL323B: printf ("AM29DL323B (32 M, bottom sector)\n");
break;
case FLASH_SST020: printf ("SST39LF/VF020 (2 Mbit, uniform sector size)\n");
break;
case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
break;
case STM_ID_M29W040B: printf ("ST Micro M29W040B (4 Mbit, uniform sector size)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20, info->sector_count);
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
/*
* Check if whole sector is erased
*/
if (i != (info->sector_count-1))
size = info->start[i+1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */
for (k=0; k<size; k++) {
if (*flash++ != 0xffffffff) {
erased = 0;
break;
}
}
if ((i % 5) == 0)
printf ("\n ");
/* print empty and read-only info */
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " ");
#else
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
#endif
}
printf ("\n");
return;
}
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long *addr, flash_info_t *info)
{
short i;
short n;
volatile CONFIG_SYS_FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
value = addr2[CONFIG_SYS_FLASH_READ0];
switch (value) {
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
info->flash_id = FLASH_MAN_EXCEL;
break;
case (CONFIG_SYS_FLASH_WORD_SIZE)MX_MANUFACT:
info->flash_id = FLASH_MAN_MX;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
switch (value) {
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 0.5 MB */
break;
case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_M29W040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x0080000; /* => 0,5 MB */
break;
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 4 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 4 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 4 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 4 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 4 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 4 MB */
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
info->flash_id += FLASH_SST020;
info->sector_count = 64;
info->size = 0x00040000;
break; /* => 256 kB */
case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
info->flash_id += FLASH_SST040;
info->sector_count = 128;
info->size = 0x00080000;
break; /* => 512 kB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00001000);
} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
/* set sector offsets for bottom boot block type */
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
info->start[i] = base;
base += 8 << 10;
}
while (i < info->sector_count) { /* 64k regular sectors */
info->start[i] = base;
base += 64 << 10;
++i;
}
} else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
/* set sector offsets for top boot block type */
base += info->size;
i = info->sector_count;
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
base -= 8 << 10;
--i;
info->start[i] = base;
}
while (i > 0) { /* 64k regular sectors */
base -= 64 << 10;
--i;
info->start[i] = base;
}
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
info->protect[i] = 0;
else
info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
}
return (info->size);
}
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf ("- missing\n");
else
printf ("- no sectors to erase\n");
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect)
if (info->protect[sect])
prot++;
if (prot)
printf ("- Warning: %d protected sectors will not be erased!\n", prot);
else
printf ("\n");
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
/* re-enable interrupts if necessary */
if (flag) {
enable_interrupts();
flag = 0;
}
/* data polling for D7 */
start = get_timer (0);
while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
(CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
return (1);
}
} else {
if (sect == s_first) {
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
}
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
}
/*
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i)
data = (data << 8) | *src++;
if ((rc = write_word(info, wp, data)) != 0)
return (rc);
wp += 4;
cnt -= 4;
}
if (cnt == 0)
return (0);
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp)
data = (data << 8) | (*(uchar *)cp);
return (write_word(info, wp, data));
}
/*
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word(flash_info_t *info, ulong dest, ulong data)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
int i;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data)
return (2);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
dest2[i] = data2[i];
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
return (1);
}
}
return (0);
}

56
board/pcs440ep/init.S
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@ -1,56 +0,0 @@
/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <ppc_asm.tmpl>
#include <asm/mmu.h>
#include <config.h>
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR detection
* routine.
*/
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
/* PCI */
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
/* USB 2.0 Device */
tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
tlbtab_end

755
board/pcs440ep/pcs440ep.c
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/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <malloc.h>
#include <command.h>
#include <crc.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <status_led.h>
#include <u-boot/sha1.h>
#include <asm/io.h>
#include <net.h>
#include <ata.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
unsigned char sha1_checksum[SHA1_SUM_LEN];
/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
static void set_leds (int val)
{
out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
}
#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
void __led_init (led_id_t mask, int state)
{
int val = GET_LEDS;
if (state == STATUS_LED_ON)
val |= mask;
else
val &= ~mask;
set_leds (val);
}
void __led_set (led_id_t mask, int state)
{
int val = GET_LEDS;
if (state == STATUS_LED_ON)
val |= mask;
else if (state == STATUS_LED_OFF)
val &= ~mask;
set_leds (val);
}
void __led_toggle (led_id_t mask)
{
int val = GET_LEDS;
val ^= mask;
set_leds (val);
}
static void status_led_blink (void)
{
int i;
int val = GET_LEDS;
/* set all LED which are on, to state BLINKING */
for (i = 0; i < 4; i++) {
if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING);
else status_led_set (3 - i, STATUS_LED_OFF);
val = val >> 1;
}
}
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress (int val)
{
/* find all valid Codes for val in README */
if (val == -BOOTSTAGE_ID_NEED_RESET)
return;
if (val < 0) {
/* smthing goes wrong */
status_led_blink ();
return;
}
switch (val) {
case BOOTSTAGE_ID_CHECK_MAGIC:
/* validating Image */
status_led_set(0, STATUS_LED_OFF);
status_led_set(1, STATUS_LED_ON);
status_led_set(2, STATUS_LED_ON);
break;
case BOOTSTAGE_ID_RUN_OS:
status_led_set(0, STATUS_LED_ON);
status_led_set(1, STATUS_LED_ON);
status_led_set(2, STATUS_LED_ON);
break;
#if 0
case BOOTSTAGE_ID_NET_ETH_START:
/* starting Ethernet configuration */
status_led_set(0, STATUS_LED_OFF);
status_led_set(1, STATUS_LED_OFF);
status_led_set(2, STATUS_LED_ON);
break;
#endif
case BOOTSTAGE_ID_NET_START:
/* loading Image */
status_led_set(0, STATUS_LED_ON);
status_led_set(1, STATUS_LED_OFF);
status_led_set(2, STATUS_LED_ON);
break;
}
}
#endif
int board_early_init_f(void)
{
register uint reg;
set_leds(0); /* display boot info counter */
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(EBC0_CFGADDR, EBC0_CFG);
reg = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
* GPIO's are alreay setup in arch/powerpc/cpu/ppc4xx/cpu_init.c
* via define from board config file.
*-------------------------------------------------------------------*/
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC0ER, 0x00000000); /* disable all */
mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
mtdcr(UIC0PR, 0xfffffe1f); /* per ref-board manual */
mtdcr(UIC0TR, 0x01c00000); /* per ref-board manual */
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC0SR, 0xffffffff); /* clear all */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
mtdcr(UIC1ER, 0x00000000); /* disable all */
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(UIC1SR, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(SDR0_PCI0, reg);
mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(SDR0_PFC0, 0x00000000); /* Pin function: enable GPIO49-63 */
mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
return 0;
}
#define EEPROM_LEN 256
static void load_ethaddr(void)
{
int ok_ethaddr, ok_eth1addr;
int ret;
uchar buf[EEPROM_LEN];
char *use_eeprom;
u16 checksumcrc16 = 0;
/* If the env is sane, then nothing for us to do */
ok_ethaddr = eth_getenv_enetaddr("ethaddr", buf);
ok_eth1addr = eth_getenv_enetaddr("eth1addr", buf);
if (ok_ethaddr && ok_eth1addr)
return;
/* read the MACs from EEprom */
status_led_set (0, STATUS_LED_ON);
status_led_set (1, STATUS_LED_ON);
ret = eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 0, buf, EEPROM_LEN);
if (ret == 0) {
checksumcrc16 = cyg_crc16 (buf, EEPROM_LEN - 2);
/* check, if the EEprom is programmed:
* - The Prefix(Byte 0,1,2) is equal to "ATR"
* - The checksum, stored in the last 2 Bytes, is correct
*/
if ((strncmp ((char *)buf,"ATR",3) != 0) ||
((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
/* EEprom is not programmed */
printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
} else {
/* get the MACs */
if (!ok_ethaddr)
eth_setenv_enetaddr("ethaddr", &buf[3]);
if (!ok_eth1addr)
eth_setenv_enetaddr("eth1addr", &buf[9]);
return;
}
}
/* some error reading the EEprom */
if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
/* dont use bootcmd */
setenv("bootdelay", "-1");
return;
}
/* == default ? use standard */
if (strncmp (use_eeprom, "default", 7) == 0) {
return;
}
/* Env doesnt exist -> hang */
status_led_blink ();
/* here we do this "handy" because we have no interrupts
at this time */
puts ("### EEPROM ERROR ### Please RESET the board ###\n");
for (;;) {
__led_toggle (12);
udelay (100000);
}
return;
}
#ifdef CONFIG_PREBOOT
static uchar kbd_magic_prefix[] = "key_magic";
static uchar kbd_command_prefix[] = "key_cmd";
struct kbd_data_t {
char s1;
char s2;
};
struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
{
char *val;
unsigned long tmp;
/* use the DIPs for some bootoptions */
val = getenv (ENV_NAME_DIP);
tmp = simple_strtoul (val, NULL, 16);
kbd_data->s2 = (tmp & 0x0f);
kbd_data->s1 = (tmp & 0xf0) >> 4;
return kbd_data;
}
static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
{
char s1 = str[0];
if (s1 >= '0' && s1 <= '9')
s1 -= '0';
else if (s1 >= 'a' && s1 <= 'f')
s1 = s1 - 'a' + 10;
else if (s1 >= 'A' && s1 <= 'F')
s1 = s1 - 'A' + 10;
else
return -1;
if (s1 != kbd_data->s1) return -1;
s1 = str[1];
if (s1 >= '0' && s1 <= '9')
s1 -= '0';
else if (s1 >= 'a' && s1 <= 'f')
s1 = s1 - 'a' + 10;
else if (s1 >= 'A' && s1 <= 'F')
s1 = s1 - 'A' + 10;
else
return -1;
if (s1 != kbd_data->s2) return -1;
return 0;
}
static char *key_match (const struct kbd_data_t *kbd_data)
{
char magic[sizeof (kbd_magic_prefix) + 1];
char *suffix;
char *kbd_magic_keys;
/*
* The following string defines the characters that can be appended
* to "key_magic" to form the names of environment variables that
* hold "magic" key codes, i. e. such key codes that can cause
* pre-boot actions. If the string is empty (""), then only
* "key_magic" is checked (old behaviour); the string "125" causes
* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
*/
if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
kbd_magic_keys = "";
/* loop over all magic keys;
* use '\0' suffix in case of empty string
*/
for (suffix = kbd_magic_keys; *suffix ||
suffix == kbd_magic_keys; ++suffix) {
sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
if (compare_magic (kbd_data, getenv (magic)) == 0) {
char cmd_name[sizeof (kbd_command_prefix) + 1];
char *cmd;
sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
cmd = getenv (cmd_name);
return (cmd);
}
}
return (NULL);
}
#endif /* CONFIG_PREBOOT */
static int pcs440ep_readinputs (void)
{
int i;
char value[20];
/* read the inputs and set the Envvars */
/* Revision Level Bit 26 - 29 */
i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
i = swapbits[i];
sprintf (value, "%02x", i);
setenv (ENV_NAME_REVLEV, value);
/* Solder Switch Bit 30 - 33 */
i = (in32 (GPIO0_IR) & 0x00000003) << 2;
i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
i = swapbits[i];
sprintf (value, "%02x", i);
setenv (ENV_NAME_SOLDER, value);
/* DIP Switch Bit 49 - 56 */
i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
sprintf (value, "%02x", i);
setenv (ENV_NAME_DIP, value);
return 0;
}
#if defined(CONFIG_SHA1_CHECK_UB_IMG)
/*************************************************************************
* calculate a SHA1 sum for the U-Boot image in Flash.
*
************************************************************************/
static int pcs440ep_sha1 (int docheck)
{
unsigned char *data;
unsigned char *ptroff;
unsigned char output[20];
unsigned char org[20];
int i, len = CONFIG_SHA1_LEN;
memcpy ((char *)CONFIG_SYS_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
data = (unsigned char *)CONFIG_SYS_LOAD_ADDR;
ptroff = &data[len + SHA1_SUM_POS];
for (i = 0; i < SHA1_SUM_LEN; i++) {
org[i] = ptroff[i];
ptroff[i] = 0;
}
sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
if (docheck == 2) {
for (i = 0; i < 20 ; i++) {
printf("%02X ", output[i]);
}
printf("\n");
}
if (docheck == 1) {
for (i = 0; i < 20 ; i++) {
if (org[i] != output[i]) return 1;
}
}
return 0;
}
/*************************************************************************
* do some checks after the SHA1 checksum from the U-Boot Image was
* calculated.
*
************************************************************************/
static void pcs440ep_checksha1 (void)
{
int ret;
char *cs_test;
status_led_set (0, STATUS_LED_OFF);
status_led_set (1, STATUS_LED_OFF);
status_led_set (2, STATUS_LED_ON);
ret = pcs440ep_sha1 (1);
if (ret == 0) return;
if ((cs_test = getenv ("cs_test")) == NULL) {
/* Env doesnt exist -> hang */
status_led_blink ();
/* here we do this "handy" because we have no interrupts
at this time */
puts ("### SHA1 ERROR ### Please RESET the board ###\n");
for (;;) {
__led_toggle (2);
udelay (100000);
}
}
if (strncmp (cs_test, "off", 3) == 0) {
printf ("SHA1 U-Boot sum NOT ok!\n");
setenv ("bootdelay", "-1");
}
}
#else
static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
#endif
int misc_init_r (void)
{
uint pbcr;
int size_val = 0;
load_ethaddr();
/* Re-do sizing to get full correct info */
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
switch (gd->bd->bi_flashsize) {
case 1 << 20:
size_val = 0;
break;
case 2 << 20:
size_val = 1;
break;
case 4 << 20:
size_val = 2;
break;
case 8 << 20:
size_val = 3;
break;
case 16 << 20:
size_val = 4;
break;
case 32 << 20:
size_val = 5;
break;
case 64 << 20:
size_val = 6;
break;
case 128 << 20:
size_val = 7;
break;
}
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
mtdcr(EBC0_CFGADDR, PB0CR);
mtdcr(EBC0_CFGDATA, pbcr);
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[1]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[1]);
pcs440ep_readinputs ();
pcs440ep_checksha1 ();
#ifdef CONFIG_PREBOOT
{
struct kbd_data_t kbd_data;
/* Decode keys */
char *str = strdup (key_match (get_keys (&kbd_data)));
/* Set or delete definition */
setenv ("preboot", str);
free (str);
}
#endif /* CONFIG_PREBOOT */
return 0;
}
int checkboard(void)
{
char buf[64];
int i = getenv_f("serial#", buf, sizeof(buf));
printf("Board: PCS440EP");
if (i > 0) {
puts(", serial# ");
puts(buf);
}
putc('\n');
return (0);
}
void spd_ddr_init_hang (void)
{
status_led_set (0, STATUS_LED_OFF);
status_led_set (1, STATUS_LED_ON);
/* we cannot use hang() because we are still running from
Flash, and so the status_led driver is not initialized */
puts ("### SDRAM ERROR ### Please RESET the board ###\n");
for (;;) {
__led_toggle (4);
udelay (100000);
}
}
phys_size_t initdram (int board_type)
{
long dram_size = 0;
status_led_set (0, STATUS_LED_ON);
status_led_set (1, STATUS_LED_OFF);
dram_size = spd_sdram();
status_led_set (0, STATUS_LED_OFF);
status_led_set (1, STATUS_LED_ON);
if (dram_size == 0) {
hang();
}
return dram_size;
}
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
*
************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
}
#endif
/*************************************************************************
* "led" Commando for the U-Boot shell
*
************************************************************************/
int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 0, i;
ulong pattern = 0;
pattern = simple_strtoul (argv[1], NULL, 16);
if (pattern > 0x400) {
int val = GET_LEDS;
printf ("led: %x\n", val);
return rcode;
}
if (pattern > 0x200) {
status_led_blink ();
hang ();
return rcode;
}
if (pattern > 0x100) {
status_led_blink ();
return rcode;
}
pattern &= 0x0f;
for (i = 0; i < 4; i++) {
if (pattern & 0x01) status_led_set (i, STATUS_LED_ON);
else status_led_set (i, STATUS_LED_OFF);
pattern = pattern >> 1;
}
return rcode;
}
U_BOOT_CMD(
led, 2, 1, do_led,
"set the DIAG-LED",
"[bitmask] 0x01 = DIAG 1 on\n"
" 0x02 = DIAG 2 on\n"
" 0x04 = DIAG 3 on\n"
" 0x08 = DIAG 4 on\n"
" > 0x100 set the LED, who are on, to state blinking"
);
#if defined(CONFIG_SHA1_CHECK_UB_IMG)
/*************************************************************************
* "sha1" Commando for the U-Boot shell
*
************************************************************************/
int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = -1;
if (argc < 2) {
usage:
return cmd_usage(cmdtp);
}
if (argc >= 3) {
unsigned char *data;
unsigned char output[20];
int len;
int i;
data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
len = simple_strtoul (argv[2], NULL, 16);
sha1_csum (data, len, (unsigned char *)output);
printf ("U-Boot sum:\n");
for (i = 0; i < 20 ; i++) {
printf ("%02X ", output[i]);
}
printf ("\n");
if (argc == 4) {
data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
memcpy (data, output, 20);
}
return 0;
}
if (argc == 2) {
char *ptr = argv[1];
if (*ptr != '-') goto usage;
ptr++;
if ((*ptr == 'c') || (*ptr == 'C')) {
rcode = pcs440ep_sha1 (1);
printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
} else if ((*ptr == 'p') || (*ptr == 'P')) {
rcode = pcs440ep_sha1 (2);
} else {
rcode = pcs440ep_sha1 (0);
}
return rcode;
}
return rcode;
}
U_BOOT_CMD(
sha1, 4, 1, do_sha1,
"calculate the SHA1 Sum",
"address len [addr] calculate the SHA1 sum [save at addr]\n"
" -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
" -c check the U-Boot image in flash"
);
#endif
#if defined (CONFIG_CMD_IDE)
/* These addresses need to be shifted one place to the left
* ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
* These values are shifted
*/
void inline ide_outb(int dev, int port, unsigned char val)
{
debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
dev, port, val, (ATA_CURR_BASE(dev)+port));
out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val);
}
unsigned char inline ide_inb(int dev, int port)
{
uchar val;
val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)));
debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
dev, port, (ATA_CURR_BASE(dev)+port), val);
return (val);
}
#endif
#ifdef CONFIG_IDE_PREINIT
int ide_preinit (void)
{
/* Set True IDE Mode */
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
udelay (100000);
return 0;
}
#endif
#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
void ide_set_reset (int idereset)
{
debug ("ide_reset(%d)\n", idereset);
if (idereset == 0) {
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
} else {
out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
}
udelay (10000);
}
#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
/* this is motly the same as it should, causing a little code duplication */
#if defined(CONFIG_CMD_IDE)
#define EIEIO __asm__ volatile ("eieio")
void ide_input_swap_data(int dev, ulong *sect_buf, int words)
{
volatile ushort *pbuf =
(ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf = (ushort *) sect_buf;
debug("in input swap data base for read is %lx\n",
(unsigned long) pbuf);
while (words--) {
*dbuf++ = *pbuf;
*dbuf++ = *pbuf;
}
}
void ide_output_data(int dev, const ulong *sect_buf, int words)
{
ushort *dbuf;
volatile ushort *pbuf;
pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
dbuf = (ushort *) sect_buf;
while (words--) {
EIEIO;
*pbuf = ld_le16(dbuf++);
EIEIO;
*pbuf = ld_le16(dbuf++);
}
}
void ide_input_data(int dev, ulong *sect_buf, int words)
{
ushort *dbuf;
volatile ushort *pbuf;
pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
dbuf = (ushort *) sect_buf;
debug("in input data base for read is %lx\n", (unsigned long) pbuf);
while (words--) {
EIEIO;
*dbuf++ = ld_le16(pbuf);
EIEIO;
*dbuf++ = ld_le16(pbuf);
}
}
#endif

4
configs/pcs440ep_defconfig
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CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_PCS440EP=y
# CONFIG_CMD_SETEXPR is not set

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doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de>
p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
csb272/csb472 powerpc ppc4xx - - Tolunay Orkun <torkun@nextio.com>

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include/configs/pcs440ep.h
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/*
* (C) Copyright 2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/************************************************************************
* pcs440ep.h - configuration for PCS440EP board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/* new uImage format support */
#define CONFIG_FIT 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
/*Don't change either of these*/
#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
/*Don't change either of these*/
#define CONFIG_SYS_USB_DEVICE 0x50000000
#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#define CONFIG_ENV_OVERWRITE 1
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
#define ENV_NAME_REVLEV "revision_level"
#define ENV_NAME_SOLDER "solder_switch"
#define ENV_NAME_DIP "dip"
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#undef CONFIG_DDR_ECC /* don't use ECC */
#define SPD_EEPROM_ADDRESS {0x50}
#define CONFIG_PROG_SDRAM_TLB 1
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=pcs440ep\0" \
"use_eeprom_ethaddr=default\0" \
"cs_test=off\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=/tftpboot/pcs440ep/uImage\0" \
"kernel_addr=FFF00000\0" \
"ramdisk_addr=FFF00000\0" \
"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 100000 FFFA0000 60000\0" \
"upd=run load update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
/* check U-Boot image with SHA1 sum */
#define CONFIG_SHA1_CHECK_UB_IMG 1
#define CONFIG_SHA1_START CONFIG_SYS_MONITOR_BASE
#define CONFIG_SHA1_LEN CONFIG_SYS_MONITOR_LEN
/*-----------------------------------------------------------------------
* Definitions for status LED
*/
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1
#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */
#define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
#define STATUS_LED_STATE STATUS_LED_OFF
#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */
#define STATUS_LED_PERIOD1 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
#define STATUS_LED_STATE1 STATUS_LED_ON
#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */
#define STATUS_LED_PERIOD2 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
#define STATUS_LED_STATE2 STATUS_LED_OFF
#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */
#define STATUS_LED_PERIOD3 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
#define STATUS_LED_STATE3 STATUS_LED_OFF
#define CONFIG_SHOW_BOOT_PROGRESS 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_PHY1_ADDR 2
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#ifdef CONFIG_440EP
/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/*Comment this out to enable USB 1.1 device*/
#define USB_2_0_DEVICE
#endif /*CONFIG_440EP*/
#ifdef DEBUG
#define CONFIG_PANIC_HANG
#else
#define CONFIG_HW_WATCHDOG /* watchdog */
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_REISER
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_USB
#define CONFIG_SUPPORT_VFAT
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_LYNXKDI 1 /* support kdi files */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT
#define CONFIG_SYS_PCI_MASTER_INIT
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */
#define CONFIG_SYS_FLASH FLASH_BASE0_PRELIM
#define CONFIG_SYS_SRAM 0xF1000000
#define CONFIG_SYS_FPGA 0xF2000000
#define CONFIG_SYS_CF1 0xF0000000
#define CONFIG_SYS_CF2 0xF0100000
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */
#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 1 (SRAM) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */
#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 2 (FPGA) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 3 (CompactFlash) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x080BD400
#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
/* Memory Bank 4 (CompactFlash) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x080BD400
#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
}, \
{ \
/* GPIO Core 1 */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#endif
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
#define CONFIG_IDE_PREINIT 1
#define CONFIG_IDE_RESET 1
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF1
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET 0
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x0000)
#endif /* __CONFIG_H */
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