Tom Rini
10 years ago
commit
272a1acf1e
@ -0,0 +1,82 @@ |
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/*
|
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <asm/fsl_portals.h> |
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#include <asm/fsl_liodn.h> |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { |
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/* dqrr liodn, frame data liodn, liodn off, sdest */ |
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SET_QP_INFO(1, 27, 1, 0), |
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SET_QP_INFO(2, 28, 1, 0), |
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SET_QP_INFO(3, 29, 1, 1), |
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SET_QP_INFO(4, 30, 1, 1), |
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SET_QP_INFO(5, 31, 1, 2), |
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SET_QP_INFO(6, 32, 1, 2), |
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SET_QP_INFO(7, 33, 1, 3), |
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SET_QP_INFO(8, 34, 1, 3), |
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SET_QP_INFO(9, 35, 1, 0), |
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SET_QP_INFO(10, 36, 1, 0), |
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}; |
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#endif |
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struct liodn_id_table liodn_tbl[] = { |
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#ifdef CONFIG_SYS_DPAA_QBMAN |
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SET_QMAN_LIODN(62), |
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SET_BMAN_LIODN(63), |
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#endif |
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SET_SDHC_LIODN(1, 552), |
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SET_USB_LIODN(1, "fsl-usb2-mph", 553), |
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SET_USB_LIODN(2, "fsl-usb2-dr", 554), |
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SET_SATA_LIODN(1, 555), |
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), |
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), |
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SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), |
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|
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SET_DMA_LIODN(1, "fsl,elo3-dma", 147), |
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SET_DMA_LIODN(2, "fsl,elo3-dma", 227), |
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/* SET_NEXUS_LIODN(557), -- not yet implemented */ |
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SET_QE_LIODN(559), |
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SET_TDM_LIODN(560), |
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}; |
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int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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struct liodn_id_table fman1_liodn_tbl[] = { |
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SET_FMAN_RX_1G_LIODN(1, 0, 88), |
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SET_FMAN_RX_1G_LIODN(1, 1, 89), |
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SET_FMAN_RX_1G_LIODN(1, 2, 90), |
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SET_FMAN_RX_1G_LIODN(1, 3, 91), |
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SET_FMAN_RX_10G_LIODN(1, 0, 94), |
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}; |
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int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); |
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#endif |
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|
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struct liodn_id_table sec_liodn_tbl[] = { |
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SET_SEC_JR_LIODN_ENTRY(0, 454, 458), |
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SET_SEC_JR_LIODN_ENTRY(1, 455, 459), |
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SET_SEC_JR_LIODN_ENTRY(2, 456, 460), |
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SET_SEC_JR_LIODN_ENTRY(3, 457, 461), |
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SET_SEC_RTIC_LIODN_ENTRY(a, 453), |
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SET_SEC_RTIC_LIODN_ENTRY(b, 549), |
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SET_SEC_RTIC_LIODN_ENTRY(c, 550), |
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SET_SEC_RTIC_LIODN_ENTRY(d, 551), |
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SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), |
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SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), |
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}; |
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int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); |
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struct liodn_id_table liodn_bases[] = { |
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[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), |
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#ifdef CONFIG_SYS_DPAA_FMAN |
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[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), |
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#endif |
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}; |
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@ -0,0 +1,52 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/fsl_serdes.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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static u8 serdes_cfg_tbl[][4] = { |
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[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1}, |
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[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1}, |
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[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1}, |
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[0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1}, |
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[0x46] = {PCIE1, PCIE1, PCIE2, SATA1}, |
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[0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1}, |
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[0x56] = {PCIE1, PCIE3, PCIE2, SATA1}, |
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[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1}, |
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[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, |
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[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1}, |
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[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, |
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[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, |
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SGMII_2500_FM1_DTSEC1}, |
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[0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1}, |
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[0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, |
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SGMII_2500_FM1_DTSEC1}, |
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[0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1}, |
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[0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1}, |
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}; |
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) |
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{ |
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return serdes_cfg_tbl[cfg][lane]; |
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} |
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int is_serdes_prtcl_valid(int serdes, u32 prtcl) |
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{ |
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int i; |
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if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) |
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return 0; |
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for (i = 0; i < 4; i++) { |
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if (serdes_cfg_tbl[prtcl][i] != NONE) |
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return 1; |
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} |
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return 0; |
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} |
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@ -0,0 +1,491 @@ |
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <i2c.h> |
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#include <asm/immap_85xx.h> |
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#include "vid.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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int __weak i2c_multiplexer_select_vid_channel(u8 channel) |
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{ |
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return 0; |
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} |
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/*
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* Compensate for a board specific voltage drop between regulator and SoC |
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* return a value in mV |
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*/ |
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int __weak board_vdd_drop_compensation(void) |
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{ |
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return 0; |
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} |
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/*
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* Get the i2c address configuration for the IR regulator chip |
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* |
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* There are some variance in the RDB HW regarding the I2C address configuration |
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* for the IR regulator chip, which is likely a problem of external resistor |
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* accuracy. So we just check each address in a hopefully non-intrusive mode |
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* and use the first one that seems to work |
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* |
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* The IR chip can show up under the following addresses: |
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* 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA) |
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* 0x09 (Verified on T1040RDB-PA) |
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* 0x38 (Verified on T2080QDS, T2081QDS) |
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*/ |
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static int find_ir_chip_on_i2c(void) |
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{ |
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int i2caddress; |
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int ret; |
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u8 byte; |
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int i; |
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const int ir_i2c_addr[] = {0x38, 0x08, 0x09}; |
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/* Check all the address */ |
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for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { |
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i2caddress = ir_i2c_addr[i]; |
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ret = i2c_read(i2caddress, |
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IR36021_MFR_ID_OFFSET, 1, (void *)&byte, |
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sizeof(byte)); |
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if ((ret >= 0) && (byte == IR36021_MFR_ID)) |
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return i2caddress; |
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} |
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return -1; |
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} |
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/* Maximum loop count waiting for new voltage to take effect */ |
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#define MAX_LOOP_WAIT_NEW_VOL 100 |
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/* Maximum loop count waiting for the voltage to be stable */ |
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#define MAX_LOOP_WAIT_VOL_STABLE 100 |
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/*
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* read_voltage from sensor on I2C bus |
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* We use average of 4 readings, waiting for WAIT_FOR_ADC before |
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* another reading |
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*/ |
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#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ |
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/* If an INA220 chip is available, we can use it to read back the voltage
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* as it may have a higher accuracy than the IR chip for the same purpose |
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*/ |
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#ifdef CONFIG_VOL_MONITOR_INA220 |
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#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ |
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#define ADC_MIN_ACCURACY 4 |
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#else |
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#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */ |
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#define ADC_MIN_ACCURACY 4 |
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#endif |
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#ifdef CONFIG_VOL_MONITOR_INA220 |
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static int read_voltage_from_INA220(int i2caddress) |
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{ |
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int i, ret, voltage_read = 0; |
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u16 vol_mon; |
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u8 buf[2]; |
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for (i = 0; i < NUM_READINGS; i++) { |
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ret = i2c_read(I2C_VOL_MONITOR_ADDR, |
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I2C_VOL_MONITOR_BUS_V_OFFSET, 1, |
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(void *)&buf, 2); |
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if (ret) { |
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printf("VID: failed to read core voltage\n"); |
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return ret; |
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} |
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vol_mon = (buf[0] << 8) | buf[1]; |
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if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { |
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printf("VID: Core voltage sensor error\n"); |
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return -1; |
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} |
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debug("VID: bus voltage reads 0x%04x\n", vol_mon); |
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/* LSB = 4mv */ |
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voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; |
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udelay(WAIT_FOR_ADC); |
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} |
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/* calculate the average */ |
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voltage_read /= NUM_READINGS; |
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return voltage_read; |
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} |
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#endif |
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/* read voltage from IR */ |
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#ifdef CONFIG_VOL_MONITOR_IR36021_READ |
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static int read_voltage_from_IR(int i2caddress) |
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{ |
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int i, ret, voltage_read = 0; |
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u16 vol_mon; |
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u8 buf; |
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for (i = 0; i < NUM_READINGS; i++) { |
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ret = i2c_read(i2caddress, |
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IR36021_LOOP1_VOUT_OFFSET, |
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1, (void *)&buf, 1); |
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if (ret) { |
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printf("VID: failed to read vcpu\n"); |
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return ret; |
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} |
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vol_mon = buf; |
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if (!vol_mon) { |
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printf("VID: Core voltage sensor error\n"); |
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return -1; |
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} |
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debug("VID: bus voltage reads 0x%02x\n", vol_mon); |
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/* Resolution is 1/128V. We scale up here to get 1/128mV
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* and divide at the end |
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*/ |
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voltage_read += vol_mon * 1000; |
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udelay(WAIT_FOR_ADC); |
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} |
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/* Scale down to the real mV as IR resolution is 1/128V, rounding up */ |
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voltage_read = DIV_ROUND_UP(voltage_read, 128); |
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/* calculate the average */ |
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voltage_read /= NUM_READINGS; |
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/* Compensate for a board specific voltage drop between regulator and
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* SoC before converting into an IR VID value |
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*/ |
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voltage_read -= board_vdd_drop_compensation(); |
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return voltage_read; |
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} |
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#endif |
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static int read_voltage(int i2caddress) |
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{ |
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int voltage_read; |
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#ifdef CONFIG_VOL_MONITOR_INA220 |
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voltage_read = read_voltage_from_INA220(i2caddress); |
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#elif defined CONFIG_VOL_MONITOR_IR36021_READ |
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voltage_read = read_voltage_from_IR(i2caddress); |
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#else |
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return -1; |
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#endif |
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return voltage_read; |
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} |
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|
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/*
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* We need to calculate how long before the voltage stops to drop |
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* or increase. It returns with the loop count. Each loop takes |
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* several readings (WAIT_FOR_ADC) |
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*/ |
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static int wait_for_new_voltage(int vdd, int i2caddress) |
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{ |
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int timeout, vdd_current; |
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vdd_current = read_voltage(i2caddress); |
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/* wait until voltage starts to reach the target. Voltage slew
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* rates by typical regulators will always lead to stable readings |
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* within each fairly long ADC interval in comparison to the |
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* intended voltage delta change until the target voltage is |
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* reached. The fairly small voltage delta change to any target |
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* VID voltage also means that this function will always complete |
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* within few iterations. If the timeout was ever reached, it would |
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* point to a serious failure in the regulator system. |
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*/ |
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for (timeout = 0; |
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abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) && |
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timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) { |
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vdd_current = read_voltage(i2caddress); |
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} |
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if (timeout >= MAX_LOOP_WAIT_NEW_VOL) { |
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printf("VID: Voltage adjustment timeout\n"); |
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return -1; |
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} |
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return timeout; |
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} |
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|
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/*
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* this function keeps reading the voltage until it is stable or until the |
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* timeout expires |
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*/ |
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static int wait_for_voltage_stable(int i2caddress) |
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{ |
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int timeout, vdd_current, vdd; |
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|
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vdd = read_voltage(i2caddress); |
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udelay(NUM_READINGS * WAIT_FOR_ADC); |
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|
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/* wait until voltage is stable */ |
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vdd_current = read_voltage(i2caddress); |
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/* The maximum timeout is
|
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* MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC |
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*/ |
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for (timeout = MAX_LOOP_WAIT_VOL_STABLE; |
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abs(vdd - vdd_current) > ADC_MIN_ACCURACY && |
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timeout > 0; timeout--) { |
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vdd = vdd_current; |
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udelay(NUM_READINGS * WAIT_FOR_ADC); |
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vdd_current = read_voltage(i2caddress); |
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} |
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if (timeout == 0) |
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return -1; |
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return vdd_current; |
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} |
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|
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#ifdef CONFIG_VOL_MONITOR_IR36021_SET |
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/* Set the voltage to the IR chip */ |
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static int set_voltage_to_IR(int i2caddress, int vdd) |
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{ |
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int wait, vdd_last; |
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int ret; |
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u8 vid; |
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|
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/* Compensate for a board specific voltage drop between regulator and
|
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* SoC before converting into an IR VID value |
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*/ |
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vdd += board_vdd_drop_compensation(); |
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vid = DIV_ROUND_UP(vdd - 245, 5); |
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|
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ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET, |
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1, (void *)&vid, sizeof(vid)); |
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if (ret) { |
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printf("VID: failed to write VID\n"); |
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return -1; |
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} |
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wait = wait_for_new_voltage(vdd, i2caddress); |
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if (wait < 0) |
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return -1; |
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debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); |
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|
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vdd_last = wait_for_voltage_stable(i2caddress); |
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if (vdd_last < 0) |
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return -1; |
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debug("VID: Current voltage is %d mV\n", vdd_last); |
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return vdd_last; |
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} |
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#endif |
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|
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static int set_voltage(int i2caddress, int vdd) |
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{ |
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int vdd_last = -1; |
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|
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#ifdef CONFIG_VOL_MONITOR_IR36021_SET |
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vdd_last = set_voltage_to_IR(i2caddress, vdd); |
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#else |
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#error Specific voltage monitor must be defined |
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#endif |
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return vdd_last; |
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} |
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|
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int adjust_vdd(ulong vdd_override) |
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{ |
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int re_enable = disable_interrupts(); |
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ccsr_gur_t __iomem *gur = |
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(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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u32 fusesr; |
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u8 vid; |
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int vdd_target, vdd_current, vdd_last; |
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int ret, i2caddress; |
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unsigned long vdd_string_override; |
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char *vdd_string; |
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static const uint16_t vdd[32] = { |
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0, /* unused */ |
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9875, /* 0.9875V */ |
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9750, |
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9625, |
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9500, |
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9375, |
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9250, |
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9125, |
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9000, |
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8875, |
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8750, |
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8625, |
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8500, |
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8375, |
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8250, |
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8125, |
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10000, /* 1.0000V */ |
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10125, |
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10250, |
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10375, |
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10500, |
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10625, |
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10750, |
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10875, |
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11000, |
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0, /* reserved */ |
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}; |
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struct vdd_drive { |
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u8 vid; |
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unsigned voltage; |
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}; |
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|
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ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); |
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if (ret) { |
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debug("VID: I2C failed to switch channel\n"); |
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ret = -1; |
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goto exit; |
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} |
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ret = find_ir_chip_on_i2c(); |
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if (ret < 0) { |
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printf("VID: Could not find voltage regulator on I2C.\n"); |
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ret = -1; |
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goto exit; |
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} else { |
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i2caddress = ret; |
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debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); |
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} |
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|
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/* get the voltage ID from fuse status register */ |
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fusesr = in_be32(&gur->dcfg_fusesr); |
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/*
|
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* VID is used according to the table below |
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* --------------------------------------- |
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* | DA_V | |
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* |-------------------------------------| |
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* | 5b00000 | 5b00001-5b11110 | 5b11111 | |
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* ---------------+---------+-----------------+---------| |
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* | D | 5b00000 | NO VID | VID = DA_V | NO VID | |
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* | A |----------+---------+-----------------+---------| |
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* | _ | 5b00001 |VID = | VID = |VID = | |
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* | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT| |
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* | _ | 5b11110 | | | | |
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* | A |----------+---------+-----------------+---------| |
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* | L | 5b11111 | No VID | VID = DA_V | NO VID | |
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* | T | | | | | |
||||
* ------------------------------------------------------ |
||||
*/ |
||||
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & |
||||
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; |
||||
if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) { |
||||
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & |
||||
FSL_CORENET_DCFG_FUSESR_VID_MASK; |
||||
} |
||||
vdd_target = vdd[vid]; |
||||
|
||||
/* check override variable for overriding VDD */ |
||||
vdd_string = getenv(CONFIG_VID_FLS_ENV); |
||||
if (vdd_override == 0 && vdd_string && |
||||
!strict_strtoul(vdd_string, 10, &vdd_string_override)) |
||||
vdd_override = vdd_string_override; |
||||
if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) { |
||||
vdd_target = vdd_override * 10; /* convert to 1/10 mV */ |
||||
debug("VDD override is %lu\n", vdd_override); |
||||
} else if (vdd_override != 0) { |
||||
printf("Invalid value.\n"); |
||||
} |
||||
if (vdd_target == 0) { |
||||
debug("VID: VID not used\n"); |
||||
ret = 0; |
||||
goto exit; |
||||
} else { |
||||
/* divide and round up by 10 to get a value in mV */ |
||||
vdd_target = DIV_ROUND_UP(vdd_target, 10); |
||||
debug("VID: vid = %d mV\n", vdd_target); |
||||
} |
||||
|
||||
/*
|
||||
* Read voltage monitor to check real voltage. |
||||
*/ |
||||
vdd_last = read_voltage(i2caddress); |
||||
if (vdd_last < 0) { |
||||
printf("VID: Couldn't read sensor abort VID adjustment\n"); |
||||
ret = -1; |
||||
goto exit; |
||||
} |
||||
vdd_current = vdd_last; |
||||
debug("VID: Core voltage is currently at %d mV\n", vdd_last); |
||||
/*
|
||||
* Adjust voltage to at or one step above target. |
||||
* As measurements are less precise than setting the values |
||||
* we may run through dummy steps that cancel each other |
||||
* when stepping up and then down. |
||||
*/ |
||||
while (vdd_last > 0 && |
||||
vdd_last < vdd_target) { |
||||
vdd_current += IR_VDD_STEP_UP; |
||||
vdd_last = set_voltage(i2caddress, vdd_current); |
||||
} |
||||
while (vdd_last > 0 && |
||||
vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) { |
||||
vdd_current -= IR_VDD_STEP_DOWN; |
||||
vdd_last = set_voltage(i2caddress, vdd_current); |
||||
} |
||||
|
||||
if (vdd_last > 0) |
||||
printf("VID: Core voltage after adjustment is at %d mV\n", |
||||
vdd_last); |
||||
else |
||||
ret = -1; |
||||
exit: |
||||
if (re_enable) |
||||
enable_interrupts(); |
||||
return ret; |
||||
} |
||||
|
||||
static int print_vdd(void) |
||||
{ |
||||
int vdd_last, ret, i2caddress; |
||||
|
||||
ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR); |
||||
if (ret) { |
||||
debug("VID : I2c failed to switch channel\n"); |
||||
return -1; |
||||
} |
||||
ret = find_ir_chip_on_i2c(); |
||||
if (ret < 0) { |
||||
printf("VID: Could not find voltage regulator on I2C.\n"); |
||||
return -1; |
||||
} else { |
||||
i2caddress = ret; |
||||
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); |
||||
} |
||||
|
||||
/*
|
||||
* Read voltage monitor to check real voltage. |
||||
*/ |
||||
vdd_last = read_voltage(i2caddress); |
||||
if (vdd_last < 0) { |
||||
printf("VID: Couldn't read sensor abort VID adjustment\n"); |
||||
return -1; |
||||
} |
||||
printf("VID: Core voltage is at %d mV\n", vdd_last); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int do_vdd_override(cmd_tbl_t *cmdtp, |
||||
int flag, int argc, |
||||
char * const argv[]) |
||||
{ |
||||
ulong override; |
||||
|
||||
if (argc < 2) |
||||
return CMD_RET_USAGE; |
||||
|
||||
if (!strict_strtoul(argv[1], 10, &override)) |
||||
adjust_vdd(override); /* the value is checked by callee */ |
||||
else |
||||
return CMD_RET_USAGE; |
||||
return 0; |
||||
} |
||||
|
||||
static int do_vdd_read(cmd_tbl_t *cmdtp, |
||||
int flag, int argc, |
||||
char * const argv[]) |
||||
{ |
||||
if (argc < 1) |
||||
return CMD_RET_USAGE; |
||||
print_vdd(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
vdd_override, 2, 0, do_vdd_override, |
||||
"override VDD", |
||||
" - override with the voltage specified in mV, eg. 1050" |
||||
); |
||||
|
||||
U_BOOT_CMD( |
||||
vdd_read, 1, 0, do_vdd_read, |
||||
"read VDD", |
||||
" - Read the voltage specified in mV" |
||||
) |
||||
@ -0,0 +1,20 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __VID_H_ |
||||
#define __VID_H_ |
||||
|
||||
#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A |
||||
#define IR36021_LOOP1_VOUT_OFFSET 0x9A |
||||
#define IR36021_MFR_ID_OFFSET 0x92 |
||||
#define IR36021_MFR_ID 0x43 |
||||
|
||||
/* step the IR regulator in 5mV increments */ |
||||
#define IR_VDD_STEP_DOWN 5 |
||||
#define IR_VDD_STEP_UP 5 |
||||
int adjust_vdd(ulong vdd_override); |
||||
|
||||
#endif /* __VID_H_ */ |
||||
@ -0,0 +1,12 @@ |
||||
if TARGET_T102XQDS |
||||
|
||||
config SYS_BOARD |
||||
default "t102xqds" |
||||
|
||||
config SYS_VENDOR |
||||
default "freescale" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "T102xQDS" |
||||
|
||||
endif |
||||
@ -0,0 +1,12 @@ |
||||
T102XQDS BOARD |
||||
M: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
||||
S: Maintained |
||||
F: board/freescale/t102xqds/ |
||||
F: include/configs/T102xQDS.h |
||||
F: configs/T1024QDS_defconfig |
||||
F: configs/T1024QDS_NAND_defconfig |
||||
F: configs/T1024QDS_SDCARD_defconfig |
||||
F: configs/T1024QDS_SPIFLASH_defconfig |
||||
F: configs/T1024QDS_D4_defconfig |
||||
F: configs/T1024QDS_SECURE_BOOT_defconfig |
||||
F: configs/T1024QDS_D4_SECURE_BOOT_defconfig |
||||
@ -0,0 +1,17 @@ |
||||
#
|
||||
# Copyright 2014 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD |
||||
obj-y += spl.o
|
||||
else |
||||
obj-y += t102xqds.o
|
||||
obj-y += eth_t102xqds.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
|
||||
endif |
||||
obj-y += ddr.o
|
||||
obj-y += law.o
|
||||
obj-y += tlb.o
|
||||
@ -0,0 +1,328 @@ |
||||
T1024 SoC Overview |
||||
------------------ |
||||
The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor |
||||
combines two or one 64-bit Power Architecture e5500 core respectively with high |
||||
performance datapath acceleration logic, and network peripheral bus interfaces |
||||
required for networking and telecommunications. This processor can be used in |
||||
applications such as enterprise WLAN access points, routers, switches, firewall |
||||
and other packet processing intensive small enterprise and branch office appliances, |
||||
and general-purpose embedded computing. Its high level of integration offers |
||||
significant performance benefits and greatly helps to simplify board design. |
||||
|
||||
|
||||
The T1024 SoC includes the following function and features: |
||||
- two e5500 cores, each with a private 256 KB L2 cache |
||||
- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) |
||||
- Three levels of instructions: User, supervisor, and hypervisor |
||||
- Independent boot and reset |
||||
- Secure boot capability |
||||
- 256 KB shared L3 CoreNet platform cache (CPC) |
||||
- Interconnect CoreNet platform |
||||
- CoreNet coherency manager supporting coherent and noncoherent transactions |
||||
with prioritization and bandwidth allocation amongst CoreNet endpoints |
||||
- 150 Gbps coherent read bandwidth |
||||
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support |
||||
- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: |
||||
- Packet parsing, classification, and distribution |
||||
- Queue management for scheduling, packet sequencing, and congestion management |
||||
- Cryptography Acceleration (SEC 5.x) |
||||
- IEEE 1588 support |
||||
- Hardware buffer management for buffer allocation and deallocation |
||||
- MACSEC on DPAA-based Ethernet ports |
||||
- Ethernet interfaces |
||||
- Four 1 Gbps Ethernet controllers |
||||
- Parallel Ethernet interfaces |
||||
- Two RGMII interfaces |
||||
- High speed peripheral interfaces |
||||
- Three PCI Express 2.0 controllers/ports running at up to 5 GHz |
||||
- One SATA controller supporting 1.5 and 3.0 Gb/s operation |
||||
- One QSGMII interface |
||||
- Four SGMII interface supporting 1000 Mbps |
||||
- Three SGMII interfaces supporting up to 2500 Mbps |
||||
- 10GbE XFI or 10Base-KR interface |
||||
- Additional peripheral interfaces |
||||
- Two USB 2.0 controllers with integrated PHY |
||||
- SD/eSDHC/eMMC |
||||
- eSPI controller |
||||
- Four I2C controllers |
||||
- Four UARTs |
||||
- Four GPIO controllers |
||||
- Integrated flash controller (IFC) |
||||
- LCD interface (DIU) with 12 bit dual data rate |
||||
- Multicore programmable interrupt controller (PIC) |
||||
- Two 8-channel DMA engines |
||||
- Single source clocking implementation |
||||
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) |
||||
- QUICC Engine block |
||||
- 32-bit RISC controller for flexible support of the communications peripherals |
||||
- Serial DMA channel for receive and transmit on all serial channels |
||||
- Two universal communication controllers, supporting TDM, HDLC, and UART |
||||
|
||||
T1023 Personality |
||||
------------------ |
||||
T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and |
||||
unavailable deep sleep. Rest of the blocks are almost same as T1024. |
||||
Differences between T1024 and T1023 |
||||
Feature T1024 T1023 |
||||
QUICC Engine: yes no |
||||
DIU: yes no |
||||
Deep Sleep: yes no |
||||
I2C controller: 4 3 |
||||
DDR: 64-bit 32-bit |
||||
IFC: 32-bit 28-bit |
||||
|
||||
|
||||
T1024QDS board Overview |
||||
----------------------- |
||||
- SERDES Connections |
||||
4 lanes supporting the following: |
||||
- PCI Express: supports Gen 1 and Gen 2 |
||||
- SGMII 1G and SGMII 2.5G |
||||
- QSGMII |
||||
- XFI |
||||
- SATA 2.0 |
||||
- High-speed multiplexers route the SerDes traffic to appropriate slots or connectors. |
||||
- Aurora debug with dedicated connectors. |
||||
- DDR Controller |
||||
- Supports up to 1600 MTPS data-rate. |
||||
- Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card. |
||||
- Supports Single-, dual- or quad-rank DIMMs |
||||
- DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT. |
||||
- IFC/Local Bus |
||||
- NAND Flash: 8-bit, async, up to 2GB |
||||
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB |
||||
- NOR devices support 8 virtual banks |
||||
- Socketed to allow alternate devices |
||||
- GASIC: Simple (minimal) target within QIXIS FPGA |
||||
- PromJET rapid memory download support |
||||
- IFC Debug/Development card |
||||
- Ethernet |
||||
- Two on-board RGMII 10M/100M/1G ethernet ports. |
||||
- One QSGMII interface |
||||
- Four SGMII interface supporting 1Gbps |
||||
- Three SGMII interfaces supporting 2.5Gbps |
||||
- one 10Gbps XFI or 10Base-KR interface |
||||
- QIXIS System Logic FPGA |
||||
- Manages system power and reset sequencing. |
||||
- Manages the configurations of DUT, board, and clock for dynamic shmoo. |
||||
- Collects V-I-T data in background for code/power profiling. |
||||
- Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion). |
||||
- General fault monitoring and logging. |
||||
- Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off. |
||||
- Clocks |
||||
- System and DDR clock (SYSCLK, DDRCLK). |
||||
- Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz. |
||||
- Software programmable in 1 MHz increments from 1-200 MHz. |
||||
- SERDES clocks |
||||
- Provides clocks to SerDes blocks and slots. |
||||
- 100 MHz, 125 MHz and 156.25 MHz options. |
||||
- Spread-spectrum option for 100 MHz. |
||||
- Power Supplies |
||||
- Dedicated PMBus regulator for VDD and VDDC. |
||||
- Adjustable from 0.7V to 1.3V at 35A |
||||
- VDD can be disabled independanty from VDDC for “deep sleep”. |
||||
- DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A. |
||||
- VTT/MVREF automatically track operating voltage. |
||||
- Dedicated 2.5V VPP supply. |
||||
- Dedicated regulators/filters for AVDD supplies. |
||||
- Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD. |
||||
- Video |
||||
- DIU supports video up to 1280x1024x32 bpp. |
||||
- Chrontel CH7201 for HDMI connection. |
||||
- TI DS90C387R for direct LCD connection. |
||||
- Raw (not encoded) video connector for testing or other encoders. |
||||
- USB |
||||
- Supports two USB 2.0 ports with integrated PHYs. |
||||
- Two type A ports with 5V@1.5A per port. |
||||
- Second port can be converted to OTG mini-AB. |
||||
- SDHC |
||||
For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features: |
||||
- upport for optional clock feedback paths. |
||||
- Support for optional high-speed voltage translation direction controls. |
||||
- Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC. |
||||
- Support for eMMC memory devices. |
||||
- SPI |
||||
-On-board support of 3 different devices and sizes. |
||||
- Other IO |
||||
- Two Serial ports |
||||
- ProfiBus port |
||||
- Four I2C ports |
||||
|
||||
|
||||
Memory map on T1024QDS |
||||
---------------------- |
||||
Start Address End Address Description Size |
||||
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB |
||||
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB |
||||
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB |
||||
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB |
||||
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB |
||||
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB |
||||
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB |
||||
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB |
||||
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB |
||||
0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB |
||||
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB |
||||
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB |
||||
0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB |
||||
0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB |
||||
0x0_0000_0000 0x0_ffff_ffff DDR 4GB |
||||
|
||||
|
||||
128MB NOR Flash memory Map |
||||
-------------------------- |
||||
Start Address End Address Definition Max size |
||||
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB |
||||
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB |
||||
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB |
||||
0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB |
||||
0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB |
||||
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB |
||||
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB |
||||
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB |
||||
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB |
||||
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB |
||||
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB |
||||
0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB |
||||
0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB |
||||
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB |
||||
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB |
||||
0xE8000000 0xE801FFFF RCW (current bank) 128KB |
||||
|
||||
|
||||
SerDes clock vs DIP-switch settings |
||||
----------------------------------- |
||||
SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4] |
||||
0x6F 100MHz 125MHz 1101 |
||||
0xD6 100MHz 100MHz 1111 |
||||
0x99 156.25MHz 100MHz 1011 |
||||
|
||||
|
||||
T1024 Clock frequency |
||||
---------------------- |
||||
BIN Core DDR Platform FMan |
||||
Bin1: 1400MHz 1600MT/s 400MHz 700MHz |
||||
Bin2: 1200MHz 1600MT/s 400MHz 600MHz |
||||
Bin3: 1000MHz 1600MT/s 400MHz 500MHz |
||||
|
||||
|
||||
|
||||
Software configurations and board settings |
||||
------------------------------------------ |
||||
1. NOR boot: |
||||
a. build NOR boot image |
||||
$ make T1024QDS_defconfig (For DDR3L, by default) |
||||
or make T1024QDS_D4_defconfig (For DDR4) |
||||
$ make |
||||
b. program u-boot.bin image to NOR flash |
||||
=> tftp 1000000 u-boot.bin |
||||
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize |
||||
set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot |
||||
|
||||
Switching between default bank0 and alternate bank4 on NOR flash |
||||
To change boot source to vbank4: |
||||
via software: run command 'qixis_reset altbank' in u-boot. |
||||
via DIP-switch: set SW6[1:4] = '0100' |
||||
|
||||
To change boot source to vbank0: |
||||
via software: run command 'qixis_reset' in u-boot. |
||||
via DIP-Switch: set SW6[1:4] = '0000' |
||||
|
||||
2. NAND Boot: |
||||
a. build PBL image for NAND boot |
||||
$ make T1024QDS_NAND_defconfig |
||||
$ make |
||||
b. program u-boot-with-spl-pbl.bin to NAND flash |
||||
=> tftp 1000000 u-boot-with-spl-pbl.bin |
||||
=> nand erase 0 $filesize |
||||
=> nand write 1000000 0 $filesize |
||||
set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot |
||||
|
||||
3. SPI Boot: |
||||
a. build PBL image for SPI boot |
||||
$ make T1024QDS_SPIFLASH_defconfig |
||||
$ make |
||||
b. program u-boot-with-spl-pbl.bin to SPI flash |
||||
=> tftp 1000000 u-boot-with-spl-pbl.bin |
||||
=> sf probe 0 |
||||
=> sf erase 0 f0000 |
||||
=> sf write 1000000 0 $filesize |
||||
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot |
||||
|
||||
4. SD Boot: |
||||
a. build PBL image for SD boot |
||||
$ make T1024QDS_SDCARD_defconfig |
||||
$ make |
||||
b. program u-boot-with-spl-pbl.bin to SD/MMC card |
||||
=> tftp 1000000 u-boot-with-spl-pbl.bin |
||||
=> mmc write 1000000 8 0x800 |
||||
=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin |
||||
=> mmc write 1000000 0x820 80 |
||||
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot |
||||
|
||||
|
||||
DIU/QE-TDM/SDXC settings |
||||
------------------- |
||||
a) For TDM Riser: set pin_mux=tdm in hwconfig |
||||
b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig |
||||
c) For HDMI(DVI): set pin_mux=hdmi in hwconfig |
||||
d) For LCD(DFP): set pin_mux=lcd in hwconfig |
||||
e) For SDXC: set adaptor=sdxc in hwconfig |
||||
|
||||
2-stage NAND/SPI/SD boot loader |
||||
------------------------------- |
||||
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. |
||||
SPL further initializes DDR using SPD and environment variables |
||||
and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. |
||||
Finally SPL transers control to u-boot for futher booting. |
||||
|
||||
SPL has following features: |
||||
- Executes within 256K |
||||
- No relocation required |
||||
|
||||
Run time view of SPL framework |
||||
------------------------------------------------- |
||||
|Area | Address | |
||||
------------------------------------------------- |
||||
|SecureBoot header | 0xFFFC0000 (32KB) | |
||||
------------------------------------------------- |
||||
|GD, BD | 0xFFFC8000 (4KB) | |
||||
------------------------------------------------- |
||||
|ENV | 0xFFFC9000 (8KB) | |
||||
------------------------------------------------- |
||||
|HEAP | 0xFFFCB000 (30KB) | |
||||
------------------------------------------------- |
||||
|STACK | 0xFFFD8000 (22KB) | |
||||
------------------------------------------------- |
||||
|U-boot SPL | 0xFFFD8000 (160KB) | |
||||
------------------------------------------------- |
||||
|
||||
NAND Flash memory Map on T1024QDS |
||||
------------------------------------------------------------- |
||||
Start End Definition Size |
||||
0x000000 0x0FFFFF u-boot 1MB |
||||
0x100000 0x15FFFF u-boot env 8KB |
||||
0x160000 0x17FFFF FMAN Ucode 128KB |
||||
0x180000 0x19FFFF QE Firmware 128KB |
||||
|
||||
|
||||
SD Card memory Map on T1024QDS |
||||
---------------------------------------------------- |
||||
Block #blocks Definition Size |
||||
0x008 2048 u-boot img 1MB |
||||
0x800 0016 u-boot env 8KB |
||||
0x820 0256 FMAN Ucode 128KB |
||||
0x920 0256 QE Firmware 128KB |
||||
|
||||
|
||||
SPI Flash memory Map on T1024QDS |
||||
---------------------------------------------------- |
||||
Start End Definition Size |
||||
0x000000 0x0FFFFF u-boot img 1MB |
||||
0x100000 0x101FFF u-boot env 8KB |
||||
0x110000 0x12FFFF FMAN Ucode 128KB |
||||
0x130000 0x14FFFF QE Firmware 128KB |
||||
|
||||
|
||||
For more details, please refer to T1024QDS Reference Manual and access |
||||
website www.freescale.com and Freescale QorIQ SDK Infocenter document. |
||||
@ -0,0 +1,170 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <hwconfig.h> |
||||
#include <asm/mmu.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <fsl_ddr_dimm_params.h> |
||||
#include <asm/fsl_law.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
struct board_specific_parameters { |
||||
u32 n_ranks; |
||||
u32 datarate_mhz_high; |
||||
u32 rank_gb; |
||||
u32 clk_adjust; |
||||
u32 wrlvl_start; |
||||
u32 wrlvl_ctl_2; |
||||
u32 wrlvl_ctl_3; |
||||
}; |
||||
|
||||
/*
|
||||
* datarate_mhz_high values need to be in ascending order |
||||
*/ |
||||
static const struct board_specific_parameters udimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |
||||
*/ |
||||
#if defined(CONFIG_SYS_FSL_DDR4) |
||||
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, |
||||
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, |
||||
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, |
||||
{1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, |
||||
{1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, |
||||
#elif defined(CONFIG_SYS_FSL_DDR3) |
||||
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, |
||||
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, |
||||
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, |
||||
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, |
||||
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, |
||||
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, |
||||
#else |
||||
#error DDR type not defined |
||||
#endif |
||||
{} |
||||
}; |
||||
|
||||
static const struct board_specific_parameters *udimms[] = { |
||||
udimm0, |
||||
}; |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
||||
ulong ddr_freq; |
||||
struct cpu_type *cpu = gd->arch.cpu; |
||||
|
||||
if (ctrl_num > 2) { |
||||
printf("Not supported controller number %d\n", ctrl_num); |
||||
return; |
||||
} |
||||
if (!pdimm->n_ranks) |
||||
return; |
||||
|
||||
pbsp = udimms[0]; |
||||
|
||||
/* Get clk_adjust according to the board ddr freqency and n_banks
|
||||
* specified in board_specific_parameters table. |
||||
*/ |
||||
ddr_freq = get_ddr_freq(0) / 1000000; |
||||
while (pbsp->datarate_mhz_high) { |
||||
if (pbsp->n_ranks == pdimm->n_ranks && |
||||
(pdimm->rank_density >> 30) >= pbsp->rank_gb) { |
||||
if (ddr_freq <= pbsp->datarate_mhz_high) { |
||||
popts->clk_adjust = pbsp->clk_adjust; |
||||
popts->wrlvl_start = pbsp->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
goto found; |
||||
} |
||||
pbsp_highest = pbsp; |
||||
} |
||||
pbsp++; |
||||
} |
||||
|
||||
if (pbsp_highest) { |
||||
printf("Error: board specific timing not found\n"); |
||||
printf("for data rate %lu MT/s\n", ddr_freq); |
||||
printf("Trying to use the highest speed (%u) parameters\n", |
||||
pbsp_highest->datarate_mhz_high); |
||||
popts->clk_adjust = pbsp_highest->clk_adjust; |
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
} else { |
||||
panic("DIMM is not supported by this board"); |
||||
} |
||||
found: |
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", |
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); |
||||
debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", |
||||
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); |
||||
debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); |
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable: |
||||
* - number of DIMMs installed |
||||
*/ |
||||
popts->half_strength_driver_enable = 1; |
||||
/*
|
||||
* Write leveling override |
||||
*/ |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
|
||||
/*
|
||||
* rtt and rtt_wr override |
||||
*/ |
||||
popts->rtt_override = 0; |
||||
|
||||
/* Enable ZQ calibration */ |
||||
popts->zq_en = 1; |
||||
|
||||
/* DHC_EN =1, ODT = 75 Ohm */ |
||||
#ifdef CONFIG_SYS_FSL_DDR4 |
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); |
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | |
||||
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ |
||||
#else |
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); |
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); |
||||
#endif |
||||
|
||||
/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
|
||||
* set DDR bus width to 32bit for T1023 |
||||
*/ |
||||
if (cpu->soc_ver == SVR_T1023) |
||||
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; |
||||
|
||||
#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 |
||||
/* for DDR bus 32bit test on T1024 */ |
||||
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; |
||||
#endif |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
phys_size_t dram_size; |
||||
|
||||
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) |
||||
puts("Initializing....using SPD\n"); |
||||
|
||||
dram_size = fsl_ddr_sdram(); |
||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
||||
dram_size *= 0x100000; |
||||
#else |
||||
/* DDR has been initialised by first stage boot loader */ |
||||
dram_size = fsl_ddr_sdram_size(); |
||||
#endif |
||||
return dram_size; |
||||
} |
||||
@ -0,0 +1,442 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* Shengzhou Liu <Shengzhou.Liu@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <netdev.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <malloc.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_mdio.h> |
||||
#include <miiphy.h> |
||||
#include <phy.h> |
||||
#include <asm/fsl_dtsec.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include "../common/qixis.h" |
||||
#include "../common/fman.h" |
||||
#include "t102xqds_qixis.h" |
||||
|
||||
#define EMI_NONE 0xFFFFFFFF |
||||
#define EMI1_RGMII1 0 |
||||
#define EMI1_RGMII2 1 |
||||
#define EMI1_SLOT1 2 |
||||
#define EMI1_SLOT2 3 |
||||
#define EMI1_SLOT3 4 |
||||
#define EMI1_SLOT4 5 |
||||
#define EMI1_SLOT5 6 |
||||
#define EMI2 7 |
||||
|
||||
static int mdio_mux[NUM_FM_PORTS]; |
||||
|
||||
static const char * const mdio_names[] = { |
||||
"T1024QDS_MDIO_RGMII1", |
||||
"T1024QDS_MDIO_RGMII2", |
||||
"T1024QDS_MDIO_SLOT1", |
||||
"T1024QDS_MDIO_SLOT2", |
||||
"T1024QDS_MDIO_SLOT3", |
||||
"T1024QDS_MDIO_SLOT4", |
||||
"T1024QDS_MDIO_SLOT5", |
||||
"T1024QDS_MDIO_10GC", |
||||
"NULL", |
||||
}; |
||||
|
||||
/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ |
||||
static u8 lane_to_slot[] = {2, 3, 4, 5}; |
||||
|
||||
static const char *t1024qds_mdio_name_for_muxval(u8 muxval) |
||||
{ |
||||
return mdio_names[muxval]; |
||||
} |
||||
|
||||
struct mii_dev *mii_dev_for_muxval(u8 muxval) |
||||
{ |
||||
struct mii_dev *bus; |
||||
const char *name; |
||||
|
||||
if (muxval > EMI2) |
||||
return NULL; |
||||
|
||||
name = t1024qds_mdio_name_for_muxval(muxval); |
||||
|
||||
if (!name) { |
||||
printf("No bus for muxval %x\n", muxval); |
||||
return NULL; |
||||
} |
||||
|
||||
bus = miiphy_get_dev_by_name(name); |
||||
|
||||
if (!bus) { |
||||
printf("No bus by name %s\n", name); |
||||
return NULL; |
||||
} |
||||
|
||||
return bus; |
||||
} |
||||
|
||||
struct t1024qds_mdio { |
||||
u8 muxval; |
||||
struct mii_dev *realbus; |
||||
}; |
||||
|
||||
static void t1024qds_mux_mdio(u8 muxval) |
||||
{ |
||||
u8 brdcfg4; |
||||
|
||||
if (muxval < 7) { |
||||
brdcfg4 = QIXIS_READ(brdcfg[4]); |
||||
brdcfg4 &= ~BRDCFG4_EMISEL_MASK; |
||||
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); |
||||
QIXIS_WRITE(brdcfg[4], brdcfg4); |
||||
} |
||||
} |
||||
|
||||
static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad, |
||||
int regnum) |
||||
{ |
||||
struct t1024qds_mdio *priv = bus->priv; |
||||
|
||||
t1024qds_mux_mdio(priv->muxval); |
||||
|
||||
return priv->realbus->read(priv->realbus, addr, devad, regnum); |
||||
} |
||||
|
||||
static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad, |
||||
int regnum, u16 value) |
||||
{ |
||||
struct t1024qds_mdio *priv = bus->priv; |
||||
|
||||
t1024qds_mux_mdio(priv->muxval); |
||||
|
||||
return priv->realbus->write(priv->realbus, addr, devad, regnum, value); |
||||
} |
||||
|
||||
static int t1024qds_mdio_reset(struct mii_dev *bus) |
||||
{ |
||||
struct t1024qds_mdio *priv = bus->priv; |
||||
|
||||
return priv->realbus->reset(priv->realbus); |
||||
} |
||||
|
||||
static int t1024qds_mdio_init(char *realbusname, u8 muxval) |
||||
{ |
||||
struct t1024qds_mdio *pmdio; |
||||
struct mii_dev *bus = mdio_alloc(); |
||||
|
||||
if (!bus) { |
||||
printf("Failed to allocate t1024qds MDIO bus\n"); |
||||
return -1; |
||||
} |
||||
|
||||
pmdio = malloc(sizeof(*pmdio)); |
||||
if (!pmdio) { |
||||
printf("Failed to allocate t1024qds private data\n"); |
||||
free(bus); |
||||
return -1; |
||||
} |
||||
|
||||
bus->read = t1024qds_mdio_read; |
||||
bus->write = t1024qds_mdio_write; |
||||
bus->reset = t1024qds_mdio_reset; |
||||
sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval)); |
||||
|
||||
pmdio->realbus = miiphy_get_dev_by_name(realbusname); |
||||
|
||||
if (!pmdio->realbus) { |
||||
printf("No bus with name %s\n", realbusname); |
||||
free(bus); |
||||
free(pmdio); |
||||
return -1; |
||||
} |
||||
|
||||
pmdio->muxval = muxval; |
||||
bus->priv = pmdio; |
||||
return mdio_register(bus); |
||||
} |
||||
|
||||
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, |
||||
enum fm_port port, int offset) |
||||
{ |
||||
struct fixed_link f_link; |
||||
|
||||
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) { |
||||
if (port == FM1_DTSEC3) { |
||||
fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2"); |
||||
fdt_setprop(fdt, offset, "phy-connection-type", |
||||
"rgmii", 5); |
||||
fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); |
||||
} |
||||
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { |
||||
if (port == FM1_DTSEC1) { |
||||
fdt_set_phy_handle(fdt, compat, addr, |
||||
"sgmii_vsc8234_phy_s5"); |
||||
} else if (port == FM1_DTSEC2) { |
||||
fdt_set_phy_handle(fdt, compat, addr, |
||||
"sgmii_vsc8234_phy_s4"); |
||||
} |
||||
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { |
||||
if (port == FM1_DTSEC3) { |
||||
fdt_set_phy_handle(fdt, compat, addr, |
||||
"sgmii_aqr105_phy_s3"); |
||||
} |
||||
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { |
||||
switch (port) { |
||||
case FM1_DTSEC1: |
||||
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1"); |
||||
break; |
||||
case FM1_DTSEC2: |
||||
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2"); |
||||
break; |
||||
case FM1_DTSEC3: |
||||
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3"); |
||||
break; |
||||
case FM1_DTSEC4: |
||||
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4"); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
fdt_delprop(fdt, offset, "phy-connection-type"); |
||||
fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6); |
||||
fdt_status_okay_by_alias(fdt, "emi1_slot2"); |
||||
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { |
||||
/* XFI interface */ |
||||
f_link.phy_id = port; |
||||
f_link.duplex = 1; |
||||
f_link.link_speed = 10000; |
||||
f_link.pause = 0; |
||||
f_link.asym_pause = 0; |
||||
/* no PHY for XFI */ |
||||
fdt_delprop(fdt, offset, "phy-handle"); |
||||
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); |
||||
fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5); |
||||
} |
||||
} |
||||
|
||||
void fdt_fixup_board_enet(void *fdt) |
||||
{ |
||||
} |
||||
|
||||
/*
|
||||
* This function reads RCW to check if Serdes1{A:D} is configured |
||||
* to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly |
||||
*/ |
||||
static void initialize_lane_to_slot(void) |
||||
{ |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
|
||||
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
switch (srds_s1) { |
||||
case 0x46: |
||||
case 0x47: |
||||
lane_to_slot[1] = 2; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#if defined(CONFIG_FMAN_ENET) |
||||
int i, idx, lane, slot, interface; |
||||
struct memac_mdio_info dtsec_mdio_info; |
||||
struct memac_mdio_info tgec_mdio_info; |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_s1; |
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
initialize_lane_to_slot(); |
||||
|
||||
/* Initialize the mdio_mux array so we can recognize empty elements */ |
||||
for (i = 0; i < NUM_FM_PORTS; i++) |
||||
mdio_mux[i] = EMI_NONE; |
||||
|
||||
dtsec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; |
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
||||
|
||||
/* Register the 1G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info); |
||||
|
||||
tgec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; |
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; |
||||
|
||||
/* Register the 10G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &tgec_mdio_info); |
||||
|
||||
/* Register the muxing front-ends to the MDIO buses */ |
||||
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); |
||||
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); |
||||
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); |
||||
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); |
||||
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); |
||||
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); |
||||
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); |
||||
t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); |
||||
|
||||
/* Set the two on-board RGMII PHY address */ |
||||
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); |
||||
|
||||
switch (srds_s1) { |
||||
case 0xd5: |
||||
case 0xd6: |
||||
/* QSGMII in Slot2 */ |
||||
fm_info_set_phy_address(FM1_DTSEC1, 0x8); |
||||
fm_info_set_phy_address(FM1_DTSEC2, 0x9); |
||||
fm_info_set_phy_address(FM1_DTSEC3, 0xa); |
||||
fm_info_set_phy_address(FM1_DTSEC4, 0xb); |
||||
break; |
||||
case 0x95: |
||||
case 0x99: |
||||
/*
|
||||
* XFI does not need a PHY to work, but to avoid U-boot use |
||||
* default PHY address which is zero to a MAC when it found |
||||
* a MAC has no PHY address, we give a PHY address to XFI |
||||
* MAC, and should not use a real XAUI PHY address, since |
||||
* MDIO can access it successfully, and then MDIO thinks the |
||||
* XAUI card is used for the XFI MAC, which will cause error. |
||||
*/ |
||||
fm_info_set_phy_address(FM1_10GEC1, 4); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); |
||||
break; |
||||
case 0x6f: |
||||
/* SGMII in Slot3, Slot4, Slot5 */ |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); |
||||
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); |
||||
break; |
||||
case 0x7f: |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); |
||||
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); |
||||
break; |
||||
case 0x47: |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); |
||||
break; |
||||
case 0x77: |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); |
||||
break; |
||||
case 0x5a: |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); |
||||
break; |
||||
case 0x6a: |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); |
||||
break; |
||||
case 0x5b: |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); |
||||
break; |
||||
case 0x6b: |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
||||
idx = i - FM1_DTSEC1; |
||||
interface = fm_info_get_enet_if(i); |
||||
switch (interface) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
case PHY_INTERFACE_MODE_SGMII_2500: |
||||
case PHY_INTERFACE_MODE_QSGMII: |
||||
if (interface == PHY_INTERFACE_MODE_SGMII) { |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
SGMII_FM1_DTSEC1 + idx); |
||||
} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
SGMII_2500_FM1_DTSEC1 + idx); |
||||
} else { |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
QSGMII_FM1_A); |
||||
} |
||||
|
||||
if (lane < 0) |
||||
break; |
||||
|
||||
slot = lane_to_slot[lane]; |
||||
debug("FM1@DTSEC%u expects SGMII in slot %u\n", |
||||
idx + 1, slot); |
||||
if (QIXIS_READ(present2) & (1 << (slot - 1))) |
||||
fm_disable_port(i); |
||||
|
||||
switch (slot) { |
||||
case 2: |
||||
mdio_mux[i] = EMI1_SLOT2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
case 3: |
||||
mdio_mux[i] = EMI1_SLOT3; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
case 4: |
||||
mdio_mux[i] = EMI1_SLOT4; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
case 5: |
||||
mdio_mux[i] = EMI1_SLOT5; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval( |
||||
mdio_mux[i])); |
||||
break; |
||||
} |
||||
break; |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
if (i == FM1_DTSEC3) |
||||
mdio_mux[i] = EMI1_RGMII2; |
||||
else if (i == FM1_DTSEC4) |
||||
mdio_mux[i] = EMI1_RGMII1; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { |
||||
idx = i - FM1_10GEC1; |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_XGMII: |
||||
lane = serdes_get_first_lane(FSL_SRDS_1, |
||||
XFI_FM1_MAC1 + idx); |
||||
if (lane < 0) |
||||
break; |
||||
mdio_mux[i] = EMI2; |
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
cpu_eth_init(bis); |
||||
#endif /* CONFIG_FMAN_ENET */ |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
||||
@ -0,0 +1,32 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SYS_NO_FLASH |
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), |
||||
#endif |
||||
#ifdef QIXIS_BASE_PHYS |
||||
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS |
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,23 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <pci.h> |
||||
#include <asm/fsl_pci.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
fsl_pcie_init_board(0); |
||||
} |
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd) |
||||
{ |
||||
FT_FSL_PCI_SETUP; |
||||
} |
||||
@ -0,0 +1,151 @@ |
||||
/* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <ns16550.h> |
||||
#include <nand.h> |
||||
#include <i2c.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <spi_flash.h> |
||||
#include "../common/qixis.h" |
||||
#include "t102xqds_qixis.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
phys_size_t get_effective_memsize(void) |
||||
{ |
||||
return CONFIG_SYS_L3_SIZE; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch (sysclk_conf & 0x0F) { |
||||
case QIXIS_SYSCLK_83: |
||||
return 83333333; |
||||
case QIXIS_SYSCLK_100: |
||||
return 100000000; |
||||
case QIXIS_SYSCLK_125: |
||||
return 125000000; |
||||
case QIXIS_SYSCLK_133: |
||||
return 133333333; |
||||
case QIXIS_SYSCLK_150: |
||||
return 150000000; |
||||
case QIXIS_SYSCLK_160: |
||||
return 160000000; |
||||
case QIXIS_SYSCLK_166: |
||||
return 166666666; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch ((ddrclk_conf & 0x30) >> 4) { |
||||
case QIXIS_DDRCLK_100: |
||||
return 100000000; |
||||
case QIXIS_DDRCLK_125: |
||||
return 125000000; |
||||
case QIXIS_DDRCLK_133: |
||||
return 133333333; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio, sys_clk, ccb_clk; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT) |
||||
/*
|
||||
* There is T1040 SoC issue where NOR, FPGA are inaccessible during |
||||
* NAND boot because IFC signals > IFC_AD7 are not enabled. |
||||
* This workaround changes RCW source to make all signals enabled. |
||||
*/ |
||||
u32 porsr1, pinctl; |
||||
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 |
||||
|
||||
porsr1 = in_be32(&gur->porsr1); |
||||
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); |
||||
out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); |
||||
#endif |
||||
|
||||
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ |
||||
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); |
||||
|
||||
/* Update GD pointer */ |
||||
gd = (gd_t *)(CONFIG_SPL_GD_ADDR); |
||||
|
||||
console_init_f(); |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
sys_clk = get_board_sys_clk(); |
||||
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; |
||||
ccb_clk = sys_clk * plat_ratio / 2; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
ccb_clk / 16 / CONFIG_BAUDRATE); |
||||
|
||||
#if defined(CONFIG_SPL_MMC_BOOT) |
||||
puts("\nSD boot...\n"); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
puts("\nSPI boot...\n"); |
||||
#elif defined(CONFIG_SPL_NAND_BOOT) |
||||
puts("\nNAND boot...\n"); |
||||
#endif |
||||
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
bd_t *bd; |
||||
|
||||
bd = (bd_t *)(gd + sizeof(gd_t)); |
||||
memset(bd, 0, sizeof(bd_t)); |
||||
gd->bd = bd; |
||||
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; |
||||
bd->bi_memsize = CONFIG_SYS_L3_SIZE; |
||||
|
||||
probecpu(); |
||||
get_clocks(); |
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, |
||||
CONFIG_SPL_RELOC_MALLOC_SIZE); |
||||
|
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_initialize(bd); |
||||
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_SPI_BOOT |
||||
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
|
||||
gd->env_addr = (ulong)(CONFIG_ENV_ADDR); |
||||
gd->env_valid = 1; |
||||
|
||||
i2c_init_all(); |
||||
|
||||
gd->ram_size = initdram(0); |
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_boot(); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
spi_boot(); |
||||
#elif defined(CONFIG_SPL_NAND_BOOT) |
||||
nand_boot(); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,26 @@ |
||||
#PBI commands |
||||
#Initialize CPC1 |
||||
09010000 00200400 |
||||
09138000 00000000 |
||||
091380c0 00000100 |
||||
#Configure CPC1 as 256KB SRAM |
||||
09010100 00000000 |
||||
09010104 fffc0007 |
||||
09010f00 08000000 |
||||
09010000 80000000 |
||||
#Configure LAW for CPC1 |
||||
09000cd0 00000000 |
||||
09000cd4 fffc0000 |
||||
09000cd8 81000011 |
||||
#Configure alternate space |
||||
09000010 00000000 |
||||
09000014 ff000000 |
||||
09000018 81000000 |
||||
#Configure SPI controller |
||||
09110000 80000403 |
||||
09110020 2d170008 |
||||
09110024 00100008 |
||||
09110028 00100008 |
||||
0911002c 00100008 |
||||
#Flush PBL data |
||||
091380c0 000FFFFF |
||||
@ -0,0 +1,10 @@ |
||||
# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz |
||||
# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz |
||||
|
||||
# PBL preamble and RCW header for T1024QDS |
||||
aa55aa55 010e0100 |
||||
# Serdes protocol 0x6F |
||||
0810000e 00000000 00000000 00000000 |
||||
37800001 00000012 e8104000 21000000 |
||||
00000000 00000000 00000000 00030810 |
||||
00000000 036c5a00 00000000 00000006 |
||||
@ -0,0 +1,408 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <i2c.h> |
||||
#include <netdev.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <fm_eth.h> |
||||
#include <hwconfig.h> |
||||
#include <asm/mpc85xx_gpio.h> |
||||
#include "../common/qixis.h" |
||||
#include "t102xqds.h" |
||||
#include "t102xqds_qixis.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
char buf[64]; |
||||
struct cpu_type *cpu = gd->arch.cpu; |
||||
static const char *const freq[] = {"100", "125", "156.25", "100.0"}; |
||||
int clock; |
||||
u8 sw = QIXIS_READ(arch); |
||||
|
||||
printf("Board: %sQDS, ", cpu->name); |
||||
printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); |
||||
printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); |
||||
|
||||
#ifdef CONFIG_SDCARD |
||||
puts("SD/MMC\n"); |
||||
#elif CONFIG_SPIFLASH |
||||
puts("SPI\n"); |
||||
#else |
||||
sw = QIXIS_READ(brdcfg[0]); |
||||
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; |
||||
|
||||
if (sw < 0x8) |
||||
printf("vBank: %d\n", sw); |
||||
else if (sw == 0x8) |
||||
puts("PromJet\n"); |
||||
else if (sw == 0x9) |
||||
puts("NAND\n"); |
||||
else if (sw == 0x15) |
||||
printf("IFC Card\n"); |
||||
else |
||||
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); |
||||
#endif |
||||
|
||||
printf("FPGA: v%d (%s), build %d", |
||||
(int)QIXIS_READ(scver), qixis_read_tag(buf), |
||||
(int)qixis_read_minor()); |
||||
/* the timestamp string contains "\n" at the end */ |
||||
printf(" on %s", qixis_read_time(buf)); |
||||
|
||||
puts("SERDES Reference: "); |
||||
sw = QIXIS_READ(brdcfg[2]); |
||||
clock = (sw >> 6) & 3; |
||||
printf("Clock1=%sMHz ", freq[clock]); |
||||
clock = (sw >> 4) & 3; |
||||
printf("Clock2=%sMHz\n", freq[clock]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int select_i2c_ch_pca9547(u8 ch) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
||||
if (ret) { |
||||
puts("PCA: failed to select proper channel\n"); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int board_mux_lane_to_slot(void) |
||||
{ |
||||
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_prtcl_s1; |
||||
u8 brdcfg9; |
||||
|
||||
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
|
||||
brdcfg9 = QIXIS_READ(brdcfg[9]); |
||||
QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE); |
||||
|
||||
switch (srds_prtcl_s1) { |
||||
case 0: |
||||
/* SerDes1 is not enabled */ |
||||
break; |
||||
case 0xd5: |
||||
case 0x5b: |
||||
case 0x6b: |
||||
case 0x77: |
||||
case 0x6f: |
||||
case 0x7f: |
||||
QIXIS_WRITE(brdcfg[12], 0x8c); |
||||
break; |
||||
case 0x40: |
||||
QIXIS_WRITE(brdcfg[12], 0xfc); |
||||
break; |
||||
case 0xd6: |
||||
case 0x5a: |
||||
case 0x6a: |
||||
case 0x56: |
||||
QIXIS_WRITE(brdcfg[12], 0x88); |
||||
break; |
||||
case 0x47: |
||||
QIXIS_WRITE(brdcfg[12], 0xcc); |
||||
break; |
||||
case 0x46: |
||||
QIXIS_WRITE(brdcfg[12], 0xc8); |
||||
break; |
||||
case 0x95: |
||||
case 0x99: |
||||
brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE; |
||||
QIXIS_WRITE(brdcfg[9], brdcfg9); |
||||
QIXIS_WRITE(brdcfg[12], 0x8c); |
||||
break; |
||||
case 0x116: |
||||
QIXIS_WRITE(brdcfg[12], 0x00); |
||||
break; |
||||
case 0x115: |
||||
case 0x119: |
||||
case 0x129: |
||||
case 0x12b: |
||||
/* Aurora, PCIe, SGMII, SATA */ |
||||
QIXIS_WRITE(brdcfg[12], 0x04); |
||||
break; |
||||
default: |
||||
printf("WARNING: unsupported for SerDes Protocol %d\n", |
||||
srds_prtcl_s1); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_PPC_T1024 |
||||
static void board_mux_setup(void) |
||||
{ |
||||
u8 brdcfg15; |
||||
|
||||
brdcfg15 = QIXIS_READ(brdcfg[15]); |
||||
brdcfg15 &= ~BRDCFG15_DIUSEL_MASK; |
||||
|
||||
if (hwconfig_arg_cmp("pin_mux", "tdm")) { |
||||
/* Route QE_TDM multiplexed signals to TDM Riser slot */ |
||||
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM); |
||||
QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2); |
||||
QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & |
||||
~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM); |
||||
} else if (hwconfig_arg_cmp("pin_mux", "ucc")) { |
||||
/* to UCC (ProfiBus) interface */ |
||||
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC); |
||||
} else if (hwconfig_arg_cmp("pin_mux", "hdmi")) { |
||||
/* to DVI (HDMI) encoder */ |
||||
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI); |
||||
} else if (hwconfig_arg_cmp("pin_mux", "lcd")) { |
||||
/* to DFP (LCD) encoder */ |
||||
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM | |
||||
BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD); |
||||
} |
||||
|
||||
if (hwconfig_arg_cmp("adaptor", "sdxc")) |
||||
/* Route SPI_CS multiplexed signals to SD slot */ |
||||
QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & |
||||
~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC); |
||||
} |
||||
#endif |
||||
|
||||
void board_retimer_ds125df111_init(void) |
||||
{ |
||||
u8 reg; |
||||
|
||||
/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ |
||||
reg = I2C_MUX_CH7; |
||||
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); |
||||
reg = I2C_MUX_CH5; |
||||
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); |
||||
|
||||
/* Access to Control/Shared register */ |
||||
reg = 0x0; |
||||
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); |
||||
|
||||
/* Read device revision and ID */ |
||||
i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); |
||||
debug("Retimer version id = 0x%x\n", reg); |
||||
|
||||
/* Enable Broadcast */ |
||||
reg = 0x0c; |
||||
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); |
||||
|
||||
/* Reset Channel Registers */ |
||||
i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); |
||||
reg |= 0x4; |
||||
i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); |
||||
|
||||
/* Enable override divider select and Enable Override Output Mux */ |
||||
i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); |
||||
reg |= 0x24; |
||||
i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); |
||||
|
||||
/* Select VCO Divider to full rate (000) */ |
||||
i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); |
||||
reg &= 0x8f; |
||||
i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); |
||||
|
||||
/* Select active PFD MUX input as re-timed data (001) */ |
||||
i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); |
||||
reg &= 0x3f; |
||||
reg |= 0x20; |
||||
i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); |
||||
|
||||
/* Set data rate as 10.3125 Gbps */ |
||||
reg = 0x0; |
||||
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); |
||||
reg = 0xb2; |
||||
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); |
||||
reg = 0x90; |
||||
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); |
||||
reg = 0xb3; |
||||
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); |
||||
reg = 0xcd; |
||||
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); |
||||
} |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_SYS_FLASH_BASE |
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
||||
int flash_esel = find_tlb_idx((void *)flashbase, 1); |
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited |
||||
* so that flash can be erased properly. |
||||
*/ |
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||
flush_dcache(); |
||||
invalidate_icache(); |
||||
|
||||
if (flash_esel == -1) { |
||||
/* very unlikely unless something is messed up */ |
||||
puts("Error: Could not find TLB for FLASH BASE\n"); |
||||
flash_esel = 2; /* give our best effort to continue */ |
||||
} else { |
||||
/* invalidate existing TLB entry for flash + promjet */ |
||||
disable_tlb(flash_esel); |
||||
} |
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1); |
||||
#endif |
||||
set_liodns(); |
||||
#ifdef CONFIG_SYS_DPAA_QBMAN |
||||
setup_portals(); |
||||
#endif |
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); |
||||
board_mux_lane_to_slot(); |
||||
board_retimer_ds125df111_init(); |
||||
|
||||
/* Increase IO drive strength to address FCS error on RGMII */ |
||||
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch (sysclk_conf & 0x0F) { |
||||
case QIXIS_SYSCLK_64: |
||||
return 64000000; |
||||
case QIXIS_SYSCLK_83: |
||||
return 83333333; |
||||
case QIXIS_SYSCLK_100: |
||||
return 100000000; |
||||
case QIXIS_SYSCLK_125: |
||||
return 125000000; |
||||
case QIXIS_SYSCLK_133: |
||||
return 133333333; |
||||
case QIXIS_SYSCLK_150: |
||||
return 150000000; |
||||
case QIXIS_SYSCLK_160: |
||||
return 160000000; |
||||
case QIXIS_SYSCLK_166: |
||||
return 166666666; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); |
||||
|
||||
switch ((ddrclk_conf & 0x30) >> 4) { |
||||
case QIXIS_DDRCLK_100: |
||||
return 100000000; |
||||
case QIXIS_DDRCLK_125: |
||||
return 125000000; |
||||
case QIXIS_DDRCLK_133: |
||||
return 133333333; |
||||
} |
||||
return 66666666; |
||||
} |
||||
|
||||
#define NUM_SRDS_PLL 2 |
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_PPC_T1024 |
||||
board_mux_setup(); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
void fdt_fixup_spi_mux(void *blob) |
||||
{ |
||||
int nodeoff = 0; |
||||
|
||||
if (hwconfig_arg_cmp("pin_mux", "tdm")) { |
||||
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, |
||||
"eon,en25s64")) >= 0) { |
||||
fdt_del_node(blob, nodeoff); |
||||
} |
||||
} else { |
||||
/* remove tdm node */ |
||||
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, |
||||
"maxim,ds26522")) >= 0) { |
||||
fdt_del_node(blob, nodeoff); |
||||
} |
||||
} |
||||
} |
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
#ifdef CONFIG_PCI |
||||
pci_of_setup(blob, bd); |
||||
#endif |
||||
|
||||
fdt_fixup_liodn(blob); |
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
fdt_fixup_fman_ethernet(blob); |
||||
fdt_fixup_board_enet(blob); |
||||
#endif |
||||
fdt_fixup_spi_mux(blob); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void qixis_dump_switch(void) |
||||
{ |
||||
int i, nr_of_cfgsw; |
||||
|
||||
QIXIS_WRITE(cms[0], 0x00); |
||||
nr_of_cfgsw = QIXIS_READ(cms[1]); |
||||
|
||||
puts("DIP switch settings dump:\n"); |
||||
for (i = 1; i <= nr_of_cfgsw; i++) { |
||||
QIXIS_WRITE(cms[0], i); |
||||
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); |
||||
} |
||||
} |
||||
|
||||
#ifdef CONFIG_DEEP_SLEEP |
||||
void board_mem_sleep_setup(void) |
||||
{ |
||||
/* does not provide HW signals for power management */ |
||||
QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); |
||||
/* Disable MCKE isolation */ |
||||
gpio_set_value(2, 0); |
||||
udelay(1); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,14 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __T102x_QDS_H__ |
||||
#define __T102x_QDS_H__ |
||||
|
||||
void fdt_fixup_board_enet(void *blob); |
||||
void pci_of_setup(void *blob, bd_t *bd); |
||||
int select_i2c_ch_pca9547(u8 ch); |
||||
|
||||
#endif |
||||
@ -0,0 +1,64 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __T1024QDS_QIXIS_H__ |
||||
#define __T1024QDS_QIXIS_H__ |
||||
|
||||
/* Definitions of QIXIS Registers for T1024/T1023 QDS */ |
||||
|
||||
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ |
||||
#define BRDCFG4_EMISEL_MASK 0xE0 |
||||
#define BRDCFG4_EMISEL_SHIFT 5 |
||||
|
||||
/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ |
||||
#define BRDCFG5_IMX_MASK 0xC0 |
||||
#define BRDCFG5_IMX_DIU 0x80 |
||||
|
||||
#define BRDCFG5_SPIRTE_MASK 0x07 |
||||
#define BRDCFG5_SPIRTE_TDM 0x01 |
||||
#define BRDCFG5_SPIRTE_SDHC 0x02 |
||||
#define BRDCFG9_XFI_TX_DISABLE 0x10 |
||||
|
||||
/* BRDCFG13[0:5] TDM configuration and setup */ |
||||
#define BRDCFG13_TDM_MASK 0xfc |
||||
#define BRDCFG13_TDM_INTERFACE 0x37 |
||||
#define BRDCFG13_HDLC_LOOPBACK 0x29 |
||||
#define BRDCFG13_TDM_LOOPBACK 0x31 |
||||
|
||||
/* BRDCFG15[3] controls LCD Panel Powerdown */ |
||||
#define BRDCFG15_LCDFM 0x20 |
||||
#define BRDCFG15_LCDPD 0x10 |
||||
#define BRDCFG15_LCDPD_MASK 0x10 |
||||
#define BRDCFG15_LCDPD_ENABLED 0x00 |
||||
|
||||
/* BRDCFG15[6:7] controls DIU MUX selction*/ |
||||
#define BRDCFG15_DIUSEL_MASK 0x03 |
||||
#define BRDCFG15_DIUSEL_HDMI 0x00 |
||||
#define BRDCFG15_DIUSEL_LCD 0x01 |
||||
#define BRDCFG15_DIUSEL_UCC 0x02 |
||||
#define BRDCFG15_DIUSEL_TDM 0x03 |
||||
|
||||
/* SYSCLK */ |
||||
#define QIXIS_SYSCLK_66 0x0 |
||||
#define QIXIS_SYSCLK_83 0x1 |
||||
#define QIXIS_SYSCLK_100 0x2 |
||||
#define QIXIS_SYSCLK_125 0x3 |
||||
#define QIXIS_SYSCLK_133 0x4 |
||||
#define QIXIS_SYSCLK_150 0x5 |
||||
#define QIXIS_SYSCLK_160 0x6 |
||||
#define QIXIS_SYSCLK_166 0x7 |
||||
#define QIXIS_SYSCLK_64 0x8 |
||||
|
||||
/* DDRCLK */ |
||||
#define QIXIS_DDRCLK_66 0x0 |
||||
#define QIXIS_DDRCLK_100 0x1 |
||||
#define QIXIS_DDRCLK_125 0x2 |
||||
#define QIXIS_DDRCLK_133 0x3 |
||||
|
||||
|
||||
#define QIXIS_SRDS1CLK_122 0x5a |
||||
#define QIXIS_SRDS1CLK_125 0x5e |
||||
#endif |
||||
@ -0,0 +1,117 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 */ |
||||
/* *I*** - Covers boot page */ |
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) |
||||
/*
|
||||
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the |
||||
* SRAM is at 0xfffc0000, it covered the 0xfffff000. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_256K, 1), |
||||
#else |
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_4K, 1), |
||||
#endif |
||||
|
||||
/* *I*G* - CCSRBAR */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/* *I*G* - Flash, localbus */ |
||||
/* This will be changed to *I*G* after relocation to RAM. */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/* *I*G* - PCI I/O */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256K, 1), |
||||
|
||||
/* Bman/Qman */ |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 5, BOOKE_PAGESZ_16M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, |
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 7, BOOKE_PAGESZ_16M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, |
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 9, BOOKE_PAGESZ_4M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 10, BOOKE_PAGESZ_64K, 1), |
||||
#endif |
||||
#ifdef QIXIS_BASE |
||||
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 11, BOOKE_PAGESZ_4K, 1), |
||||
#endif |
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 12, BOOKE_PAGESZ_1G, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, |
||||
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 13, BOOKE_PAGESZ_1G, 1) |
||||
#endif |
||||
/* entry 14 and 15 has been used hard coded, they will be disabled
|
||||
* in cpu_init_f, so if needed more, will use entry 16 later. |
||||
*/ |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -0,0 +1,12 @@ |
||||
if TARGET_T102XRDB |
||||
|
||||
config SYS_BOARD |
||||
default "t102xrdb" |
||||
|
||||
config SYS_VENDOR |
||||
default "freescale" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "T102xRDB" |
||||
|
||||
endif |
||||
@ -0,0 +1,10 @@ |
||||
T102XRDB BOARD |
||||
M: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
||||
S: Maintained |
||||
F: board/freescale/t102xrdb/ |
||||
F: include/configs/T102xRDB.h |
||||
F: configs/T1024RDB_defconfig |
||||
F: configs/T1024RDB_NAND_defconfig |
||||
F: configs/T1024RDB_SDCARD_defconfig |
||||
F: configs/T1024RDB_SPIFLASH_defconfig |
||||
F: configs/T1024RDB_SECURE_BOOT_defconfig |
||||
@ -0,0 +1,17 @@ |
||||
#
|
||||
# Copyright 2014 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
ifdef CONFIG_SPL_BUILD |
||||
obj-y += spl.o
|
||||
else |
||||
obj-y += t102xrdb.o
|
||||
obj-y += cpld.o
|
||||
obj-y += eth_t102xrdb.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
endif |
||||
obj-y += ddr.o
|
||||
obj-y += law.o
|
||||
obj-y += tlb.o
|
||||
@ -0,0 +1,258 @@ |
||||
T1024 SoC Overview |
||||
------------------ |
||||
The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor |
||||
combines two or one 64-bit Power Architecture e5500 core respectively with high |
||||
performance datapath acceleration logic, and network peripheral bus interfaces |
||||
required for networking and telecommunications. This processor can be used in |
||||
applications such as enterprise WLAN access points, routers, switches, firewall |
||||
and other packet processing intensive small enterprise and branch office appliances, |
||||
and general-purpose embedded computing. Its high level of integration offers |
||||
significant performance benefits and greatly helps to simplify board design. |
||||
|
||||
|
||||
The T1024 SoC includes the following function and features: |
||||
- two e5500 cores, each with a private 256 KB L2 cache |
||||
- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) |
||||
- Three levels of instructions: User, supervisor, and hypervisor |
||||
- Independent boot and reset |
||||
- Secure boot capability |
||||
- 256 KB shared L3 CoreNet platform cache (CPC) |
||||
- Interconnect CoreNet platform |
||||
- CoreNet coherency manager supporting coherent and noncoherent transactions |
||||
with prioritization and bandwidth allocation amongst CoreNet endpoints |
||||
- 150 Gbps coherent read bandwidth |
||||
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support |
||||
- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: |
||||
- Packet parsing, classification, and distribution |
||||
- Queue management for scheduling, packet sequencing, and congestion management |
||||
- Cryptography Acceleration (SEC 5.x) |
||||
- IEEE 1588 support |
||||
- Hardware buffer management for buffer allocation and deallocation |
||||
- MACSEC on DPAA-based Ethernet ports |
||||
- Ethernet interfaces |
||||
- Four 1 Gbps Ethernet controllers |
||||
- Parallel Ethernet interfaces |
||||
- Two RGMII interfaces |
||||
- High speed peripheral interfaces |
||||
- Three PCI Express 2.0 controllers/ports running at up to 5 GHz |
||||
- One SATA controller supporting 1.5 and 3.0 Gb/s operation |
||||
- One QSGMII interface |
||||
- Four SGMII interface supporting 1000 Mbps |
||||
- Three SGMII interfaces supporting up to 2500 Mbps |
||||
- 10GbE XFI or 10Base-KR interface |
||||
- Additional peripheral interfaces |
||||
- Two USB 2.0 controllers with integrated PHY |
||||
- SD/eSDHC/eMMC |
||||
- eSPI controller |
||||
- Four I2C controllers |
||||
- Four UARTs |
||||
- Four GPIO controllers |
||||
- Integrated flash controller (IFC) |
||||
- LCD interface (DIU) with 12 bit dual data rate |
||||
- Multicore programmable interrupt controller (PIC) |
||||
- Two 8-channel DMA engines |
||||
- Single source clocking implementation |
||||
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) |
||||
- QUICC Engine block |
||||
- 32-bit RISC controller for flexible support of the communications peripherals |
||||
- Serial DMA channel for receive and transmit on all serial channels |
||||
- Two universal communication controllers, supporting TDM, HDLC, and UART |
||||
|
||||
T1023 Personality |
||||
------------------ |
||||
T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and |
||||
unavailable deep sleep. Rest of the blocks are almost same as T1024. |
||||
Differences between T1024 and T1023 |
||||
Feature T1024 T1023 |
||||
QUICC Engine: yes no |
||||
DIU: yes no |
||||
Deep Sleep: yes no |
||||
I2C controller: 4 3 |
||||
DDR: 64-bit 32-bit |
||||
IFC: 32-bit 28-bit |
||||
|
||||
|
||||
T1024RDB board Overview |
||||
----------------------- |
||||
- Ethernet |
||||
- Two on-board 10M/100M/1G bps RGMII ethernet ports |
||||
- One on-board 10G bps Base-T port. |
||||
- DDR Memory |
||||
- Supports 64-bit 4GB DDR3L DIMM |
||||
- PCIe |
||||
- One on-board PCIe slot. |
||||
- Two on-board PCIe Mini-PCIe connectors. |
||||
- IFC/Local Bus |
||||
- NOR: 128MB 16-bit NOR Flash |
||||
- NAND: 1GB 8-bit NAND flash |
||||
- CPLD: for system controlling with programable header on-board |
||||
- USB |
||||
- Supports two USB 2.0 ports with integrated PHYs |
||||
- Two type A ports with 5V@1.5A per port. |
||||
- SDHC |
||||
- one SD connector supporting 1.8V/3.3V via J53. |
||||
- SPI |
||||
- On-board 64MB SPI flash |
||||
- Other |
||||
- Two Serial ports |
||||
- Four I2C ports |
||||
|
||||
|
||||
Memory map on T1024RDB |
||||
---------------------- |
||||
Start Address End Address Description Size |
||||
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB |
||||
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB |
||||
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB |
||||
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB |
||||
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB |
||||
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB |
||||
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB |
||||
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB |
||||
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB |
||||
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB |
||||
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB |
||||
0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB |
||||
0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB |
||||
0x0_0000_0000 0x0_ffff_ffff DDR 4GB |
||||
|
||||
|
||||
128MB NOR Flash memory Map |
||||
-------------------------- |
||||
Start Address End Address Definition Max size |
||||
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB |
||||
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB |
||||
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB |
||||
0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB |
||||
0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB |
||||
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB |
||||
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB |
||||
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB |
||||
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB |
||||
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB |
||||
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB |
||||
0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB |
||||
0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB |
||||
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB |
||||
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB |
||||
0xE8000000 0xE801FFFF RCW (current bank) 128KB |
||||
|
||||
|
||||
T1024 Clock frequency |
||||
--------------------- |
||||
BIN Core DDR Platform FMan |
||||
Bin1: 1400MHz 1600MT/s 400MHz 700MHz |
||||
Bin2: 1200MHz 1600MT/s 400MHz 600MHz |
||||
Bin3: 1000MHz 1600MT/s 400MHz 500MHz |
||||
|
||||
|
||||
Software configurations and board settings |
||||
------------------------------------------ |
||||
1. NOR boot: |
||||
a. build NOR boot image |
||||
$ make T1024RDB_defconfig |
||||
$ make |
||||
b. program u-boot.bin image to NOR flash |
||||
=> tftp 1000000 u-boot.bin |
||||
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize |
||||
set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot |
||||
|
||||
Switching between default bank0 and alternate bank4 on NOR flash |
||||
To change boot source to vbank4: |
||||
via software: run command 'cpld reset altbank' in u-boot. |
||||
via DIP-switch: set SW3[5:7] = '100' |
||||
|
||||
To change boot source to vbank0: |
||||
via software: run command 'cpld reset' in u-boot. |
||||
via DIP-Switch: set SW3[5:7] = '000' |
||||
|
||||
2. NAND Boot: |
||||
a. build PBL image for NAND boot |
||||
$ make T1024RDB_NAND_defconfig |
||||
$ make |
||||
b. program u-boot-with-spl-pbl.bin to NAND flash |
||||
=> tftp 1000000 u-boot-with-spl-pbl.bin |
||||
=> nand erase 0 $filesize |
||||
=> nand write 1000000 0 $filesize |
||||
set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot |
||||
|
||||
3. SPI Boot: |
||||
a. build PBL image for SPI boot |
||||
$ make T1024RDB_SPIFLASH_defconfig |
||||
$ make |
||||
b. program u-boot-with-spl-pbl.bin to SPI flash |
||||
=> tftp 1000000 u-boot-with-spl-pbl.bin |
||||
=> sf probe 0 |
||||
=> sf erase 0 f0000 |
||||
=> sf write 1000000 0 $filesize |
||||
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot |
||||
|
||||
4. SD Boot: |
||||
a. build PBL image for SD boot |
||||
$ make T1024RDB_SDCARD_defconfig |
||||
$ make |
||||
b. program u-boot-with-spl-pbl.bin to SD/MMC card |
||||
=> tftp 1000000 u-boot-with-spl-pbl.bin |
||||
=> mmc write 1000000 8 0x800 |
||||
=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin |
||||
=> mmc write 1000000 0x820 80 |
||||
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot |
||||
|
||||
|
||||
2-stage NAND/SPI/SD boot loader |
||||
------------------------------- |
||||
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. |
||||
SPL further initializes DDR using SPD and environment variables |
||||
and copy u-boot(768 KB) from NAND/SPI/SD device to DDR. |
||||
Finally SPL transers control to u-boot for futher booting. |
||||
|
||||
SPL has following features: |
||||
- Executes within 256K |
||||
- No relocation required |
||||
|
||||
Run time view of SPL framework |
||||
------------------------------------------------- |
||||
|Area | Address | |
||||
------------------------------------------------- |
||||
|SecureBoot header | 0xFFFC0000 (32KB) | |
||||
------------------------------------------------- |
||||
|GD, BD | 0xFFFC8000 (4KB) | |
||||
------------------------------------------------- |
||||
|ENV | 0xFFFC9000 (8KB) | |
||||
------------------------------------------------- |
||||
|HEAP | 0xFFFCB000 (30KB) | |
||||
------------------------------------------------- |
||||
|STACK | 0xFFFD8000 (22KB) | |
||||
------------------------------------------------- |
||||
|U-boot SPL | 0xFFFD8000 (160KB) | |
||||
------------------------------------------------- |
||||
|
||||
NAND Flash memory Map on T1024RDB |
||||
------------------------------------------------------------- |
||||
Start End Definition Size |
||||
0x000000 0x0FFFFF u-boot 1MB(2 block) |
||||
0x100000 0x17FFFF u-boot env 512KB(1 block) |
||||
0x180000 0x1FFFFF FMAN Ucode 512KB(1 block) |
||||
0x200000 0x27FFFF QE Firmware 512KB(1 block) |
||||
|
||||
|
||||
SD Card memory Map on T1024RDB |
||||
---------------------------------------------------- |
||||
Block #blocks Definition Size |
||||
0x008 2048 u-boot img 1MB |
||||
0x800 0016 u-boot env 8KB |
||||
0x820 0256 FMAN Ucode 128KB |
||||
0x920 0256 QE Firmware 128KB |
||||
|
||||
|
||||
SPI Flash memory Map on T1024RDB |
||||
---------------------------------------------------- |
||||
Start End Definition Size |
||||
0x000000 0x0FFFFF u-boot img 1MB |
||||
0x100000 0x101FFF u-boot env 8KB |
||||
0x110000 0x12FFFF FMAN Ucode 128KB |
||||
0x130000 0x14FFFF QE Firmware 128KB |
||||
|
||||
|
||||
For more details, please refer to T1024RDB Reference Manual and access |
||||
website www.freescale.com and Freescale QorIQ SDK Infocenter document. |
||||
@ -0,0 +1,103 @@ |
||||
/**
|
||||
* Copyright 2014 Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Freescale T1024RDB board-specific CPLD controlling supports. |
||||
* |
||||
* The following macros need to be defined: |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/io.h> |
||||
#include "cpld.h" |
||||
|
||||
u8 cpld_read(unsigned int reg) |
||||
{ |
||||
void *p = (void *)CONFIG_SYS_CPLD_BASE; |
||||
|
||||
return in_8(p + reg); |
||||
} |
||||
|
||||
void cpld_write(unsigned int reg, u8 value) |
||||
{ |
||||
void *p = (void *)CONFIG_SYS_CPLD_BASE; |
||||
|
||||
out_8(p + reg, value); |
||||
} |
||||
|
||||
/**
|
||||
* Set the boot bank to the alternate bank |
||||
*/ |
||||
void cpld_set_altbank(void) |
||||
{ |
||||
u8 reg = CPLD_READ(flash_csr); |
||||
|
||||
reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK; |
||||
|
||||
CPLD_WRITE(flash_csr, reg); |
||||
CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); |
||||
} |
||||
|
||||
/**
|
||||
* Set the boot bank to the default bank |
||||
*/ |
||||
void cpld_set_defbank(void) |
||||
{ |
||||
u8 reg = CPLD_READ(flash_csr); |
||||
|
||||
reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK; |
||||
|
||||
CPLD_WRITE(flash_csr, reg); |
||||
CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET); |
||||
} |
||||
|
||||
static void cpld_dump_regs(void) |
||||
{ |
||||
printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); |
||||
printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); |
||||
printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver)); |
||||
printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver)); |
||||
printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1)); |
||||
printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2)); |
||||
printf("int_status = 0x%02x\n", CPLD_READ(int_status)); |
||||
printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr)); |
||||
printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status)); |
||||
printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status)); |
||||
printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status)); |
||||
printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status)); |
||||
printf("boot_override = 0x%02x\n", CPLD_READ(boot_override)); |
||||
printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1)); |
||||
printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2)); |
||||
putc('\n'); |
||||
} |
||||
|
||||
int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
||||
{ |
||||
int rc = 0; |
||||
|
||||
if (argc <= 1) |
||||
return cmd_usage(cmdtp); |
||||
|
||||
if (strcmp(argv[1], "reset") == 0) { |
||||
if (strcmp(argv[2], "altbank") == 0) |
||||
cpld_set_altbank(); |
||||
else |
||||
cpld_set_defbank(); |
||||
} else if (strcmp(argv[1], "dump") == 0) { |
||||
cpld_dump_regs(); |
||||
} else { |
||||
rc = cmd_usage(cmdtp); |
||||
} |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
U_BOOT_CMD( |
||||
cpld, CONFIG_SYS_MAXARGS, 1, do_cpld, |
||||
"Reset the board or alternate bank", |
||||
"reset - hard reset to default bank\n" |
||||
"cpld reset altbank - reset to alternate bank\n" |
||||
"cpld dump - display the CPLD registers\n" |
||||
); |
||||
@ -0,0 +1,45 @@ |
||||
/**
|
||||
* Copyright 2014 Freescale Semiconductor |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
*/ |
||||
|
||||
struct cpld_data { |
||||
u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */ |
||||
u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */ |
||||
u8 hw_ver; /* 0x02 - Hardware Revision Register */ |
||||
u8 sw_ver; /* 0x03 - Software Revision register */ |
||||
u8 res0[12]; /* 0x04 - 0x0F - not used */ |
||||
u8 reset_ctl1; /* 0x10 - Reset control Register1 */ |
||||
u8 reset_ctl2; /* 0x11 - Reset control Register2 */ |
||||
u8 int_status; /* 0x12 - Interrupt status Register */ |
||||
u8 flash_csr; /* 0x13 - Flash control and status register */ |
||||
u8 fan_ctl_status; /* 0x14 - Fan control and status register */ |
||||
u8 led_ctl_status; /* 0x15 - LED control and status register */ |
||||
u8 sfp_ctl_status; /* 0x16 - SFP control and status register */ |
||||
u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/ |
||||
u8 boot_override; /* 0x18 - Boot override register */ |
||||
u8 boot_config1; /* 0x19 - Boot config override register*/ |
||||
u8 boot_config2; /* 0x1A - Boot config override register*/ |
||||
} cpld_data_t; |
||||
|
||||
|
||||
/* Pointer to the CPLD register set */ |
||||
|
||||
u8 cpld_read(unsigned int reg); |
||||
void cpld_write(unsigned int reg, u8 value); |
||||
|
||||
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) |
||||
#define CPLD_WRITE(reg, value)\ |
||||
cpld_write(offsetof(struct cpld_data, reg), value) |
||||
|
||||
/* CPLD on IFC */ |
||||
#define CPLD_LBMAP_MASK 0x3F |
||||
#define CPLD_BANK_SEL_MASK 0x07 |
||||
#define CPLD_BANK_OVERRIDE 0x40 |
||||
#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ |
||||
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */ |
||||
#define CPLD_LBMAP_RESET 0xFF |
||||
#define CPLD_LBMAP_SHIFT 0x03 |
||||
#define CPLD_BOOT_SEL 0x80 |
||||
@ -0,0 +1,154 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <hwconfig.h> |
||||
#include <asm/mmu.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <fsl_ddr_dimm_params.h> |
||||
#include <asm/fsl_law.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
struct board_specific_parameters { |
||||
u32 n_ranks; |
||||
u32 datarate_mhz_high; |
||||
u32 rank_gb; |
||||
u32 clk_adjust; |
||||
u32 wrlvl_start; |
||||
u32 wrlvl_ctl_2; |
||||
u32 wrlvl_ctl_3; |
||||
}; |
||||
|
||||
/*
|
||||
* datarate_mhz_high values need to be in ascending order |
||||
*/ |
||||
static const struct board_specific_parameters udimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |
||||
*/ |
||||
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, |
||||
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, |
||||
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, |
||||
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, |
||||
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, |
||||
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, |
||||
{} |
||||
}; |
||||
|
||||
static const struct board_specific_parameters *udimms[] = { |
||||
udimm0, |
||||
}; |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
||||
ulong ddr_freq; |
||||
struct cpu_type *cpu = gd->arch.cpu; |
||||
|
||||
if (ctrl_num > 1) { |
||||
printf("Not supported controller number %d\n", ctrl_num); |
||||
return; |
||||
} |
||||
if (!pdimm->n_ranks) |
||||
return; |
||||
|
||||
pbsp = udimms[0]; |
||||
|
||||
/* Get clk_adjust according to the board ddr freqency and n_banks
|
||||
* specified in board_specific_parameters table. |
||||
*/ |
||||
ddr_freq = get_ddr_freq(0) / 1000000; |
||||
while (pbsp->datarate_mhz_high) { |
||||
if (pbsp->n_ranks == pdimm->n_ranks && |
||||
(pdimm->rank_density >> 30) >= pbsp->rank_gb) { |
||||
if (ddr_freq <= pbsp->datarate_mhz_high) { |
||||
popts->clk_adjust = pbsp->clk_adjust; |
||||
popts->wrlvl_start = pbsp->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
goto found; |
||||
} |
||||
pbsp_highest = pbsp; |
||||
} |
||||
pbsp++; |
||||
} |
||||
|
||||
if (pbsp_highest) { |
||||
printf("Error: board specific timing not found\n"); |
||||
printf("for data rate %lu MT/s\n", ddr_freq); |
||||
printf("Trying to use the highest speed (%u) parameters\n", |
||||
pbsp_highest->datarate_mhz_high); |
||||
popts->clk_adjust = pbsp_highest->clk_adjust; |
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
} else { |
||||
panic("DIMM is not supported by this board"); |
||||
} |
||||
found: |
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", |
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); |
||||
debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", |
||||
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); |
||||
debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); |
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable: |
||||
* - number of DIMMs installed |
||||
*/ |
||||
popts->half_strength_driver_enable = 0; |
||||
/*
|
||||
* Write leveling override |
||||
*/ |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
|
||||
/*
|
||||
* rtt and rtt_wr override |
||||
*/ |
||||
popts->rtt_override = 0; |
||||
|
||||
/* Enable ZQ calibration */ |
||||
popts->zq_en = 1; |
||||
|
||||
/* DHC_EN =1, ODT = 75 Ohm */ |
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF); |
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF); |
||||
|
||||
/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
|
||||
* force DDR bus width to 32bit for T1023 |
||||
*/ |
||||
if (cpu->soc_ver == SVR_T1023) |
||||
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; |
||||
|
||||
#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 |
||||
/* for DDR bus 32bit test on T1024 */ |
||||
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; |
||||
#endif |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
phys_size_t dram_size; |
||||
|
||||
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) |
||||
puts("Initializing....using SPD\n"); |
||||
|
||||
dram_size = fsl_ddr_sdram(); |
||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
||||
dram_size *= 0x100000; |
||||
#else |
||||
/* DDR has been initialised by first stage boot loader */ |
||||
dram_size = fsl_ddr_sdram_size(); |
||||
#endif |
||||
return dram_size; |
||||
} |
||||
@ -0,0 +1,100 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <netdev.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <malloc.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_mdio.h> |
||||
#include <miiphy.h> |
||||
#include <phy.h> |
||||
#include <asm/fsl_dtsec.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#if defined(CONFIG_FMAN_ENET) |
||||
int i, interface; |
||||
struct memac_mdio_info dtsec_mdio_info; |
||||
struct memac_mdio_info tgec_mdio_info; |
||||
struct mii_dev *dev; |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_s1; |
||||
|
||||
srds_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
|
||||
dtsec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; |
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
||||
|
||||
/* Register the 1G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info); |
||||
|
||||
tgec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; |
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; |
||||
|
||||
/* Register the 10G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &tgec_mdio_info); |
||||
|
||||
/* Set the two on-board RGMII PHY address */ |
||||
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); |
||||
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); |
||||
|
||||
switch (srds_s1) { |
||||
case 0x95: |
||||
/* 10G XFI with Aquantia PHY */ |
||||
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); |
||||
break; |
||||
default: |
||||
printf("SerDes protocol 0x%x is not supported on T102xRDB\n", |
||||
srds_s1); |
||||
break; |
||||
} |
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
||||
interface = fm_info_get_enet_if(i); |
||||
switch (interface) { |
||||
case PHY_INTERFACE_MODE_RGMII: |
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); |
||||
fm_info_set_mdio(i, dev); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_XGMII: |
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); |
||||
fm_info_set_mdio(i, dev); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
cpu_eth_init(bis); |
||||
#endif /* CONFIG_FMAN_ENET */ |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
||||
|
||||
void fdt_fixup_board_enet(void *fdt) |
||||
{ |
||||
} |
||||
@ -0,0 +1,32 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
#ifndef CONFIG_SYS_NO_FLASH |
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), |
||||
#endif |
||||
#ifdef CONFIG_SYS_CPLD_BASE_PHYS |
||||
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS |
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
@ -0,0 +1,23 @@ |
||||
/*
|
||||
* Copyright 2007-2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <pci.h> |
||||
#include <asm/fsl_pci.h> |
||||
#include <libfdt.h> |
||||
#include <fdt_support.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
fsl_pcie_init_board(0); |
||||
} |
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd) |
||||
{ |
||||
FT_FSL_PCI_SETUP; |
||||
} |
||||
@ -0,0 +1,107 @@ |
||||
/* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <ns16550.h> |
||||
#include <nand.h> |
||||
#include <i2c.h> |
||||
#include <mmc.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <spi_flash.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
phys_size_t get_effective_memsize(void) |
||||
{ |
||||
return CONFIG_SYS_L3_SIZE; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
return CONFIG_SYS_CLK_FREQ; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
return CONFIG_DDR_CLK_FREQ; |
||||
} |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio, sys_clk, ccb_clk; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ |
||||
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); |
||||
|
||||
/* Update GD pointer */ |
||||
gd = (gd_t *)(CONFIG_SPL_GD_ADDR); |
||||
|
||||
console_init_f(); |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
sys_clk = get_board_sys_clk(); |
||||
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; |
||||
ccb_clk = sys_clk * plat_ratio / 2; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
ccb_clk / 16 / CONFIG_BAUDRATE); |
||||
|
||||
#if defined(CONFIG_SPL_MMC_BOOT) |
||||
puts("\nSD boot...\n"); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
puts("\nSPI boot...\n"); |
||||
#elif defined(CONFIG_SPL_NAND_BOOT) |
||||
puts("\nNAND boot...\n"); |
||||
#endif |
||||
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
bd_t *bd; |
||||
|
||||
bd = (bd_t *)(gd + sizeof(gd_t)); |
||||
memset(bd, 0, sizeof(bd_t)); |
||||
gd->bd = bd; |
||||
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; |
||||
bd->bi_memsize = CONFIG_SYS_L3_SIZE; |
||||
|
||||
probecpu(); |
||||
get_clocks(); |
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, |
||||
CONFIG_SPL_RELOC_MALLOC_SIZE); |
||||
|
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_initialize(bd); |
||||
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_SPI_BOOT |
||||
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
|
||||
gd->env_addr = (ulong)(CONFIG_ENV_ADDR); |
||||
gd->env_valid = 1; |
||||
|
||||
i2c_init_all(); |
||||
|
||||
gd->ram_size = initdram(0); |
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_boot(); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
spi_boot(); |
||||
#elif defined(CONFIG_SPL_NAND_BOOT) |
||||
nand_boot(); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,26 @@ |
||||
#PBI commands |
||||
#Initialize CPC1 |
||||
09010000 00200400 |
||||
09138000 00000000 |
||||
091380c0 00000100 |
||||
#Configure CPC1 as 256KB SRAM |
||||
09010100 00000000 |
||||
09010104 fffc0007 |
||||
09010f00 08000000 |
||||
09010000 80000000 |
||||
#Configure LAW for CPC1 |
||||
09000cd0 00000000 |
||||
09000cd4 fffc0000 |
||||
09000cd8 81000011 |
||||
#Configure alternate space |
||||
09000010 00000000 |
||||
09000014 ff000000 |
||||
09000018 81000000 |
||||
#Configure SPI controller |
||||
09110000 80000403 |
||||
09110020 2d170008 |
||||
09110024 00100008 |
||||
09110028 00100008 |
||||
0911002c 00100008 |
||||
#Flush PBL data |
||||
091380c0 000FFFFF |
||||
@ -0,0 +1,8 @@ |
||||
#PBL preamble and RCW header for T1024RDB |
||||
aa55aa55 010e0100 |
||||
#SerDes Protocol: 0x95 |
||||
#Core/DDR: 1400Mhz/1600MT/s with single source clock |
||||
0810000c 00000000 00000000 00000000 |
||||
4a800003 80000012 ec027000 21000000 |
||||
00000000 00000000 00000000 00030810 |
||||
00000000 0b005a08 00000000 00000006 |
||||
@ -0,0 +1,144 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <i2c.h> |
||||
#include <netdev.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <asm/mpc85xx_gpio.h> |
||||
#include <fm_eth.h> |
||||
#include "t102xrdb.h" |
||||
#include "cpld.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
struct cpu_type *cpu = gd->arch.cpu; |
||||
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; |
||||
|
||||
printf("Board: %sRDB, ", cpu->name); |
||||
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ", |
||||
CPLD_READ(hw_ver), CPLD_READ(sw_ver)); |
||||
|
||||
#ifdef CONFIG_SDCARD |
||||
puts("SD/MMC\n"); |
||||
#elif CONFIG_SPIFLASH |
||||
puts("SPI\n"); |
||||
#else |
||||
u8 reg; |
||||
|
||||
reg = CPLD_READ(flash_csr); |
||||
|
||||
if (reg & CPLD_BOOT_SEL) { |
||||
puts("NAND\n"); |
||||
} else { |
||||
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); |
||||
printf("NOR vBank%d\n", reg); |
||||
} |
||||
#endif |
||||
|
||||
puts("SERDES Reference Clocks:\n"); |
||||
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_early_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_SYS_FLASH_BASE |
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
||||
int flash_esel = find_tlb_idx((void *)flashbase, 1); |
||||
/*
|
||||
* Remap Boot flash region to caching-inhibited |
||||
* so that flash can be erased properly. |
||||
*/ |
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */ |
||||
flush_dcache(); |
||||
invalidate_icache(); |
||||
if (flash_esel == -1) { |
||||
/* very unlikely unless something is messed up */ |
||||
puts("Error: Could not find TLB for FLASH BASE\n"); |
||||
flash_esel = 2; /* give our best effort to continue */ |
||||
} else { |
||||
/* invalidate existing TLB entry for flash + promjet */ |
||||
disable_tlb(flash_esel); |
||||
} |
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1); |
||||
#endif |
||||
|
||||
set_liodns(); |
||||
#ifdef CONFIG_SYS_DPAA_QBMAN |
||||
setup_portals(); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
unsigned long get_board_sys_clk(void) |
||||
{ |
||||
return CONFIG_SYS_CLK_FREQ; |
||||
} |
||||
|
||||
unsigned long get_board_ddr_clk(void) |
||||
{ |
||||
return CONFIG_DDR_CLK_FREQ; |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd) |
||||
{ |
||||
phys_addr_t base; |
||||
phys_size_t size; |
||||
|
||||
ft_cpu_setup(blob, bd); |
||||
|
||||
base = getenv_bootm_low(); |
||||
size = getenv_bootm_size(); |
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size); |
||||
|
||||
#ifdef CONFIG_PCI |
||||
pci_of_setup(blob, bd); |
||||
#endif |
||||
|
||||
fdt_fixup_liodn(blob); |
||||
fdt_fixup_dr_usb(blob, bd); |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
fdt_fixup_fman_ethernet(blob); |
||||
fdt_fixup_board_enet(blob); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_DEEP_SLEEP |
||||
void board_mem_sleep_setup(void) |
||||
{ |
||||
/* does not provide HW signals for power management */ |
||||
CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40)); |
||||
/* Disable MCKE isolation */ |
||||
gpio_set_value(2, 0); |
||||
udelay(1); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,13 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __T1024_RDB_H__ |
||||
#define __T1024_RDB_H__ |
||||
|
||||
void fdt_fixup_board_enet(void *blob); |
||||
void pci_of_setup(void *blob, bd_t *bd); |
||||
|
||||
#endif |
||||
@ -0,0 +1,117 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = { |
||||
/* TLB 0 - for temp stack in cache */ |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 0, BOOKE_PAGESZ_4K, 0), |
||||
|
||||
/* TLB 1 */ |
||||
/* *I*** - Covers boot page */ |
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) |
||||
/*
|
||||
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the |
||||
* SRAM is at 0xfffc0000, it covered the 0xfffff000. |
||||
*/ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_256K, 1), |
||||
#else |
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 0, BOOKE_PAGESZ_4K, 1), |
||||
#endif |
||||
|
||||
/* *I*G* - CCSRBAR */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 1, BOOKE_PAGESZ_16M, 1), |
||||
|
||||
/* *I*G* - Flash, localbus */ |
||||
/* This will be changed to *I*G* after relocation to RAM. */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
||||
0, 2, BOOKE_PAGESZ_256M, 1), |
||||
|
||||
#ifndef CONFIG_SPL_BUILD |
||||
/* *I*G* - PCI */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 3, BOOKE_PAGESZ_1G, 1), |
||||
|
||||
/* *I*G* - PCI I/O */ |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 4, BOOKE_PAGESZ_256K, 1), |
||||
|
||||
/* Bman/Qman */ |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 5, BOOKE_PAGESZ_16M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, |
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 6, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 7, BOOKE_PAGESZ_16M, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, |
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 8, BOOKE_PAGESZ_16M, 1), |
||||
#endif |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 9, BOOKE_PAGESZ_4M, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 10, BOOKE_PAGESZ_64K, 1), |
||||
#endif |
||||
#ifdef CONFIG_SYS_CPLD_BASE |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
||||
0, 11, BOOKE_PAGESZ_256K, 1), |
||||
#endif |
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 12, BOOKE_PAGESZ_1G, 1), |
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, |
||||
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, |
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0, |
||||
0, 13, BOOKE_PAGESZ_1G, 1) |
||||
#endif |
||||
/* entry 14 and 15 has been used hard coded, they will be disabled
|
||||
* in cpu_init_f, so if needed more, will use entry 16 later. |
||||
*/ |
||||
}; |
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table); |
||||
@ -1,8 +1,16 @@ |
||||
#PBL preamble and RCW header |
||||
aa55aa55 010e0100 |
||||
#SerDes Protocol: 0x66_0x16 |
||||
#Core/DDR: 1533Mhz/2133MT/s |
||||
12100017 15000000 00000000 00000000 |
||||
66150002 00008400 e8104000 c1000000 |
||||
|
||||
#For T2080 v1.0 |
||||
#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s |
||||
#12100017 15000000 00000000 00000000 |
||||
#66150002 00008400 e8104000 c1000000 |
||||
#00000000 00000000 00000000 000307fc |
||||
#00000000 00000000 00000000 00000004 |
||||
|
||||
#For T2080 v1.1 |
||||
#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s |
||||
0c070012 0e000000 00000000 00000000 |
||||
66150002 00000000 e8104000 c1000000 |
||||
00000000 00000000 00000000 000307fc |
||||
00000000 00000000 00000000 00000004 |
||||
|
||||
@ -1,8 +1,16 @@ |
||||
#PBL preamble and RCW header for T2080RDB |
||||
#PBL preamble and RCW header |
||||
aa55aa55 010e0100 |
||||
#SerDes Protocol: 0x66_0x16 |
||||
#Core/DDR: 1533Mhz/1600MT/s |
||||
120c0017 15000000 00000000 00000000 |
||||
66150002 00008400 ec104000 c1000000 |
||||
00000000 00000000 00000000 000307fc |
||||
|
||||
#For T2080 v1.0 |
||||
#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s |
||||
#120c0017 15000000 00000000 00000000 |
||||
#66150002 00008400 ec104000 c1000000 |
||||
#00000000 00000000 00000000 000307fc |
||||
#00000000 00000000 00000000 00000004 |
||||
|
||||
#For T2080 v1.1 |
||||
#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s |
||||
1206001b 15000000 00000000 00000000 |
||||
66150002 00000000 e8104000 c1000000 |
||||
00800000 00000000 00000000 000307fc |
||||
00000000 00000000 00000000 00000004 |
||||
|
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XQDS=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_T102XQDS=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_T102XQDS=y |
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XQDS=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_T102XQDS=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,5 @@ |
||||
CONFIG_SPL=y |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" |
||||
+S:CONFIG_PPC=y |
||||
+S:CONFIG_MPC85xx=y |
||||
+S:CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,4 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" |
||||
CONFIG_PPC=y |
||||
CONFIG_MPC85xx=y |
||||
CONFIG_TARGET_T102XRDB=y |
||||
@ -0,0 +1,10 @@ |
||||
This file documents Freescale DPAA-specific options. |
||||
|
||||
FMan (Frame Manager) |
||||
- CONFIG_FSL_FM_10GEC_REGULAR_NOTATION |
||||
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: |
||||
10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 |
||||
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: |
||||
10GEC1->MAC1, 10GEC2->MAC2 |
||||
so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on |
||||
which 10GEC enumeration is consistent with MAC enumeration. |
||||
@ -0,0 +1,88 @@ |
||||
/* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* |
||||
* Shengzhou Liu <Shengzhou.Liu@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <phy.h> |
||||
#include <fm_eth.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_serdes.h> |
||||
|
||||
u32 port_to_devdisr[] = { |
||||
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, |
||||
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, |
||||
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, |
||||
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, |
||||
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */ |
||||
}; |
||||
|
||||
static int is_device_disabled(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 devdisr2 = in_be32(&gur->devdisr2); |
||||
|
||||
return port_to_devdisr[port] & devdisr2; |
||||
} |
||||
|
||||
void fman_disable_port(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
|
||||
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); |
||||
} |
||||
|
||||
phy_interface_t fman_port_enet_if(enum fm_port port) |
||||
{ |
||||
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 rcwsr13 = in_be32(&gur->rcwsr[13]); |
||||
|
||||
if (is_device_disabled(port)) |
||||
return PHY_INTERFACE_MODE_NONE; |
||||
|
||||
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1))) |
||||
return PHY_INTERFACE_MODE_XGMII; |
||||
|
||||
if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == |
||||
FSL_CORENET_RCWSR13_EC2_RGMII) && |
||||
(!is_serdes_configured(QSGMII_FM1_A))) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == |
||||
FSL_CORENET_RCWSR13_EC1_RGMII) && |
||||
(!is_serdes_configured(QSGMII_FM1_A))) |
||||
return PHY_INTERFACE_MODE_RGMII; |
||||
|
||||
/* handle SGMII */ |
||||
switch (port) { |
||||
case FM1_DTSEC1: |
||||
case FM1_DTSEC2: |
||||
case FM1_DTSEC3: |
||||
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) |
||||
return PHY_INTERFACE_MODE_SGMII; |
||||
else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1 |
||||
+ port - FM1_DTSEC1)) |
||||
return PHY_INTERFACE_MODE_SGMII_2500; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
/* handle QSGMII */ |
||||
switch (port) { |
||||
case FM1_DTSEC1: |
||||
case FM1_DTSEC2: |
||||
case FM1_DTSEC3: |
||||
case FM1_DTSEC4: |
||||
/* check lane A on SerDes1 */ |
||||
if (is_serdes_configured(QSGMII_FM1_A)) |
||||
return PHY_INTERFACE_MODE_QSGMII; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
return PHY_INTERFACE_MODE_NONE; |
||||
} |
||||
@ -0,0 +1,333 @@ |
||||
/*
|
||||
* Cortina CS4315/CS4340 10G PHY drivers |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <linux/ctype.h> |
||||
#include <linux/string.h> |
||||
#include <linux/err.h> |
||||
#include <phy.h> |
||||
#include <cortina.h> |
||||
#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND |
||||
#include <nand.h> |
||||
#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) |
||||
#include <spi_flash.h> |
||||
#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) |
||||
#include <mmc.h> |
||||
#endif |
||||
|
||||
#ifndef CONFIG_PHYLIB_10G |
||||
#error The Cortina PHY needs 10G support |
||||
#endif |
||||
|
||||
struct cortina_reg_config cortina_reg_cfg[] = { |
||||
/* CS4315_enable_sr_mode */ |
||||
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, |
||||
{VILLA_MSEQ_OPTIONS, 0xf}, |
||||
{VILLA_MSEQ_PC, 0x0}, |
||||
{VILLA_MSEQ_BANKSELECT, 0x4}, |
||||
{VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55}, |
||||
{VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30}, |
||||
{VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1}, |
||||
{VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2}, |
||||
{VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003}, |
||||
{VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047}, |
||||
{VILLA_MSEQ_ENABLE_MSB, 0x0000}, |
||||
{VILLA_MSEQ_SPARE21_LSB, 0x6}, |
||||
{VILLA_MSEQ_RESET_COUNT_LSB, 0x0}, |
||||
{VILLA_MSEQ_SPARE12_MSB, 0x0000}, |
||||
/*
|
||||
* to invert the receiver path, uncomment the next line |
||||
* write (VILLA_MSEQ_SPARE12_MSB, 0x4000) |
||||
* |
||||
* SPARE2_LSB is used to configure the device while in sr mode to |
||||
* enable power savings and to use the optical module LOS signal. |
||||
* in power savings mode, the internal prbs checker can not be used. |
||||
* if the optical module LOS signal is used as an input to the micro |
||||
* code, then the micro code will wait until the optical module |
||||
* LOS = 0 before turning on the adaptive equalizer. |
||||
* Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode |
||||
* while setting bit 0 to 0 disables power savings mode. |
||||
* Setting SPARE2_LSB bit 2 to 0 configures the device to use the |
||||
* optical module LOS signal while setting bit 2 to 1 configures the |
||||
* device so that it will ignore the optical module LOS SPARE2_LSB = 0 |
||||
*/ |
||||
|
||||
/* enable power savings, ignore optical module LOS */ |
||||
{VILLA_MSEQ_SPARE2_LSB, 0x5}, |
||||
|
||||
{VILLA_MSEQ_SPARE7_LSB, 0x1e}, |
||||
{VILLA_MSEQ_BANKSELECT, 0x4}, |
||||
{VILLA_MSEQ_SPARE9_LSB, 0x2}, |
||||
{VILLA_MSEQ_SPARE3_LSB, 0x0F53}, |
||||
{VILLA_MSEQ_SPARE3_MSB, 0x2006}, |
||||
{VILLA_MSEQ_SPARE8_LSB, 0x3FF7}, |
||||
{VILLA_MSEQ_SPARE8_MSB, 0x0A46}, |
||||
{VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500}, |
||||
{VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200}, |
||||
{VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00}, |
||||
{VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100}, |
||||
{VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300}, |
||||
{VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300}, |
||||
{VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700}, |
||||
{VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00}, |
||||
{VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00}, |
||||
{VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2}, |
||||
{VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000}, |
||||
{VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF}, |
||||
{VILLA_MSEQ_POWER_DOWN_MSB, 0x0}, |
||||
{VILLA_MSEQ_CAL_RX_SLICER, 0x80}, |
||||
{VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f}, |
||||
{VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, |
||||
{VILLA_MSEQ_OPTIONS, 0x7}, |
||||
|
||||
/* set up min value for ffe1 */ |
||||
{VILLA_MSEQ_COEF_INIT_SEL, 0x2}, |
||||
{VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41}, |
||||
|
||||
/* CS4315_sr_rx_pre_eq_set_4in */ |
||||
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, |
||||
{VILLA_MSEQ_OPTIONS, 0xf}, |
||||
{VILLA_MSEQ_BANKSELECT, 0x4}, |
||||
{VILLA_MSEQ_PC, 0x0}, |
||||
|
||||
/* for lengths from 3.5 to 4.5inches */ |
||||
{VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306}, |
||||
{VILLA_MSEQ_SPARE25_LSB, 0x0306}, |
||||
{VILLA_MSEQ_SPARE21_LSB, 0x2}, |
||||
{VILLA_MSEQ_SPARE23_LSB, 0x2}, |
||||
{VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0}, |
||||
|
||||
{VILLA_GLOBAL_MSEQCLKCTRL, 0x4}, |
||||
{VILLA_MSEQ_OPTIONS, 0x7}, |
||||
|
||||
/* CS4315_rx_drive_4inch */ |
||||
/* for length 4inches */ |
||||
{VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, |
||||
{VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, |
||||
{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, |
||||
|
||||
/* CS4315_tx_drive_4inch */ |
||||
/* for length 4inches */ |
||||
{VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000}, |
||||
{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023}, |
||||
{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E}, |
||||
}; |
||||
|
||||
void cs4340_upload_firmware(struct phy_device *phydev) |
||||
{ |
||||
char line_temp[0x50] = {0}; |
||||
char reg_addr[0x50] = {0}; |
||||
char reg_data[0x50] = {0}; |
||||
int i, line_cnt = 0, column_cnt = 0; |
||||
struct cortina_reg_config fw_temp; |
||||
char *addr = NULL; |
||||
|
||||
#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \ |
||||
defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE) |
||||
|
||||
addr = (char *)CONFIG_CORTINA_FW_ADDR; |
||||
#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND) |
||||
int ret; |
||||
size_t fw_length = CONFIG_CORTINA_FW_LENGTH; |
||||
|
||||
addr = malloc(CONFIG_CORTINA_FW_LENGTH); |
||||
ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR, |
||||
&fw_length, (u_char *)addr); |
||||
if (ret == -EUCLEAN) { |
||||
printf("NAND read of Cortina firmware at 0x%x failed %d\n", |
||||
CONFIG_CORTINA_FW_ADDR, ret); |
||||
} |
||||
#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) |
||||
int ret; |
||||
struct spi_flash *ucode_flash; |
||||
|
||||
addr = malloc(CONFIG_CORTINA_FW_LENGTH); |
||||
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, |
||||
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); |
||||
if (!ucode_flash) { |
||||
puts("SF: probe for Cortina ucode failed\n"); |
||||
} else { |
||||
ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR, |
||||
CONFIG_CORTINA_FW_LENGTH, addr); |
||||
if (ret) |
||||
puts("SF: read for Cortina ucode failed\n"); |
||||
spi_flash_free(ucode_flash); |
||||
} |
||||
#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) |
||||
int dev = CONFIG_SYS_MMC_ENV_DEV; |
||||
u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; |
||||
u32 blk = CONFIG_CORTINA_FW_ADDR / 512; |
||||
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); |
||||
|
||||
if (!mmc) { |
||||
puts("Failed to find MMC device for Cortina ucode\n"); |
||||
} else { |
||||
addr = malloc(CONFIG_CORTINA_FW_LENGTH); |
||||
printf("MMC read: dev # %u, block # %u, count %u ...\n", |
||||
dev, blk, cnt); |
||||
mmc_init(mmc); |
||||
(void)mmc->block_dev.block_read(dev, blk, cnt, addr); |
||||
/* flush cache after read */ |
||||
flush_cache((ulong)addr, cnt * 512); |
||||
} |
||||
#endif |
||||
|
||||
while (*addr != 'Q') { |
||||
i = 0; |
||||
|
||||
while (*addr != 0x0a) { |
||||
line_temp[i++] = *addr++; |
||||
if (0x50 < i) { |
||||
printf("Not found Cortina PHY ucode at 0x%x\n", |
||||
CONFIG_CORTINA_FW_ADDR); |
||||
return; |
||||
} |
||||
} |
||||
|
||||
addr++; /* skip '\n' */ |
||||
line_cnt++; |
||||
column_cnt = i; |
||||
line_temp[column_cnt] = '\0'; |
||||
|
||||
if (CONFIG_CORTINA_FW_LENGTH < line_cnt) |
||||
return; |
||||
|
||||
for (i = 0; i < column_cnt; i++) { |
||||
if (isspace(line_temp[i++])) |
||||
break; |
||||
} |
||||
|
||||
memcpy(reg_addr, line_temp, i); |
||||
memcpy(reg_data, &line_temp[i], column_cnt - i); |
||||
strim(reg_addr); |
||||
strim(reg_data); |
||||
fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; |
||||
fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & |
||||
0xffff; |
||||
phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); |
||||
} |
||||
} |
||||
|
||||
int cs4340_phy_init(struct phy_device *phydev) |
||||
{ |
||||
int timeout = 100; /* 100ms */ |
||||
int reg_value; |
||||
|
||||
/* step1: BIST test */ |
||||
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); |
||||
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); |
||||
phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); |
||||
while (--timeout) { |
||||
reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); |
||||
if (reg_value & mseq_edc_bist_done) { |
||||
if (0 == (reg_value & mseq_edc_bist_fail)) |
||||
break; |
||||
} |
||||
udelay(1000); |
||||
} |
||||
|
||||
if (!timeout) { |
||||
printf("%s BIST mseq_edc_bist_done timeout!\n", __func__); |
||||
return -1; |
||||
} |
||||
|
||||
/* setp2: upload ucode */ |
||||
cs4340_upload_firmware(phydev); |
||||
reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); |
||||
if (reg_value) { |
||||
debug("%s checksum status failed.\n", __func__); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int cs4340_config(struct phy_device *phydev) |
||||
{ |
||||
cs4340_phy_init(phydev); |
||||
return 0; |
||||
} |
||||
|
||||
int cs4340_startup(struct phy_device *phydev) |
||||
{ |
||||
phydev->link = 1; |
||||
|
||||
/* For now just lie and say it's 10G all the time */ |
||||
phydev->speed = SPEED_10000; |
||||
phydev->duplex = DUPLEX_FULL; |
||||
return 0; |
||||
} |
||||
|
||||
struct phy_driver cs4340_driver = { |
||||
.name = "Cortina CS4315/CS4340", |
||||
.uid = PHY_UID_CS4340, |
||||
.mask = 0xfffffff0, |
||||
.features = PHY_10G_FEATURES, |
||||
.mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | |
||||
MDIO_DEVS_PHYXS | MDIO_DEVS_AN | |
||||
MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2), |
||||
.config = &cs4340_config, |
||||
.startup = &cs4340_startup, |
||||
.shutdown = &gen10g_shutdown, |
||||
}; |
||||
|
||||
int phy_cortina_init(void) |
||||
{ |
||||
phy_register(&cs4340_driver); |
||||
return 0; |
||||
} |
||||
|
||||
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) |
||||
{ |
||||
int phy_reg; |
||||
bool is_cortina_phy = false; |
||||
|
||||
switch (addr) { |
||||
#ifdef CORTINA_PHY_ADDR1 |
||||
case CORTINA_PHY_ADDR1: |
||||
#endif |
||||
#ifdef CORTINA_PHY_ADDR2 |
||||
case CORTINA_PHY_ADDR2: |
||||
#endif |
||||
#ifdef CORTINA_PHY_ADDR3 |
||||
case CORTINA_PHY_ADDR3: |
||||
#endif |
||||
#ifdef CORTINA_PHY_ADDR4 |
||||
case CORTINA_PHY_ADDR4: |
||||
#endif |
||||
is_cortina_phy = true; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
/* Cortina PHY has non-standard offset of PHY ID registers */ |
||||
if (is_cortina_phy) |
||||
phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB); |
||||
else |
||||
phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); |
||||
|
||||
if (phy_reg < 0) |
||||
return -EIO; |
||||
|
||||
*phy_id = (phy_reg & 0xffff) << 16; |
||||
if (is_cortina_phy) |
||||
phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB); |
||||
else |
||||
phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); |
||||
|
||||
if (phy_reg < 0) |
||||
return -EIO; |
||||
|
||||
*phy_id |= (phy_reg & 0xffff); |
||||
|
||||
return 0; |
||||
} |
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in new issue