Board support for the Guntermann & Drunck DLVision-10G. Adds support for multiple FPGAs per board for gdsys 405ep architecture. Adds support for dual link osd hardware for gdsys 405ep. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>master
Dirk Eibach
14 years ago
committed by
Stefan Roese
parent
42d44f631c
commit
2da0fc0d0f
@ -0,0 +1,239 @@ |
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/*
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* (C) Copyright 2010 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <asm/ppc4xx-gpio.h> |
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#include <gdsys_fpga.h> |
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#include "../common/osd.h" |
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enum { |
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UNITTYPE_VIDEO_USER = 0, |
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UNITTYPE_MAIN_USER = 1, |
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UNITTYPE_VIDEO_SERVER = 2, |
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UNITTYPE_MAIN_SERVER = 3, |
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}; |
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enum { |
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HWVER_101 = 0, |
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HWVER_110 = 1, |
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}; |
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enum { |
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AUDIO_NONE = 0, |
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AUDIO_TX = 1, |
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AUDIO_RX = 2, |
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AUDIO_RXTX = 3, |
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}; |
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enum { |
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SYSCLK_156250 = 2, |
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}; |
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enum { |
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RAM_NONE = 0, |
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RAM_DDR2_32 = 1, |
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RAM_DDR2_64 = 2, |
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}; |
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static void print_fpga_info(unsigned dev) |
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{ |
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ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev); |
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u16 versions = in_le16(&fpga->versions); |
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u16 fpga_version = in_le16(&fpga->fpga_version); |
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u16 fpga_features = in_le16(&fpga->fpga_features); |
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unsigned unit_type; |
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unsigned hardware_version; |
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unsigned feature_compression; |
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unsigned feature_rs232; |
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unsigned feature_audio; |
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unsigned feature_sysclock; |
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unsigned feature_ramconfig; |
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unsigned feature_carrier_speed; |
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unsigned feature_carriers; |
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unsigned feature_video_channels; |
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int fpga_state = get_fpga_state(dev); |
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printf("FPGA%d: ", dev); |
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hardware_version = versions & 0x000f; |
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if (fpga_state |
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&& !((hardware_version == HWVER_101) |
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&& (fpga_state == FPGA_STATE_DONE_FAILED))) { |
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puts("not available\n"); |
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print_fpga_state(dev); |
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return; |
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} |
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unit_type = (versions >> 4) & 0x000f; |
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hardware_version = versions & 0x000f; |
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feature_compression = (fpga_features >> 13) & 0x0003; |
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feature_rs232 = fpga_features & (1<<11); |
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feature_audio = (fpga_features >> 9) & 0x0003; |
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feature_sysclock = (fpga_features >> 7) & 0x0003; |
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feature_ramconfig = (fpga_features >> 5) & 0x0003; |
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feature_carrier_speed = fpga_features & (1<<4); |
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feature_carriers = (fpga_features >> 2) & 0x0003; |
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feature_video_channels = fpga_features & 0x0003; |
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switch (unit_type) { |
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case UNITTYPE_VIDEO_USER: |
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printf("Videochannel Userside"); |
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break; |
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case UNITTYPE_MAIN_USER: |
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printf("Mainchannel Userside"); |
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break; |
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case UNITTYPE_VIDEO_SERVER: |
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printf("Videochannel Serverside"); |
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break; |
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case UNITTYPE_MAIN_SERVER: |
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printf("Mainchannel Serverside"); |
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break; |
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default: |
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printf("UnitType %d(not supported)", unit_type); |
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break; |
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} |
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switch (hardware_version) { |
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case HWVER_101: |
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printf(" HW-Ver 1.01\n"); |
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break; |
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case HWVER_110: |
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printf(" HW-Ver 1.10\n"); |
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break; |
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default: |
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printf(" HW-Ver %d(not supported)\n", |
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hardware_version); |
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break; |
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} |
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printf(" FPGA V %d.%02d, features:", |
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fpga_version / 100, fpga_version % 100); |
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printf(" %sRS232", feature_rs232 ? "" : "no "); |
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switch (feature_audio) { |
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case AUDIO_NONE: |
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printf(", no audio"); |
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break; |
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case AUDIO_TX: |
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printf(", audio tx"); |
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break; |
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case AUDIO_RX: |
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printf(", audio rx"); |
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break; |
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case AUDIO_RXTX: |
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printf(", audio rx+tx"); |
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break; |
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default: |
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printf(", audio %d(not supported)", feature_audio); |
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break; |
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} |
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switch (feature_sysclock) { |
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case SYSCLK_156250: |
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printf(", clock 156.25 MHz"); |
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break; |
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default: |
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printf(", clock %d(not supported)", feature_sysclock); |
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break; |
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} |
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puts(",\n "); |
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switch (feature_ramconfig) { |
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case RAM_NONE: |
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printf("no RAM"); |
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break; |
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case RAM_DDR2_32: |
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printf("RAM 32 bit DDR2"); |
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break; |
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case RAM_DDR2_64: |
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printf("RAM 64 bit DDR2"); |
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break; |
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default: |
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printf("RAM %d(not supported)", feature_ramconfig); |
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break; |
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} |
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printf(", %d carrier(s) %s", feature_carriers, |
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feature_carrier_speed ? "10 Gbit/s" : "of unknown speed"); |
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printf(", %d video channel(s)\n", feature_video_channels); |
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} |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard(void) |
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{ |
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unsigned k; |
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char *s = getenv("serial#"); |
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printf("Board: "); |
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printf("DLVision 10G"); |
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if (s != NULL) { |
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puts(", serial# "); |
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puts(s); |
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} |
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puts("\n"); |
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for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) |
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print_fpga_info(k); |
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return 0; |
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} |
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int last_stage_init(void) |
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{ |
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unsigned k; |
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for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k) |
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if (!get_fpga_state(k) |
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|| (get_fpga_state(k) == FPGA_STATE_DONE_FAILED)) |
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osd_probe(k); |
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return 0; |
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} |
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@ -1,37 +0,0 @@ |
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/*
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* (C) Copyright 2010 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef _FPGA_H_ |
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#define _FPGA_H_ |
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static inline u16 fpga_get_reg(unsigned reg) |
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{ |
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return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg)); |
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} |
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static inline void fpga_set_reg(unsigned reg, u16 val) |
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{ |
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return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val); |
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} |
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#endif |
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@ -0,0 +1,316 @@ |
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/*
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* (C) Copyright 2010 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_405EP 1 /* this is a PPC405 CPU */ |
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#define CONFIG_4xx 1 /* member of PPC4xx family */ |
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#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */ |
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#define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
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/*
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* Include common defines/options for all AMCC eval boards |
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*/ |
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#define CONFIG_HOSTNAME dlvsion-10g |
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#define CONFIG_IDENT_STRING " dlvision-10g 0.01" |
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#include "amcc-common.h" |
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ |
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#define CONFIG_LAST_STAGE_INIT |
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
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/*
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* Configure PLL |
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*/ |
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#define PLLMR0_DEFAULT PLLMR0_266_133_66 |
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#define PLLMR1_DEFAULT PLLMR1_266_133_66 |
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/* new uImage format support */ |
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#define CONFIG_FIT |
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#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
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#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ |
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/*
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* Default environment variables |
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*/ |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"fdt_addr=fc1e0000\0" \
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"ramdisk_addr=fc200000\0" \
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"" |
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#define CONFIG_PHY_ADDR 4 /* PHY address */ |
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#define CONFIG_HAS_ETH0 |
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#define CONFIG_HAS_ETH1 |
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#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ |
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ |
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/*
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* Commands additional to the ones defined in amcc-common.h |
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*/ |
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#define CONFIG_CMD_CACHE |
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#undef CONFIG_CMD_EEPROM |
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/*
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* SDRAM configuration (please see cpu/ppc/sdram.[ch]) |
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*/ |
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
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/* SDRAM timings used in datasheet */ |
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#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ |
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#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ |
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#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ |
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#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ |
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#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ |
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/*
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* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
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* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. |
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* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. |
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* The Linux BASE_BAUD define should match this configuration. |
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* baseBaud = cpuClock/(uartDivisor*16) |
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* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
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* set Linux BASE_BAUD to 403200. |
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*/ |
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#define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
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#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
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#define CONFIG_SYS_BASE_BAUD 691200 |
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/*
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* I2C stuff |
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*/ |
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#define CONFIG_SYS_I2C_SPEED 100000 |
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/* Temp sensor/hwmon/dtt */ |
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#define CONFIG_DTT_LM63 1 /* National LM63 */ |
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#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ |
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#define CONFIG_DTT_PWM_LOOKUPTABLE \ |
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{ { 40, 10 }, { 50, 20 }, { 60, 40 } } |
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#define CONFIG_DTT_TACH_LIMIT 0xa10 |
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/* EBC peripherals */ |
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#define CONFIG_SYS_FLASH_BASE 0xFC000000 |
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#define CONFIG_SYS_FPGA0_BASE 0x7f100000 |
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#define CONFIG_SYS_FPGA1_BASE 0x7f200000 |
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#define CONFIG_SYS_LATCH_BASE 0x7f300000 |
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#define CONFIG_SYS_FPGA_BASE(k) \ |
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(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) |
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#define CONFIG_SYS_FPGA_DONE(k) \ |
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(k ? 0x2000 : 0x1000) |
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#define CONFIG_SYS_FPGA_COUNT 2 |
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#define CONFIG_SYS_LATCH0_RESET 0xffff |
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#define CONFIG_SYS_LATCH0_BOOT 0xffff |
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#define CONFIG_SYS_LATCH1_RESET 0xffcf |
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#define CONFIG_SYS_LATCH1_BOOT 0xffff |
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/*
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* FLASH organization |
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*/ |
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ |
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */ |
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ |
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#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ |
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#ifdef CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
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#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
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/* Address and size of Redundant Environment Sector */ |
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
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#endif |
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/*
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* PPC405 GPIO Configuration |
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*/ |
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#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ |
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{ \
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/* GPIO Core 0 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
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} \
|
||||
} |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ |
||||
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (NOR-flash) */ |
||||
#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \ |
||||
EBC_BXAP_FWT_ENCODE(8) | \
|
||||
EBC_BXAP_BWT_ENCODE(7) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(2) | \
|
||||
EBC_BXAP_WBN_ENCODE(2) | \
|
||||
EBC_BXAP_WBF_ENCODE(2) | \
|
||||
EBC_BXAP_TH_ENCODE(4) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ |
||||
EBC_BXCR_BS_64MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/* Memory Bank 1 (FPGA0) */ |
||||
#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ |
||||
EBC_BXAP_TWT_ENCODE(5) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(2) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(0) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \ |
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/* Memory Bank 2 (FPGA1) */ |
||||
#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ |
||||
EBC_BXAP_TWT_ENCODE(6) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(2) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(0) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ |
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/* Memory Bank 3 (Latches) */ |
||||
#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \ |
||||
EBC_BXAP_FWT_ENCODE(8) | \
|
||||
EBC_BXAP_BWT_ENCODE(4) | \
|
||||
EBC_BXAP_BCE_DISABLE | \
|
||||
EBC_BXAP_BCT_2TRANS | \
|
||||
EBC_BXAP_CSN_ENCODE(0) | \
|
||||
EBC_BXAP_OEN_ENCODE(1) | \
|
||||
EBC_BXAP_WBN_ENCODE(1) | \
|
||||
EBC_BXAP_WBF_ENCODE(1) | \
|
||||
EBC_BXAP_TH_ENCODE(2) | \
|
||||
EBC_BXAP_RE_DISABLED | \
|
||||
EBC_BXAP_SOR_NONDELAYED | \
|
||||
EBC_BXAP_BEM_WRITEONLY | \
|
||||
EBC_BXAP_PEN_DISABLED) |
||||
#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \ |
||||
EBC_BXCR_BS_1MB | \
|
||||
EBC_BXCR_BU_RW | \
|
||||
EBC_BXCR_BW_16BIT) |
||||
|
||||
/*
|
||||
* OSD Setup |
||||
*/ |
||||
#define CONFIG_SYS_ICS8N3QV01 |
||||
#define CONFIG_SYS_SIL1178 |
||||
#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,108 @@ |
||||
/*
|
||||
* (C) Copyright 2010 |
||||
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __GDSYS_FPGA_H |
||||
#define __GDSYS_FPGA_H |
||||
|
||||
enum { |
||||
FPGA_STATE_DONE_FAILED = 1 << 0, |
||||
FPGA_STATE_REFLECTION_FAILED = 1 << 1, |
||||
}; |
||||
|
||||
int get_fpga_state(unsigned dev); |
||||
void print_fpga_state(unsigned dev); |
||||
|
||||
typedef struct ihs_gpio { |
||||
u16 read; |
||||
u16 clear; |
||||
u16 set; |
||||
} ihs_gpio_t; |
||||
|
||||
typedef struct ihs_i2c { |
||||
u16 write_mailbox; |
||||
u16 write_mailbox_ext; |
||||
u16 read_mailbox; |
||||
u16 read_mailbox_ext; |
||||
} ihs_i2c_t; |
||||
|
||||
typedef struct ihs_osd { |
||||
u16 version; |
||||
u16 features; |
||||
u16 control; |
||||
u16 xy_size; |
||||
} ihs_osd_t; |
||||
|
||||
#ifdef CONFIG_IO |
||||
typedef struct ihs_fpga { |
||||
u16 reflection_low; /* 0x0000 */ |
||||
u16 versions; /* 0x0002 */ |
||||
u16 fpga_features; /* 0x0004 */ |
||||
u16 fpga_version; /* 0x0006 */ |
||||
u16 reserved_0[5]; /* 0x0008 */ |
||||
u16 quad_serdes_reset; /* 0x0012 */ |
||||
u16 reserved_1[8181]; /* 0x0014 */ |
||||
u16 reflection_high; /* 0x3ffe */ |
||||
} ihs_fpga_t; |
||||
#endif |
||||
|
||||
#ifdef CONFIG_IOCON |
||||
typedef struct ihs_fpga { |
||||
u16 reflection_low; /* 0x0000 */ |
||||
u16 versions; /* 0x0002 */ |
||||
u16 fpga_version; /* 0x0004 */ |
||||
u16 fpga_features; /* 0x0006 */ |
||||
u16 reserved_0[6]; /* 0x0008 */ |
||||
ihs_gpio_t gpio; /* 0x0014 */ |
||||
u16 mpc3w_control; /* 0x001a */ |
||||
u16 reserved_1[19]; /* 0x001c */ |
||||
u16 videocontrol; /* 0x0042 */ |
||||
u16 reserved_2[93]; /* 0x0044 */ |
||||
u16 reflection_high; /* 0x00fe */ |
||||
ihs_osd_t osd; /* 0x0100 */ |
||||
u16 reserved_3[892]; /* 0x0108 */ |
||||
u16 videomem; /* 0x0800 */ |
||||
} ihs_fpga_t; |
||||
#endif |
||||
|
||||
#ifdef CONFIG_DLVISION_10G |
||||
typedef struct ihs_fpga { |
||||
u16 reflection_low; /* 0x0000 */ |
||||
u16 versions; /* 0x0002 */ |
||||
u16 fpga_version; /* 0x0004 */ |
||||
u16 fpga_features; /* 0x0006 */ |
||||
u16 reserved_0[10]; /* 0x0008 */ |
||||
u16 extended_interrupt; /* 0x001c */ |
||||
u16 reserved_1[9]; /* 0x001e */ |
||||
ihs_i2c_t i2c; /* 0x0030 */ |
||||
u16 reserved_2[35]; /* 0x0038 */ |
||||
u16 reflection_high; /* 0x007e */ |
||||
u16 reserved_3[15]; /* 0x0080 */ |
||||
u16 videocontrol; /* 0x009e */ |
||||
u16 reserved_4[176]; /* 0x00a0 */ |
||||
ihs_osd_t osd; /* 0x0200 */ |
||||
u16 reserved_5[764]; /* 0x0208 */ |
||||
u16 videomem; /* 0x0800 */ |
||||
} ihs_fpga_t; |
||||
#endif |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue