- added support for arm925t cpu core - added support for TI OMAP 1510 Innovator Boardmaster
wdenk
22 years ago
parent
6dff552972
commit
2e5983d2ea
@ -0,0 +1,47 @@ |
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := omap1510innovator.o flash.o
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SOBJS := platform.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,25 @@ |
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
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# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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#
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# (C) Copyright 2003
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# Texas Instruments, <www.ti.com>
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# Kshitij Gupta <Kshitij@ti.com>
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#
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# TI Innovator board with OMAP1510 (ARM925T) cpu
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# see http://www.ti.com/ for more information on Texas Insturments
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#
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# Innovator has 1 bank of 256 MB SDRAM
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# Physical Address:
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# 1000'0000 to 2000'0000
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#
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#
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# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved)
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#
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# we load ourself to 1100'0000
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#
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#
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TEXT_BASE = 0x11000000
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@ -0,0 +1,428 @@ |
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/*
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* (C) Copyright 2001 |
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
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* |
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* (C) Copyright 2001 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <linux/byteorder/swab.h> |
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#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* Board support for 1 or 2 flash devices */ |
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#undef FLASH_PORT_WIDTH32 |
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#define FLASH_PORT_WIDTH16 |
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#ifdef FLASH_PORT_WIDTH16 |
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#define FLASH_PORT_WIDTH ushort |
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#define FLASH_PORT_WIDTHV vu_short |
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#define SWAP(x) __swab16(x) |
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#else |
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#define FLASH_PORT_WIDTH ulong |
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#define FLASH_PORT_WIDTHV vu_long |
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#define SWAP(x) __swab32(x) |
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#endif |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define mb() __asm__ __volatile__ ("" : : : "memory") |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size (FPW * addr, flash_info_t * info); |
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static int write_data (flash_info_t * info, ulong dest, FPW data); |
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static void flash_get_offsets (ulong base, flash_info_t * info); |
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void inline spin_wheel (void); |
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/*-----------------------------------------------------------------------
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*/ |
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unsigned long flash_init (void) |
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{ |
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int i; |
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ulong size = 0; |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { |
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switch (i) { |
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case 0: |
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flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); |
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flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); |
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break; |
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default: |
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panic ("configured to many flash banks!\n"); |
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break; |
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} |
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size += flash_info[i].size; |
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} |
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/* Protect monitor and environment sectors
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*/ |
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flash_protect ( FLAG_PROTECT_SET, |
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CFG_FLASH_BASE, |
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CFG_FLASH_BASE + monitor_flash_len - 1, |
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&flash_info[0]); |
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flash_protect ( FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, |
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&flash_info[0]); |
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return size; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_get_offsets (ulong base, flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return; |
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} |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { |
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for (i = 0; i < info->sector_count; i++) { |
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info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); |
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info->protect[i] = 0; |
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} |
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} |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t * info) |
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{ |
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int i; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F128J3A: |
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printf ("28F128J3A\n"); |
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break; |
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default: |
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printf ("Unknown Chip Type\n"); |
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break; |
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} |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", |
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info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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return; |
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} |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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static ulong flash_get_size (FPW * addr, flash_info_t * info) |
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{ |
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volatile FPW value; |
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/* Write auto select command: read Manufacturer ID */ |
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addr[0x5555] = (FPW) 0x00AA00AA; |
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addr[0x2AAA] = (FPW) 0x00550055; |
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addr[0x5555] = (FPW) 0x00900090; |
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mb (); |
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value = addr[0]; |
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switch (value) { |
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case (FPW) INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (0); /* no or unknown flash */ |
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} |
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mb (); |
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value = addr[1]; /* device ID */ |
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switch (value) { |
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case (FPW) INTEL_ID_28F128J3A: |
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info->flash_id += FLASH_28F128J3A; |
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info->sector_count = 128; |
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info->size = 0x02000000; |
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break; /* => 16 MB */ |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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break; |
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} |
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if (info->sector_count > CFG_MAX_FLASH_SECT) { |
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printf ("** ERROR: sector count %d > max (%d) **\n", |
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info->sector_count, CFG_MAX_FLASH_SECT); |
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info->sector_count = CFG_MAX_FLASH_SECT; |
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} |
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addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t * info, int s_first, int s_last) |
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{ |
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int flag, prot, sect; |
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ulong type, start, last; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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type = (info->flash_id & FLASH_VENDMASK); |
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if ((type != FLASH_MAN_INTEL)) { |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) { |
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printf ("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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} else { |
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printf ("\n"); |
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} |
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/*start = get_timer (0); */ |
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last = start; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last; sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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FPWV *addr = (FPWV *) (info->start[sect]); |
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FPW status; |
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printf ("Erasing sector %2d ... ", sect); |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked (); |
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*addr = (FPW) 0x00500050; /* clear status register */ |
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*addr = (FPW) 0x00200020; /* erase setup */ |
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*addr = (FPW) 0x00D000D0; /* erase confirm */ |
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while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
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if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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*addr = (FPW) 0x00B000B0; /* suspend erase */ |
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*addr = (FPW) 0x00FF00FF; /* reset to read mode */ |
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rcode = 1; |
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break; |
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} |
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} |
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*addr = (FPW) 0x00500050; /* clear status register cmd. */ |
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*addr = (FPW) 0x00FF00FF; /* resest to read mode */ |
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printf (" done\n"); |
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} |
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} |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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* 4 - Flash not identified |
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*/ |
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp; |
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FPW data; |
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int count, i, l, rc, port_width; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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return 4; |
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} |
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/* get lower word aligned address */ |
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#ifdef FLASH_PORT_WIDTH16 |
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wp = (addr & ~1); |
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port_width = 2; |
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#else |
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wp = (addr & ~3); |
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port_width = 4; |
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#endif |
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i = 0, cp = wp; i < l; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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for (; i < port_width && cnt > 0; ++i) { |
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data = (data << 8) | *src++; |
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--cnt; |
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++cp; |
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} |
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for (; cnt == 0 && i < port_width; ++i, ++cp) { |
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data = (data << 8) | (*(uchar *) cp); |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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} |
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/*
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* handle word aligned part |
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*/ |
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count = 0; |
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while (cnt >= port_width) { |
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data = 0; |
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for (i = 0; i < port_width; ++i) { |
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data = (data << 8) | *src++; |
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} |
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if ((rc = write_data (info, wp, SWAP (data))) != 0) { |
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return (rc); |
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} |
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wp += port_width; |
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cnt -= port_width; |
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if (count++ > 0x800) { |
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spin_wheel (); |
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count = 0; |
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} |
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} |
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if (cnt == 0) { |
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return (0); |
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} |
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/*
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* handle unaligned tail bytes |
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*/ |
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data = 0; |
||||||
|
for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { |
||||||
|
data = (data << 8) | *src++; |
||||||
|
--cnt; |
||||||
|
} |
||||||
|
for (; i < port_width; ++i, ++cp) { |
||||||
|
data = (data << 8) | (*(uchar *) cp); |
||||||
|
} |
||||||
|
|
||||||
|
return (write_data (info, wp, SWAP (data))); |
||||||
|
} |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Write a word or halfword to Flash, returns: |
||||||
|
* 0 - OK |
||||||
|
* 1 - write timeout |
||||||
|
* 2 - Flash not erased |
||||||
|
*/ |
||||||
|
static int write_data (flash_info_t * info, ulong dest, FPW data) |
||||||
|
{ |
||||||
|
FPWV *addr = (FPWV *) dest; |
||||||
|
ulong status; |
||||||
|
int flag; |
||||||
|
|
||||||
|
/* Check if Flash is (sufficiently) erased */ |
||||||
|
if ((*addr & data) != data) { |
||||||
|
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); |
||||||
|
return (2); |
||||||
|
} |
||||||
|
/* Disable interrupts which might cause a timeout here */ |
||||||
|
flag = disable_interrupts (); |
||||||
|
|
||||||
|
*addr = (FPW) 0x00400040; /* write setup */ |
||||||
|
*addr = data; |
||||||
|
|
||||||
|
/* arm simple, non interrupt dependent timer */ |
||||||
|
reset_timer_masked (); |
||||||
|
|
||||||
|
/* wait while polling the status register */ |
||||||
|
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
||||||
|
|
||||||
|
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) { |
||||||
|
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
||||||
|
return (1); |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
||||||
|
|
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
void inline spin_wheel (void) |
||||||
|
{ |
||||||
|
static int p = 0; |
||||||
|
static char w[] = "\\/-"; |
||||||
|
|
||||||
|
printf ("\010%c", w[p]); |
||||||
|
(++p == 3) ? (p = 0) : 0; |
||||||
|
} |
||||||
@ -0,0 +1,131 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2002 |
||||||
|
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||||
|
* Marius Groeger <mgroeger@sysgo.de> |
||||||
|
* |
||||||
|
* (C) Copyright 2002 |
||||||
|
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
||||||
|
* |
||||||
|
* (C) Copyright 2003 |
||||||
|
* Texas Instruments, <www.ti.com> |
||||||
|
* Kshitij Gupta <Kshitij@ti.com> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
|
||||||
|
static void flash__init (void); |
||||||
|
static void ether__init (void); |
||||||
|
|
||||||
|
static inline void delay (unsigned long loops) |
||||||
|
{ |
||||||
|
__asm__ volatile ("1:\n" |
||||||
|
"subs %0, %1, #1\n" |
||||||
|
"bne 1b":"=r" (loops):"0" (loops)); |
||||||
|
} |
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous platform dependent initialisations |
||||||
|
*/ |
||||||
|
|
||||||
|
int board_init (void) |
||||||
|
{ |
||||||
|
DECLARE_GLOBAL_DATA_PTR; |
||||||
|
|
||||||
|
/* arch number of OMAP 1510-Board */ |
||||||
|
gd->bd->bi_arch_number = 234; |
||||||
|
|
||||||
|
/* adress of boot parameters */ |
||||||
|
gd->bd->bi_boot_params = 0x10000100; |
||||||
|
|
||||||
|
/* kk - this speeds up your boot a quite a bit. However to make it
|
||||||
|
* work, you need make sure your kernel startup flush bug is fixed. |
||||||
|
* ... rkw ... |
||||||
|
*/ |
||||||
|
icache_enable (); |
||||||
|
|
||||||
|
flash__init (); |
||||||
|
ether__init (); |
||||||
|
return 0; |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
int misc_init_r (void) |
||||||
|
{ |
||||||
|
/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ |
||||||
|
/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ |
||||||
|
|
||||||
|
/* setup gpio direction to match board (no floats!) */ |
||||||
|
/**gdir = 0xCFF9; */ |
||||||
|
/**mdir = 0x103F; */ |
||||||
|
|
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
/******************************
|
||||||
|
Routine: |
||||||
|
Description: |
||||||
|
******************************/ |
||||||
|
static void flash__init (void) |
||||||
|
{ |
||||||
|
#define CS0_CHIP_SELECT_REG 0xfffecc10 |
||||||
|
#define CS3_CHIP_SELECT_REG 0xfffecc1c |
||||||
|
#define EMIFS_GlB_Config_REG 0xfffecc0c |
||||||
|
|
||||||
|
{ |
||||||
|
unsigned int regval; |
||||||
|
|
||||||
|
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); |
||||||
|
regval = regval | 0x0001; /* Turn off write protection for flash devices. */ |
||||||
|
if (regval & 0x0002) { |
||||||
|
regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ |
||||||
|
/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ |
||||||
|
/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ |
||||||
|
/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ |
||||||
|
} |
||||||
|
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; |
||||||
|
} |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
/******************************
|
||||||
|
Routine: |
||||||
|
Description: |
||||||
|
******************************/ |
||||||
|
static void ether__init (void) |
||||||
|
{ |
||||||
|
#define ETH_CONTROL_REG 0x0800000b |
||||||
|
/* take the Ethernet controller out of reset and wait
|
||||||
|
* for the EEPROM load to complete. |
||||||
|
*/ |
||||||
|
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; |
||||||
|
udelay (3); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
int dram_init (void) |
||||||
|
{ |
||||||
|
DECLARE_GLOBAL_DATA_PTR; |
||||||
|
|
||||||
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||||
|
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||||
|
|
||||||
|
return 0; |
||||||
|
} |
||||||
@ -0,0 +1,386 @@ |
|||||||
|
/* |
||||||
|
* Board specific setup info |
||||||
|
* |
||||||
|
* (C) Copyright 2003 |
||||||
|
* Texas Instruments, <www.ti.com> |
||||||
|
* |
||||||
|
* -- Some bits of code used from rrload's head_OMAP1510.s -- |
||||||
|
* Copyright (C) 2002 RidgeRun, Inc. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <config.h> |
||||||
|
#include <version.h> |
||||||
|
|
||||||
|
#if defined(CONFIG_OMAP1510) |
||||||
|
#include <./configs/omap1510.h> |
||||||
|
#endif |
||||||
|
|
||||||
|
#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK)) |
||||||
|
|
||||||
|
|
||||||
|
_TEXT_BASE: |
||||||
|
.word TEXT_BASE /* sdram load addr from config.mk */ |
||||||
|
|
||||||
|
.globl platformsetup
|
||||||
|
platformsetup: |
||||||
|
|
||||||
|
/* |
||||||
|
* Configure 1510 pins functions to match our board. |
||||||
|
*/ |
||||||
|
ldr r0, REG_PULL_DWN_CTRL_0 |
||||||
|
ldr r1, VAL_PULL_DWN_CTRL_0 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_PULL_DWN_CTRL_1 |
||||||
|
ldr r1, VAL_PULL_DWN_CTRL_1 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_PULL_DWN_CTRL_2 |
||||||
|
ldr r1, VAL_PULL_DWN_CTRL_2 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_PULL_DWN_CTRL_3 |
||||||
|
ldr r1, VAL_PULL_DWN_CTRL_3 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_4 |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_4 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_5 |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_5 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_6 |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_6 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_7 |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_7 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_8 |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_8 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_9 |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_9 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_A |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_A |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_B |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_B |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_FUNC_MUX_CTRL_C |
||||||
|
ldr r1, VAL_FUNC_MUX_CTRL_C |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_VOLTAGE_CTRL_0 |
||||||
|
ldr r1, VAL_VOLTAGE_CTRL_0 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_TEST_DBG_CTRL_0 |
||||||
|
ldr r1, VAL_TEST_DBG_CTRL_0 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_MOD_CONF_CTRL_0 |
||||||
|
ldr r1, VAL_MOD_CONF_CTRL_0 |
||||||
|
str r1, [r0] |
||||||
|
|
||||||
|
/* Move to 1510 mode */ |
||||||
|
ldr r0, REG_COMP_MODE_CTRL_0 |
||||||
|
ldr r1, VAL_COMP_MODE_CTRL_0 |
||||||
|
str r1, [r0] |
||||||
|
|
||||||
|
/* Set up Traffic Ctlr*/ |
||||||
|
ldr r0, REG_TC_IMIF_PRIO |
||||||
|
mov r1, #0x0 |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_TC_EMIFS_PRIO |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, REG_TC_EMIFF_PRIO |
||||||
|
str r1, [r0] |
||||||
|
|
||||||
|
ldr r0, REG_TC_EMIFS_CONFIG |
||||||
|
ldr r1, [r0] |
||||||
|
bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ |
||||||
|
bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ |
||||||
|
str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */ |
||||||
|
|
||||||
|
/* Setup some clock domains */ |
||||||
|
ldr r1, =OMAP1510_CLKS |
||||||
|
ldr r0, REG_ARM_IDLECT2 |
||||||
|
strh r1, [r0] /* CLKM, Clock domain control. */ |
||||||
|
|
||||||
|
mov r1, #0x01 /* PER_EN bit */ |
||||||
|
ldr r0, REG_ARM_RSTCT2 |
||||||
|
strh r1, [r0] /* CLKM; Peripheral reset. */
|
||||||
|
|
||||||
|
/* Set CLKM to Sync-Scalable */ |
||||||
|
/* I supposidly need to enable the dsp clock before switching */ |
||||||
|
mov r1, #0x1000 |
||||||
|
ldr r0, REG_ARM_SYSST |
||||||
|
strh r1, [r0] |
||||||
|
mov r0, #0x400 |
||||||
|
1: |
||||||
|
subs r0, r0, #0x1 /* wait for any bubbles to finish */ |
||||||
|
bne 1b |
||||||
|
|
||||||
|
ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */ |
||||||
|
ldr r0, REG_ARM_CKCTL |
||||||
|
strh r1, [r0] |
||||||
|
|
||||||
|
/* setup DPLL 1 */ |
||||||
|
ldr r1, VAL_DPLL1_CTL |
||||||
|
ldr r0, REG_DPLL1_CTL |
||||||
|
strh r1, [r0] |
||||||
|
ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
||||||
|
beq lock_end /* Do not look for lock if BYPASS selected */ |
||||||
|
2: |
||||||
|
ldrh r1, [r0] |
||||||
|
ands r1, r1, #0x01 /* Check the LOCK bit. */ |
||||||
|
beq 2b /* ...loop until bit goes hi. */ |
||||||
|
lock_end: |
||||||
|
|
||||||
|
/* Set memory timings corresponding to the new clock speed */ |
||||||
|
|
||||||
|
/* Check execution location to determine current execution location |
||||||
|
* and branch to appropriate initialization code. |
||||||
|
*/ |
||||||
|
mov r0, #0x10000000 /* Load physical SDRAM base. */ |
||||||
|
mov r1, pc /* Get current execution location. */ |
||||||
|
cmp r1, r0 /* Compare. */ |
||||||
|
bge skip_sdram /* Skip over EMIF-fast initialization if running from SDRAM. */ |
||||||
|
|
||||||
|
/* |
||||||
|
* Delay for SDRAM initialization. |
||||||
|
*/ |
||||||
|
mov r3, #0x1800 /* value should be checked */ |
||||||
|
3: |
||||||
|
subs r3, r3, #0x1 /* Decrement count */ |
||||||
|
bne 3b |
||||||
|
|
||||||
|
/* |
||||||
|
* Set SDRAM control values. Disable refresh before MRS command. |
||||||
|
*/ |
||||||
|
ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */ |
||||||
|
bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */ |
||||||
|
orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */ |
||||||
|
orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */ |
||||||
|
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
||||||
|
str r3, [r2] /* Store the passed value with AR disabled. */ |
||||||
|
|
||||||
|
ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */ |
||||||
|
ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */ |
||||||
|
str r1, [r2] /* Store the passed value.*/ |
||||||
|
|
||||||
|
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
||||||
|
str r0, [r2] /* Store the passed value. */ |
||||||
|
|
||||||
|
/* |
||||||
|
* Delay for SDRAM initialization. |
||||||
|
*/ |
||||||
|
mov r3, #0x1800 |
||||||
|
4: |
||||||
|
subs r3, r3, #1 /* Decrement count. */ |
||||||
|
bne 4b |
||||||
|
|
||||||
|
skip_sdram: |
||||||
|
|
||||||
|
/* slow interface */ |
||||||
|
ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
||||||
|
ldr r0, REG_TC_EMIFS_CS0_CONFIG |
||||||
|
str r1, [r0] /* Chip Select 0 */ |
||||||
|
ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
||||||
|
ldr r0, REG_TC_EMIFS_CS1_CONFIG |
||||||
|
str r1, [r0] /* Chip Select 1 */ |
||||||
|
ldr r1, VAL_TC_EMIFS_CS2_CONFIG |
||||||
|
ldr r0, REG_TC_EMIFS_CS2_CONFIG |
||||||
|
str r1, [r0] /* Chip Select 2 */ |
||||||
|
ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
||||||
|
ldr r0, REG_TC_EMIFS_CS3_CONFIG |
||||||
|
str r1, [r0] /* Chip Select 3 */ |
||||||
|
|
||||||
|
/* Next, Enable the RS232 Line Drivers in the FPGA. */ |
||||||
|
/* Also, power on the audio CODEC's amplifier here, */ |
||||||
|
/* which will make a noise on the audio output. */ |
||||||
|
/* This is done here instead of in the kernel so there */ |
||||||
|
/* isn't a loud popping noise at the start of each */ |
||||||
|
/* song. */ |
||||||
|
/* Also, disable the CODEC's clocks. */ |
||||||
|
/* omap1510-HelenP1 [specific] */ |
||||||
|
|
||||||
|
ldr r0, REG_FPGA_POWER |
||||||
|
mov r1, #0 |
||||||
|
ldr r2, REG_FPGA_DIP_SWITCH |
||||||
|
ldrb r3, [r2] |
||||||
|
cmp r3, #0x8 |
||||||
|
movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */ |
||||||
|
strb r1, [r0] |
||||||
|
ldr r0, REG_FPGA_AUDIO |
||||||
|
mov r1, #0x0 /* Disable sound driver (CODEC clocks) */ |
||||||
|
strb r1, [r0] |
||||||
|
|
||||||
|
/* back to arch calling code */ |
||||||
|
mov pc, lr |
||||||
|
|
||||||
|
/* the literal pools origin */ |
||||||
|
.ltorg |
||||||
|
|
||||||
|
/* OMAP configuration registers */ |
||||||
|
REG_FUNC_MUX_CTRL_0: /* 32 bits */ |
||||||
|
.word 0xfffe1000
|
||||||
|
REG_FUNC_MUX_CTRL_1: /* 32 bits */ |
||||||
|
.word 0xfffe1004
|
||||||
|
REG_FUNC_MUX_CTRL_2: /* 32 bits */ |
||||||
|
.word 0xfffe1008
|
||||||
|
REG_COMP_MODE_CTRL_0: /* 32 bits */ |
||||||
|
.word 0xfffe100c
|
||||||
|
REG_FUNC_MUX_CTRL_3: /* 32 bits */ |
||||||
|
.word 0xfffe1010
|
||||||
|
REG_FUNC_MUX_CTRL_4: /* 32 bits */ |
||||||
|
.word 0xfffe1014
|
||||||
|
REG_FUNC_MUX_CTRL_5: /* 32 bits */ |
||||||
|
.word 0xfffe1018
|
||||||
|
REG_FUNC_MUX_CTRL_6: /* 32 bits */ |
||||||
|
.word 0xfffe101c
|
||||||
|
REG_FUNC_MUX_CTRL_7: /* 32 bits */ |
||||||
|
.word 0xfffe1020
|
||||||
|
REG_FUNC_MUX_CTRL_8: /* 32 bits */ |
||||||
|
.word 0xfffe1024
|
||||||
|
REG_FUNC_MUX_CTRL_9: /* 32 bits */ |
||||||
|
.word 0xfffe1028
|
||||||
|
REG_FUNC_MUX_CTRL_A: /* 32 bits */ |
||||||
|
.word 0xfffe102C
|
||||||
|
REG_FUNC_MUX_CTRL_B: /* 32 bits */ |
||||||
|
.word 0xfffe1030
|
||||||
|
REG_FUNC_MUX_CTRL_C: /* 32 bits */ |
||||||
|
.word 0xfffe1034
|
||||||
|
REG_FUNC_MUX_CTRL_D: /* 32 bits */ |
||||||
|
.word 0xfffe1038
|
||||||
|
REG_PULL_DWN_CTRL_0: /* 32 bits */ |
||||||
|
.word 0xfffe1040
|
||||||
|
REG_PULL_DWN_CTRL_1: /* 32 bits */ |
||||||
|
.word 0xfffe1044
|
||||||
|
REG_PULL_DWN_CTRL_2: /* 32 bits */ |
||||||
|
.word 0xfffe1048
|
||||||
|
REG_PULL_DWN_CTRL_3: /* 32 bits */ |
||||||
|
.word 0xfffe104c
|
||||||
|
REG_VOLTAGE_CTRL_0: /* 32 bits */ |
||||||
|
.word 0xfffe1060
|
||||||
|
REG_TEST_DBG_CTRL_0: /* 32 bits */ |
||||||
|
.word 0xfffe1070
|
||||||
|
REG_MOD_CONF_CTRL_0: /* 32 bits */ |
||||||
|
.word 0xfffe1080
|
||||||
|
REG_TC_IMIF_PRIO: /* 32 bits */ |
||||||
|
.word 0xfffecc00
|
||||||
|
REG_TC_EMIFS_PRIO: /* 32 bits */ |
||||||
|
.word 0xfffecc04
|
||||||
|
REG_TC_EMIFF_PRIO: /* 32 bits */ |
||||||
|
.word 0xfffecc08
|
||||||
|
REG_TC_EMIFS_CONFIG: /* 32 bits */ |
||||||
|
.word 0xfffecc0c
|
||||||
|
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
||||||
|
.word 0xfffecc10
|
||||||
|
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
||||||
|
.word 0xfffecc14
|
||||||
|
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
||||||
|
.word 0xfffecc18
|
||||||
|
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
||||||
|
.word 0xfffecc1c
|
||||||
|
REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */ |
||||||
|
.word 0xfffecc20
|
||||||
|
REG_TC_EMIFF_MRS: /* 32 bits */ |
||||||
|
.word 0xfffecc24
|
||||||
|
/* MPU clock/reset/power mode control registers */ |
||||||
|
REG_ARM_CKCTL: /* 16 bits */ |
||||||
|
.word 0xfffece00
|
||||||
|
REG_ARM_IDLECT2: /* 16 bits */ |
||||||
|
.word 0xfffece08
|
||||||
|
REG_ARM_RSTCT2: /* 16 bits */ |
||||||
|
.word 0xfffece14
|
||||||
|
REG_ARM_SYSST: /* 16 bits */ |
||||||
|
.word 0xfffece18
|
||||||
|
/* DPLL control registers */ |
||||||
|
REG_DPLL1_CTL: /* 16 bits */ |
||||||
|
.word 0xfffecf00
|
||||||
|
/* identification code register */ |
||||||
|
REG_IDCODE: /* 32 bits */ |
||||||
|
.word 0xfffed404
|
||||||
|
|
||||||
|
/* Innovator specific */ |
||||||
|
REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */ |
||||||
|
.word 0x08000003
|
||||||
|
REG_FPGA_POWER: /* 8 bits */ |
||||||
|
.word 0x08000005
|
||||||
|
REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */ |
||||||
|
.word 0x0800000c
|
||||||
|
REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */ |
||||||
|
.word 0x0800000e
|
||||||
|
|
||||||
|
VAL_COMP_MODE_CTRL_0: |
||||||
|
.word 0x0000eaef
|
||||||
|
VAL_FUNC_MUX_CTRL_4: |
||||||
|
.word 0x00000000
|
||||||
|
VAL_FUNC_MUX_CTRL_5: |
||||||
|
.word 0x00000000
|
||||||
|
VAL_FUNC_MUX_CTRL_6: |
||||||
|
.word 0x00000001
|
||||||
|
VAL_FUNC_MUX_CTRL_7: |
||||||
|
.word 0x00000000
|
||||||
|
VAL_FUNC_MUX_CTRL_8: |
||||||
|
.word 0x10001200
|
||||||
|
VAL_FUNC_MUX_CTRL_9: |
||||||
|
.word 0x01201012
|
||||||
|
VAL_FUNC_MUX_CTRL_A: |
||||||
|
.word 0x00000248
|
||||||
|
VAL_FUNC_MUX_CTRL_B: |
||||||
|
.word 0x00000248
|
||||||
|
VAL_FUNC_MUX_CTRL_C: |
||||||
|
.word 0x09000000
|
||||||
|
VAL_FUNC_MUX_CTRL_D: |
||||||
|
.word 0x00000000
|
||||||
|
VAL_PULL_DWN_CTRL_0: |
||||||
|
.word 0x11a10000
|
||||||
|
VAL_PULL_DWN_CTRL_1: |
||||||
|
.word 0x2e047fff
|
||||||
|
VAL_PULL_DWN_CTRL_2: |
||||||
|
.word 0xffd7d3e6
|
||||||
|
VAL_PULL_DWN_CTRL_3: |
||||||
|
.word 0x00003f03
|
||||||
|
VAL_VOLTAGE_CTRL_0: |
||||||
|
.word 0x00000007
|
||||||
|
VAL_TEST_DBG_CTRL_0: |
||||||
|
/* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 . |
||||||
|
* This slows down internal SRAM accesses. |
||||||
|
*/ |
||||||
|
.word 0x00000007
|
||||||
|
VAL_MOD_CONF_CTRL_0: |
||||||
|
.word 0x0b000008
|
||||||
|
VAL_ARM_CKCTL: |
||||||
|
.word 0x010f
|
||||||
|
VAL_DPLL1_CTL: |
||||||
|
.word 0x2710
|
||||||
|
VAL_TC_EMIFS_CS1_CONFIG_PRELIM: |
||||||
|
.word 0x00001149
|
||||||
|
VAL_TC_EMIFS_CS2_CONFIG_PRELIM: |
||||||
|
.word 0x00004158
|
||||||
|
VAL_TC_EMIFS_CS0_CONFIG: |
||||||
|
.word 0x002130b0
|
||||||
|
VAL_TC_EMIFS_CS1_CONFIG: |
||||||
|
.word 0x0000f559
|
||||||
|
VAL_TC_EMIFS_CS2_CONFIG: |
||||||
|
.word 0x000055f0
|
||||||
|
VAL_TC_EMIFS_CS3_CONFIG: |
||||||
|
.word 0x00003331
|
||||||
|
VAL_TC_EMIFF_SDRAM_CONFIG: |
||||||
|
.word 0x010290fc
|
||||||
|
VAL_TC_EMIFF_MRS: |
||||||
|
.word 0x00000027
|
||||||
@ -0,0 +1,58 @@ |
|||||||
|
/* |
||||||
|
* (C) Copyright 2002 |
||||||
|
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||||
|
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ |
||||||
|
OUTPUT_ARCH(arm) |
||||||
|
ENTRY(_start) |
||||||
|
SECTIONS |
||||||
|
{ |
||||||
|
. = 0x00000000; |
||||||
|
|
||||||
|
. = ALIGN(4); |
||||||
|
.text : |
||||||
|
{ |
||||||
|
cpu/arm925t/start.o (.text) |
||||||
|
*(.text) |
||||||
|
} |
||||||
|
|
||||||
|
. = ALIGN(4); |
||||||
|
.rodata : { *(.rodata) } |
||||||
|
|
||||||
|
. = ALIGN(4); |
||||||
|
.data : { *(.data) } |
||||||
|
|
||||||
|
. = ALIGN(4); |
||||||
|
.got : { *(.got) } |
||||||
|
|
||||||
|
__u_boot_cmd_start = .; |
||||||
|
.u_boot_cmd : { *(.u_boot_cmd) } |
||||||
|
__u_boot_cmd_end = .; |
||||||
|
|
||||||
|
armboot_end_data = .; |
||||||
|
|
||||||
|
. = ALIGN(4); |
||||||
|
.bss : { *(.bss) } |
||||||
|
|
||||||
|
armboot_end = .; |
||||||
|
} |
||||||
@ -0,0 +1,43 @@ |
|||||||
|
#
|
||||||
|
# (C) Copyright 2000-2003
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
include $(TOPDIR)/config.mk |
||||||
|
|
||||||
|
LIB = lib$(CPU).a
|
||||||
|
|
||||||
|
START = start.o
|
||||||
|
OBJS = interrupts.o cpu.o omap925.o
|
||||||
|
|
||||||
|
all: .depend $(START) $(LIB) |
||||||
|
|
||||||
|
$(LIB): $(OBJS) |
||||||
|
$(AR) crv $@ $(OBJS)
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) |
||||||
|
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
|
||||||
|
|
||||||
|
sinclude .depend |
||||||
|
|
||||||
|
#########################################################################
|
||||||
@ -0,0 +1,27 @@ |
|||||||
|
#
|
||||||
|
# (C) Copyright 2002
|
||||||
|
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||||
|
-mshort-load-bytes -msoft-float
|
||||||
|
|
||||||
|
PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4
|
||||||
@ -0,0 +1,159 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2002 |
||||||
|
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||||
|
* Marius Groeger <mgroeger@sysgo.de> |
||||||
|
* |
||||||
|
* (C) Copyright 2002 |
||||||
|
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
/*
|
||||||
|
* CPU specific code |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <command.h> |
||||||
|
#include <arm925t.h> |
||||||
|
|
||||||
|
/* read co-processor 15, register #1 (control register) */ |
||||||
|
static unsigned long read_p15_c1 (void) |
||||||
|
{ |
||||||
|
unsigned long value; |
||||||
|
|
||||||
|
__asm__ __volatile__( |
||||||
|
"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" |
||||||
|
: "=r" (value) |
||||||
|
: |
||||||
|
: "memory"); |
||||||
|
|
||||||
|
#ifdef MMU_DEBUG |
||||||
|
printf ("p15/c1 is = %08lx\n", value); |
||||||
|
#endif |
||||||
|
return value; |
||||||
|
} |
||||||
|
|
||||||
|
/* write to co-processor 15, register #1 (control register) */ |
||||||
|
static void write_p15_c1 (unsigned long value) |
||||||
|
{ |
||||||
|
#ifdef MMU_DEBUG |
||||||
|
printf ("write %08lx to p15/c1\n", value); |
||||||
|
#endif |
||||||
|
__asm__ __volatile__( |
||||||
|
"mcr p15, 0, %0, c1, c0, 0 @ write it back\n" |
||||||
|
: |
||||||
|
: "r" (value) |
||||||
|
: "memory"); |
||||||
|
|
||||||
|
read_p15_c1 (); |
||||||
|
} |
||||||
|
|
||||||
|
static void cp_delay (void) |
||||||
|
{ |
||||||
|
volatile int i; |
||||||
|
|
||||||
|
/* Many OMAP regs need at least 2 nops */ |
||||||
|
for (i = 0; i < 100; i++); |
||||||
|
} |
||||||
|
|
||||||
|
/* See also ARM Ref. Man. */ |
||||||
|
#define C1_MMU (1<<0) /* mmu off/on */ |
||||||
|
#define C1_ALIGN (1<<1) /* alignment faults off/on */ |
||||||
|
#define C1_DC (1<<2) /* dcache off/on */ |
||||||
|
#define C1_WB (1<<3) /* merging write buffer on/off */ |
||||||
|
#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ |
||||||
|
#define C1_SYS_PROT (1<<8) /* system protection */ |
||||||
|
#define C1_ROM_PROT (1<<9) /* ROM protection */ |
||||||
|
#define C1_IC (1<<12) /* icache off/on */ |
||||||
|
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ |
||||||
|
#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ |
||||||
|
|
||||||
|
int cpu_init (void) |
||||||
|
{ |
||||||
|
/*
|
||||||
|
* setup up stack if necessary |
||||||
|
*/ |
||||||
|
#ifdef CONFIG_USE_IRQ |
||||||
|
IRQ_STACK_START = _armboot_end + |
||||||
|
CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4; |
||||||
|
FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; |
||||||
|
_armboot_real_end = FIQ_STACK_START + 4; |
||||||
|
#else |
||||||
|
_armboot_real_end = _armboot_end + CONFIG_STACKSIZE; |
||||||
|
#endif /* CONFIG_USE_IRQ */ |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
int cleanup_before_linux (void) |
||||||
|
{ |
||||||
|
/*
|
||||||
|
* this function is called just before we call linux |
||||||
|
* it prepares the processor for linux |
||||||
|
* |
||||||
|
* we turn off caches etc ... |
||||||
|
*/ |
||||||
|
|
||||||
|
unsigned long i; |
||||||
|
|
||||||
|
disable_interrupts (); |
||||||
|
|
||||||
|
/* turn off I/D-cache */ |
||||||
|
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); |
||||||
|
i &= ~(C1_DC | C1_IC); |
||||||
|
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); |
||||||
|
|
||||||
|
/* flush I/D-cache */ |
||||||
|
i = 0; |
||||||
|
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||||
|
{ |
||||||
|
extern void reset_cpu (ulong addr); |
||||||
|
|
||||||
|
disable_interrupts (); |
||||||
|
reset_cpu (0); |
||||||
|
/*NOTREACHED*/ |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
void icache_enable (void) |
||||||
|
{ |
||||||
|
ulong reg; |
||||||
|
|
||||||
|
reg = read_p15_c1 (); /* get control reg. */ |
||||||
|
cp_delay (); |
||||||
|
write_p15_c1 (reg | C1_IC); |
||||||
|
} |
||||||
|
|
||||||
|
void icache_disable (void) |
||||||
|
{ |
||||||
|
ulong reg; |
||||||
|
|
||||||
|
reg = read_p15_c1 (); |
||||||
|
cp_delay (); |
||||||
|
write_p15_c1 (reg & ~C1_IC); |
||||||
|
} |
||||||
|
|
||||||
|
int icache_status (void) |
||||||
|
{ |
||||||
|
return (read_p15_c1 () & C1_IC) != 0; |
||||||
|
} |
||||||
@ -0,0 +1,301 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2003 |
||||||
|
* Texas Instruments, <www.ti.com> |
||||||
|
* |
||||||
|
* (C) Copyright 2002 |
||||||
|
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||||
|
* Marius Groeger <mgroeger@sysgo.de> |
||||||
|
* |
||||||
|
* (C) Copyright 2002 |
||||||
|
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||||
|
* Alex Zuepke <azu@sysgo.de> |
||||||
|
* |
||||||
|
* (C) Copyright 2002 |
||||||
|
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <arm925t.h> |
||||||
|
#include <configs/omap1510.h> |
||||||
|
|
||||||
|
#include <asm/proc-armv/ptrace.h> |
||||||
|
|
||||||
|
extern void reset_cpu(ulong addr); |
||||||
|
#define TIMER_LOAD_VAL 0xffffffff |
||||||
|
|
||||||
|
/* macro to read the 32 bit timer */ |
||||||
|
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8)) |
||||||
|
|
||||||
|
#ifdef CONFIG_USE_IRQ |
||||||
|
/* enable IRQ interrupts */ |
||||||
|
void enable_interrupts (void) |
||||||
|
{ |
||||||
|
unsigned long temp; |
||||||
|
__asm__ __volatile__("mrs %0, cpsr\n" |
||||||
|
"bic %0, %0, #0x80\n" |
||||||
|
"msr cpsr_c, %0" |
||||||
|
: "=r" (temp) |
||||||
|
: |
||||||
|
: "memory"); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* disable IRQ/FIQ interrupts |
||||||
|
* returns true if interrupts had been enabled before we disabled them |
||||||
|
*/ |
||||||
|
int disable_interrupts (void) |
||||||
|
{ |
||||||
|
unsigned long old,temp; |
||||||
|
__asm__ __volatile__("mrs %0, cpsr\n" |
||||||
|
"orr %1, %0, #0xc0\n" |
||||||
|
"msr cpsr_c, %1" |
||||||
|
: "=r" (old), "=r" (temp) |
||||||
|
: |
||||||
|
: "memory"); |
||||||
|
return (old & 0x80) == 0; |
||||||
|
} |
||||||
|
#else |
||||||
|
void enable_interrupts (void) |
||||||
|
{ |
||||||
|
return; |
||||||
|
} |
||||||
|
int disable_interrupts (void) |
||||||
|
{ |
||||||
|
return 0; |
||||||
|
} |
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void bad_mode (void) |
||||||
|
{ |
||||||
|
panic ("Resetting CPU ...\n"); |
||||||
|
reset_cpu (0); |
||||||
|
} |
||||||
|
|
||||||
|
void show_regs (struct pt_regs *regs) |
||||||
|
{ |
||||||
|
unsigned long flags; |
||||||
|
const char *processor_modes[] = { |
||||||
|
"USER_26", "FIQ_26", "IRQ_26", "SVC_26", |
||||||
|
"UK4_26", "UK5_26", "UK6_26", "UK7_26", |
||||||
|
"UK8_26", "UK9_26", "UK10_26", "UK11_26", |
||||||
|
"UK12_26", "UK13_26", "UK14_26", "UK15_26", |
||||||
|
"USER_32", "FIQ_32", "IRQ_32", "SVC_32", |
||||||
|
"UK4_32", "UK5_32", "UK6_32", "ABT_32", |
||||||
|
"UK8_32", "UK9_32", "UK10_32", "UND_32", |
||||||
|
"UK12_32", "UK13_32", "UK14_32", "SYS_32", |
||||||
|
}; |
||||||
|
|
||||||
|
flags = condition_codes (regs); |
||||||
|
|
||||||
|
printf ("pc : [<%08lx>] lr : [<%08lx>]\n" |
||||||
|
"sp : %08lx ip : %08lx fp : %08lx\n", |
||||||
|
instruction_pointer (regs), |
||||||
|
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); |
||||||
|
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", |
||||||
|
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); |
||||||
|
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", |
||||||
|
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); |
||||||
|
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", |
||||||
|
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); |
||||||
|
printf ("Flags: %c%c%c%c", |
||||||
|
flags & CC_N_BIT ? 'N' : 'n', |
||||||
|
flags & CC_Z_BIT ? 'Z' : 'z', |
||||||
|
flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); |
||||||
|
printf (" IRQs %s FIQs %s Mode %s%s\n", |
||||||
|
interrupts_enabled (regs) ? "on" : "off", |
||||||
|
fast_interrupts_enabled (regs) ? "on" : "off", |
||||||
|
processor_modes[processor_mode (regs)], |
||||||
|
thumb_mode (regs) ? " (T)" : ""); |
||||||
|
} |
||||||
|
|
||||||
|
void do_undefined_instruction (struct pt_regs *pt_regs) |
||||||
|
{ |
||||||
|
printf ("undefined instruction\n"); |
||||||
|
show_regs (pt_regs); |
||||||
|
bad_mode (); |
||||||
|
} |
||||||
|
|
||||||
|
void do_software_interrupt (struct pt_regs *pt_regs) |
||||||
|
{ |
||||||
|
printf ("software interrupt\n"); |
||||||
|
show_regs (pt_regs); |
||||||
|
bad_mode (); |
||||||
|
} |
||||||
|
|
||||||
|
void do_prefetch_abort (struct pt_regs *pt_regs) |
||||||
|
{ |
||||||
|
printf ("prefetch abort\n"); |
||||||
|
show_regs (pt_regs); |
||||||
|
bad_mode (); |
||||||
|
} |
||||||
|
|
||||||
|
void do_data_abort (struct pt_regs *pt_regs) |
||||||
|
{ |
||||||
|
printf ("data abort\n"); |
||||||
|
show_regs (pt_regs); |
||||||
|
bad_mode (); |
||||||
|
} |
||||||
|
|
||||||
|
void do_not_used (struct pt_regs *pt_regs) |
||||||
|
{ |
||||||
|
printf ("not used\n"); |
||||||
|
show_regs (pt_regs); |
||||||
|
bad_mode (); |
||||||
|
} |
||||||
|
|
||||||
|
void do_fiq (struct pt_regs *pt_regs) |
||||||
|
{ |
||||||
|
printf ("fast interrupt request\n"); |
||||||
|
show_regs (pt_regs); |
||||||
|
bad_mode (); |
||||||
|
} |
||||||
|
|
||||||
|
void do_irq (struct pt_regs *pt_regs) |
||||||
|
{ |
||||||
|
printf ("interrupt request\n"); |
||||||
|
show_regs (pt_regs); |
||||||
|
bad_mode (); |
||||||
|
} |
||||||
|
|
||||||
|
static ulong timestamp; |
||||||
|
static ulong lastdec; |
||||||
|
|
||||||
|
/* nothing really to do with interrupts, just starts up a counter. */ |
||||||
|
int interrupt_init (void) |
||||||
|
{ |
||||||
|
int32_t val; |
||||||
|
|
||||||
|
*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL; |
||||||
|
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT); |
||||||
|
*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val; |
||||||
|
return (0); |
||||||
|
} |
||||||
|
|
||||||
|
/*
|
||||||
|
* timer without interrupts |
||||||
|
*/ |
||||||
|
|
||||||
|
void reset_timer (void) |
||||||
|
{ |
||||||
|
reset_timer_masked (); |
||||||
|
} |
||||||
|
|
||||||
|
ulong get_timer (ulong base) |
||||||
|
{ |
||||||
|
return get_timer_masked () - base; |
||||||
|
} |
||||||
|
|
||||||
|
void set_timer (ulong t) |
||||||
|
{ |
||||||
|
timestamp = t; |
||||||
|
} |
||||||
|
|
||||||
|
/* very rough timer... */ |
||||||
|
void udelay (unsigned long usec) |
||||||
|
{ |
||||||
|
#ifdef CONFIG_INNOVATOROMAP1510 |
||||||
|
#define LOOPS_PER_MSEC 60 /* tuned on omap1510 */ |
||||||
|
volatile int i, time_remaining = LOOPS_PER_MSEC * usec; |
||||||
|
|
||||||
|
for (i = time_remaining; i > 0; i--) { |
||||||
|
} |
||||||
|
#else |
||||||
|
|
||||||
|
ulong tmo; |
||||||
|
|
||||||
|
tmo = usec / 1000; |
||||||
|
tmo *= CFG_HZ; |
||||||
|
tmo /= 1000; |
||||||
|
|
||||||
|
tmo += get_timer (0); |
||||||
|
|
||||||
|
while (get_timer_masked () < tmo) |
||||||
|
/*NOP*/; |
||||||
|
#endif |
||||||
|
} |
||||||
|
|
||||||
|
void reset_timer_masked (void) |
||||||
|
{ |
||||||
|
/* reset time */ |
||||||
|
lastdec = READ_TIMER; |
||||||
|
timestamp = 0; |
||||||
|
} |
||||||
|
|
||||||
|
ulong get_timer_masked (void) |
||||||
|
{ |
||||||
|
ulong now = READ_TIMER; /* current tick value */ |
||||||
|
|
||||||
|
if (lastdec >= now) { /* did I roll (rem decrementer) */ |
||||||
|
/* normal mode */ |
||||||
|
timestamp += lastdec - now; /* record amount of time since last check */ |
||||||
|
} else { |
||||||
|
/* we have an overflow ... */ |
||||||
|
timestamp += lastdec + TIMER_LOAD_VAL - now; |
||||||
|
} |
||||||
|
lastdec = now; |
||||||
|
|
||||||
|
return timestamp; |
||||||
|
} |
||||||
|
|
||||||
|
void udelay_masked (unsigned long usec) |
||||||
|
{ |
||||||
|
#ifdef CONFIG_INNOVATOROMAP1510 |
||||||
|
#define LOOPS_PER_MSEC 60 /* tuned on omap1510 */ |
||||||
|
volatile int i, time_remaining = LOOPS_PER_MSEC*usec; |
||||||
|
for (i=time_remaining; i>0; i--) { } |
||||||
|
#else |
||||||
|
|
||||||
|
ulong tmo; |
||||||
|
|
||||||
|
tmo = usec / 1000; |
||||||
|
tmo *= CFG_HZ; |
||||||
|
tmo /= 1000; |
||||||
|
|
||||||
|
reset_timer_masked (); |
||||||
|
|
||||||
|
while (get_timer_masked () < tmo) |
||||||
|
/*NOP*/; |
||||||
|
#endif |
||||||
|
} |
||||||
|
|
||||||
|
/*
|
||||||
|
* This function is derived from PowerPC code (read timebase as long long). |
||||||
|
* On ARM it just returns the timer value. |
||||||
|
*/ |
||||||
|
unsigned long long get_ticks(void) |
||||||
|
{ |
||||||
|
return get_timer(0); |
||||||
|
} |
||||||
|
|
||||||
|
/*
|
||||||
|
* This function is derived from PowerPC code (timebase clock frequency). |
||||||
|
* On ARM it returns the number of timer ticks per second. |
||||||
|
*/ |
||||||
|
ulong get_tbclk (void) |
||||||
|
{ /* poor timer, may need to improve especiall for bootp. */ |
||||||
|
ulong tbclk; |
||||||
|
|
||||||
|
tbclk = CFG_HZ; |
||||||
|
return tbclk; |
||||||
|
} |
||||||
@ -0,0 +1,73 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2003 |
||||||
|
* Texas Instruments <www.ti.com> |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <common.h> |
||||||
|
#include <command.h> |
||||||
|
#include <arm925t.h> |
||||||
|
|
||||||
|
ushort gpioreserved; |
||||||
|
|
||||||
|
void gpioreserve(ushort mask) |
||||||
|
{ |
||||||
|
gpioreserved |= mask; |
||||||
|
} |
||||||
|
|
||||||
|
void gpiosetdir(ushort mask, ushort in) |
||||||
|
{ |
||||||
|
*(ushort *)GPIO_DIR_CONTROL_REG = (*(ushort *)GPIO_DIR_CONTROL_REG & ~mask) | (in & mask); |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
void gpiosetout(ushort mask, ushort out) |
||||||
|
{ |
||||||
|
ushort *r_ptr, r_val; |
||||||
|
|
||||||
|
r_ptr = (ushort *)GPIO_DATA_OUTPUT_REG; /* set pointer */ |
||||||
|
r_val = *r_ptr & ~mask; /* get previous val, clear bits we want to change */ |
||||||
|
r_val |= (out & mask); /* set specified bits in value + plus origional ones */ |
||||||
|
*r_ptr = r_val; /* write it out */
|
||||||
|
/*
|
||||||
|
* gcc screwed this one up :(. |
||||||
|
*
|
||||||
|
* *(ushort *)GPIO_DATA_OUTPUT_REG = (*(ushort *)GPIO_DATA_OUTPUT_REG & ~mask) | (out & mask); |
||||||
|
*/ |
||||||
|
|
||||||
|
} |
||||||
|
|
||||||
|
void gpioinit(void) |
||||||
|
{ |
||||||
|
} |
||||||
|
|
||||||
|
|
||||||
|
#define MIF_CONFIG_REG 0xFFFECC0C |
||||||
|
#define FLASH_GLOBAL_CTRL_NWP 1 |
||||||
|
|
||||||
|
void archflashwp (void *archdata, int wp) |
||||||
|
{ |
||||||
|
ulong *fgc = (ulong *) MIF_CONFIG_REG; |
||||||
|
|
||||||
|
if (wp == 1) |
||||||
|
*fgc &= ~FLASH_GLOBAL_CTRL_NWP; |
||||||
|
else |
||||||
|
*fgc |= FLASH_GLOBAL_CTRL_NWP; |
||||||
|
} |
||||||
@ -0,0 +1,424 @@ |
|||||||
|
/* |
||||||
|
* armboot - Startup Code for ARM925 CPU-core |
||||||
|
* |
||||||
|
* Copyright (c) 2003 Texas Instruments |
||||||
|
* |
||||||
|
* ----- Adapted for OMAP1510 from ARM920 code ------ |
||||||
|
* |
||||||
|
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
||||||
|
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
||||||
|
* Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
|
||||||
|
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
|
||||||
|
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
|
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#include <config.h> |
||||||
|
#include <version.h> |
||||||
|
|
||||||
|
#if defined(CONFIG_OMAP1510) |
||||||
|
#include <./configs/omap1510.h> |
||||||
|
#endif |
||||||
|
|
||||||
|
/* |
||||||
|
************************************************************************* |
||||||
|
* |
||||||
|
* Jump vector table as in table 3.1 in [1] |
||||||
|
* |
||||||
|
************************************************************************* |
||||||
|
*/ |
||||||
|
|
||||||
|
|
||||||
|
.globl _start
|
||||||
|
_start: b reset |
||||||
|
ldr pc, _undefined_instruction |
||||||
|
ldr pc, _software_interrupt |
||||||
|
ldr pc, _prefetch_abort |
||||||
|
ldr pc, _data_abort |
||||||
|
ldr pc, _not_used |
||||||
|
ldr pc, _irq |
||||||
|
ldr pc, _fiq |
||||||
|
|
||||||
|
_undefined_instruction: .word undefined_instruction |
||||||
|
_software_interrupt: .word software_interrupt |
||||||
|
_prefetch_abort: .word prefetch_abort |
||||||
|
_data_abort: .word data_abort |
||||||
|
_not_used: .word not_used |
||||||
|
_irq: .word irq |
||||||
|
_fiq: .word fiq |
||||||
|
|
||||||
|
.balignl 16,0xdeadbeef |
||||||
|
|
||||||
|
|
||||||
|
/* |
||||||
|
************************************************************************* |
||||||
|
* |
||||||
|
* Startup Code (reset vector) |
||||||
|
* |
||||||
|
* do important init only if we don't start from memory! |
||||||
|
* setup Memory and board specific bits prior to relocation. |
||||||
|
* relocate armboot to ram |
||||||
|
* setup stack |
||||||
|
* |
||||||
|
************************************************************************* |
||||||
|
*/ |
||||||
|
|
||||||
|
/* |
||||||
|
* CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h) |
||||||
|
*/ |
||||||
|
_TEXT_BASE: |
||||||
|
.word TEXT_BASE
|
||||||
|
|
||||||
|
.globl _armboot_start
|
||||||
|
_armboot_start: |
||||||
|
.word _start
|
||||||
|
|
||||||
|
/* |
||||||
|
* Note: _armboot_end_data and _armboot_end are defined |
||||||
|
* by the (board-dependent) linker script. |
||||||
|
* _armboot_end_data is the first usable FLASH address after armboot |
||||||
|
*/ |
||||||
|
.globl _armboot_end_data
|
||||||
|
_armboot_end_data: |
||||||
|
.word armboot_end_data
|
||||||
|
.globl _armboot_end
|
||||||
|
_armboot_end: |
||||||
|
.word armboot_end
|
||||||
|
|
||||||
|
/* |
||||||
|
* _armboot_real_end is the first usable RAM address behind armboot |
||||||
|
* and the various stacks |
||||||
|
*/ |
||||||
|
.globl _armboot_real_end
|
||||||
|
_armboot_real_end: |
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
#ifdef CONFIG_USE_IRQ |
||||||
|
/* IRQ stack memory (calculated at run-time) */ |
||||||
|
.globl IRQ_STACK_START
|
||||||
|
IRQ_STACK_START: |
||||||
|
.word 0x0badc0de
|
||||||
|
|
||||||
|
/* IRQ stack memory (calculated at run-time) */ |
||||||
|
.globl FIQ_STACK_START
|
||||||
|
FIQ_STACK_START: |
||||||
|
.word 0x0badc0de
|
||||||
|
#endif |
||||||
|
|
||||||
|
|
||||||
|
/* |
||||||
|
* the actual reset code |
||||||
|
*/ |
||||||
|
|
||||||
|
reset: |
||||||
|
/* |
||||||
|
* set the cpu to SVC32 mode |
||||||
|
*/ |
||||||
|
mrs r0,cpsr |
||||||
|
bic r0,r0,#0x1f |
||||||
|
orr r0,r0,#0xd3 |
||||||
|
msr cpsr,r0 |
||||||
|
|
||||||
|
/* |
||||||
|
* Set up 925T mode |
||||||
|
*/ |
||||||
|
mov r1, #0x81 /* Set ARM925T configuration. */ |
||||||
|
mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* turn off the watchdog, unlock/diable sequence |
||||||
|
*/ |
||||||
|
mov r1, #0xF5 |
||||||
|
ldr r0, =WDTIM_MODE |
||||||
|
strh r1, [r0] |
||||||
|
mov r1, #0xA0 |
||||||
|
strh r1, [r0] |
||||||
|
|
||||||
|
/* |
||||||
|
* mask all IRQs by setting all bits in the INTMR - default |
||||||
|
*/ |
||||||
|
mov r1, #0xffffffff |
||||||
|
ldr r0, =REG_IHL1_MIR |
||||||
|
str r1, [r0] |
||||||
|
ldr r0, =REG_IHL2_MIR |
||||||
|
str r1, [r0] |
||||||
|
|
||||||
|
/*
|
||||||
|
* wait for dpll to lock |
||||||
|
*/
|
||||||
|
ldr r0, =CK_DPLL1 |
||||||
|
mov r1, #0x10 |
||||||
|
strh r1, [r0] |
||||||
|
poll1: |
||||||
|
ldrh r1, [r0] |
||||||
|
ands r1, r1, #0x01 |
||||||
|
beq poll1 |
||||||
|
bl cpu_init_crit |
||||||
|
|
||||||
|
relocate: |
||||||
|
/* |
||||||
|
* relocate armboot to RAM |
||||||
|
*/ |
||||||
|
adr r0, _start /* r0 <- current position of code */ |
||||||
|
ldr r2, _armboot_start |
||||||
|
ldr r3, _armboot_end |
||||||
|
sub r2, r3, r2 /* r2 <- size of armboot */ |
||||||
|
ldr r1, _TEXT_BASE /* r1 <- destination address */ |
||||||
|
add r2, r0, r2 /* r2 <- source end address */ |
||||||
|
|
||||||
|
/* |
||||||
|
* r0 = source address |
||||||
|
* r1 = target address |
||||||
|
* r2 = source end address |
||||||
|
*/ |
||||||
|
copy_loop: |
||||||
|
ldmia r0!, {r3-r10} |
||||||
|
stmia r1!, {r3-r10} |
||||||
|
cmp r0, r2 |
||||||
|
ble copy_loop |
||||||
|
|
||||||
|
/* set up the stack */ |
||||||
|
ldr r0, _armboot_end |
||||||
|
add r0, r0, #CONFIG_STACKSIZE |
||||||
|
sub sp, r0, #12 /* leave 3 words for abort-stack */ |
||||||
|
|
||||||
|
ldr pc, _start_armboot |
||||||
|
|
||||||
|
_start_armboot: .word start_armboot |
||||||
|
|
||||||
|
|
||||||
|
/* |
||||||
|
************************************************************************* |
||||||
|
* |
||||||
|
* CPU_init_critical registers |
||||||
|
* |
||||||
|
* setup important registers |
||||||
|
* setup memory timing |
||||||
|
* |
||||||
|
************************************************************************* |
||||||
|
*/ |
||||||
|
|
||||||
|
|
||||||
|
cpu_init_crit: |
||||||
|
/* |
||||||
|
* flush v4 I/D caches |
||||||
|
*/ |
||||||
|
mov r0, #0 |
||||||
|
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
||||||
|
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
||||||
|
|
||||||
|
/* |
||||||
|
* disable MMU stuff and caches |
||||||
|
*/ |
||||||
|
mrc p15, 0, r0, c1, c0, 0 |
||||||
|
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
||||||
|
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
||||||
|
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
|
||||||
|
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
||||||
|
mcr p15, 0, r0, c1, c0, 0 |
||||||
|
|
||||||
|
/* |
||||||
|
* Go setup Memory and board specific bits prior to relocation. |
||||||
|
*/ |
||||||
|
mov ip, lr /* perserve link reg across call */ |
||||||
|
bl platformsetup /* go setup pll,mux,memory */ |
||||||
|
mov lr, ip /* restore link */ |
||||||
|
mov pc, lr /* back to my caller */ |
||||||
|
/* |
||||||
|
************************************************************************* |
||||||
|
* |
||||||
|
* Interrupt handling |
||||||
|
* |
||||||
|
************************************************************************* |
||||||
|
*/ |
||||||
|
|
||||||
|
@
|
||||||
|
@ IRQ stack frame.
|
||||||
|
@
|
||||||
|
#define S_FRAME_SIZE 72 |
||||||
|
|
||||||
|
#define S_OLD_R0 68 |
||||||
|
#define S_PSR 64 |
||||||
|
#define S_PC 60 |
||||||
|
#define S_LR 56 |
||||||
|
#define S_SP 52 |
||||||
|
|
||||||
|
#define S_IP 48 |
||||||
|
#define S_FP 44 |
||||||
|
#define S_R10 40 |
||||||
|
#define S_R9 36 |
||||||
|
#define S_R8 32 |
||||||
|
#define S_R7 28 |
||||||
|
#define S_R6 24 |
||||||
|
#define S_R5 20 |
||||||
|
#define S_R4 16 |
||||||
|
#define S_R3 12 |
||||||
|
#define S_R2 8 |
||||||
|
#define S_R1 4 |
||||||
|
#define S_R0 0 |
||||||
|
|
||||||
|
#define MODE_SVC 0x13 |
||||||
|
#define I_BIT 0x80 |
||||||
|
|
||||||
|
/* |
||||||
|
* use bad_save_user_regs for abort/prefetch/undef/swi ... |
||||||
|
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling |
||||||
|
*/ |
||||||
|
|
||||||
|
.macro bad_save_user_regs
|
||||||
|
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack |
||||||
|
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
|
||||||
|
|
||||||
|
ldr r2, _armboot_end @ find top of stack
|
||||||
|
add r2, r2, #CONFIG_STACKSIZE @ find base of normal stack |
||||||
|
sub r2, r2, #8 @ set base 2 words into abort stack
|
||||||
|
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
|
||||||
|
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack |
||||||
|
|
||||||
|
add r5, sp, #S_SP |
||||||
|
mov r1, lr |
||||||
|
stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
|
||||||
|
mov r0, sp @ save current stack into r0 (param register)
|
||||||
|
.endm |
||||||
|
|
||||||
|
.macro irq_save_user_regs
|
||||||
|
sub sp, sp, #S_FRAME_SIZE |
||||||
|
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||||
|
add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. |
||||||
|
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
||||||
|
str lr, [r8, #0] @ Save calling PC
|
||||||
|
mrs r6, spsr |
||||||
|
str r6, [r8, #4] @ Save CPSR
|
||||||
|
str r0, [r8, #8] @ Save OLD_R0
|
||||||
|
mov r0, sp |
||||||
|
.endm |
||||||
|
|
||||||
|
.macro irq_restore_user_regs
|
||||||
|
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
||||||
|
mov r0, r0 |
||||||
|
ldr lr, [sp, #S_PC] @ Get PC |
||||||
|
add sp, sp, #S_FRAME_SIZE |
||||||
|
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
||||||
|
.endm |
||||||
|
|
||||||
|
.macro get_bad_stack
|
||||||
|
ldr r13, _armboot_end @ get bottom of stack (into sp by by user stack pointer).
|
||||||
|
add r13, r13, #CONFIG_STACKSIZE @ head to reserved words at the top of the stack |
||||||
|
sub r13, r13, #8 @ reserved a couple spots in abort stack
|
||||||
|
|
||||||
|
str lr, [r13] @ save caller lr in position 0 of saved stack
|
||||||
|
mrs lr, spsr @ get the spsr
|
||||||
|
str lr, [r13, #4] @ save spsr in position 1 of saved stack
|
||||||
|
|
||||||
|
mov r13, #MODE_SVC @ prepare SVC-Mode |
||||||
|
@ msr spsr_c, r13
|
||||||
|
msr spsr, r13 @ switch modes, make sure moves will execute
|
||||||
|
mov lr, pc @ capture return pc
|
||||||
|
movs pc, lr @ jump to next instruction & switch modes.
|
||||||
|
.endm |
||||||
|
|
||||||
|
.macro get_irq_stack @ setup IRQ stack
|
||||||
|
ldr sp, IRQ_STACK_START |
||||||
|
.endm |
||||||
|
|
||||||
|
.macro get_fiq_stack @ setup FIQ stack
|
||||||
|
ldr sp, FIQ_STACK_START |
||||||
|
.endm |
||||||
|
|
||||||
|
/* |
||||||
|
* exception handlers |
||||||
|
*/ |
||||||
|
.align 5
|
||||||
|
undefined_instruction: |
||||||
|
get_bad_stack |
||||||
|
bad_save_user_regs |
||||||
|
bl do_undefined_instruction |
||||||
|
|
||||||
|
.align 5
|
||||||
|
software_interrupt: |
||||||
|
get_bad_stack |
||||||
|
bad_save_user_regs |
||||||
|
bl do_software_interrupt |
||||||
|
|
||||||
|
.align 5
|
||||||
|
prefetch_abort: |
||||||
|
get_bad_stack |
||||||
|
bad_save_user_regs |
||||||
|
bl do_prefetch_abort |
||||||
|
|
||||||
|
.align 5
|
||||||
|
data_abort: |
||||||
|
get_bad_stack |
||||||
|
bad_save_user_regs |
||||||
|
bl do_data_abort |
||||||
|
|
||||||
|
.align 5
|
||||||
|
not_used: |
||||||
|
get_bad_stack |
||||||
|
bad_save_user_regs |
||||||
|
bl do_not_used |
||||||
|
|
||||||
|
#ifdef CONFIG_USE_IRQ |
||||||
|
|
||||||
|
.align 5
|
||||||
|
irq: |
||||||
|
get_irq_stack |
||||||
|
irq_save_user_regs |
||||||
|
bl do_irq |
||||||
|
irq_restore_user_regs |
||||||
|
|
||||||
|
.align 5
|
||||||
|
fiq: |
||||||
|
get_fiq_stack |
||||||
|
/* someone ought to write a more effiction fiq_save_user_regs */ |
||||||
|
irq_save_user_regs |
||||||
|
bl do_fiq |
||||||
|
irq_restore_user_regs |
||||||
|
|
||||||
|
#else |
||||||
|
|
||||||
|
.align 5
|
||||||
|
irq: |
||||||
|
get_bad_stack |
||||||
|
bad_save_user_regs |
||||||
|
bl do_irq |
||||||
|
|
||||||
|
.align 5
|
||||||
|
fiq: |
||||||
|
get_bad_stack |
||||||
|
bad_save_user_regs |
||||||
|
bl do_fiq |
||||||
|
|
||||||
|
#endif |
||||||
|
|
||||||
|
.align 5
|
||||||
|
.globl reset_cpu
|
||||||
|
reset_cpu: |
||||||
|
ldr r1, rstctl1 /* get clkm1 reset ctl */ |
||||||
|
mov r3, #0x0
|
||||||
|
strh r3, [r1] /* clear it */ |
||||||
|
mov r3, #0x8 |
||||||
|
strh r3, [r1] /* force dsp+arm reset */ |
||||||
|
_loop_forever: |
||||||
|
b _loop_forever |
||||||
|
rstctl1: |
||||||
|
.word 0xfffece10
|
||||||
@ -0,0 +1,15 @@ |
|||||||
|
/************************************************
|
||||||
|
* NAME : arm925t.h |
||||||
|
* Version : 23 June 2003 * |
||||||
|
************************************************/ |
||||||
|
|
||||||
|
#ifndef __ARM925T_H__ |
||||||
|
#define __ARM925T_H__ |
||||||
|
|
||||||
|
void gpioreserve(ushort mask); |
||||||
|
void gpiosetdir(ushort mask, ushort in); |
||||||
|
void gpiosetout(ushort mask, ushort out); |
||||||
|
void gpioinit(void); |
||||||
|
void archflashwp(void *archdata, int wp); |
||||||
|
|
||||||
|
#endif /*__ARM925T_H__*/ |
||||||
@ -0,0 +1,50 @@ |
|||||||
|
/*
|
||||||
|
* This program is free software; you can redistribute it and/or modify |
||||||
|
* it under the terms of the GNU General Public License as published by |
||||||
|
* the Free Software Foundation; either version 2 of the License, or |
||||||
|
* (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
/* DO NOT EDIT!! - this file automatically generated
|
||||||
|
* from .s file by awk -f s2h.awk |
||||||
|
*/ |
||||||
|
/* Size defintions
|
||||||
|
* Copyright (C) ARM Limited 1998. All rights reserved. |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __sizes_h |
||||||
|
#define __sizes_h 1 |
||||||
|
|
||||||
|
/* handy sizes */ |
||||||
|
#define SZ_1K 0x00000400 |
||||||
|
#define SZ_4K 0x00001000 |
||||||
|
#define SZ_8K 0x00002000 |
||||||
|
#define SZ_16K 0x00004000 |
||||||
|
#define SZ_64K 0x00010000 |
||||||
|
#define SZ_128K 0x00020000 |
||||||
|
#define SZ_256K 0x00040000 |
||||||
|
#define SZ_512K 0x00080000 |
||||||
|
|
||||||
|
#define SZ_1M 0x00100000 |
||||||
|
#define SZ_2M 0x00200000 |
||||||
|
#define SZ_4M 0x00400000 |
||||||
|
#define SZ_8M 0x00800000 |
||||||
|
#define SZ_16M 0x01000000 |
||||||
|
#define SZ_32M 0x02000000 |
||||||
|
#define SZ_64M 0x04000000 |
||||||
|
#define SZ_128M 0x08000000 |
||||||
|
#define SZ_256M 0x10000000 |
||||||
|
#define SZ_512M 0x20000000 |
||||||
|
|
||||||
|
#define SZ_1G 0x40000000 |
||||||
|
#define SZ_2G 0x80000000 |
||||||
|
|
||||||
|
#endif /* __sizes_h */ |
||||||
@ -0,0 +1,687 @@ |
|||||||
|
/*
|
||||||
|
* |
||||||
|
* BRIEF MODULE DESCRIPTION |
||||||
|
* OMAP hardware map |
||||||
|
* |
||||||
|
* Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
|
||||||
|
* Author: RidgeRun, Inc. |
||||||
|
* Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or modify it |
||||||
|
* under the terms of the GNU General Public License as published by the |
||||||
|
* Free Software Foundation; either version 2 of the License, or (at your |
||||||
|
* option) any later version. |
||||||
|
* |
||||||
|
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
||||||
|
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
||||||
|
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||||||
|
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
||||||
|
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
||||||
|
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
||||||
|
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License along |
||||||
|
* with this program; if not, write to the Free Software Foundation, Inc., |
||||||
|
* 675 Mass Ave, Cambridge, MA 02139, USA. |
||||||
|
*/ |
||||||
|
|
||||||
|
#include <asm/arch/sizes.h> |
||||||
|
|
||||||
|
/*
|
||||||
|
There are 2 sets of general I/O --> |
||||||
|
1. GPIO (shared between ARM & DSP, configured by ARM) |
||||||
|
2. MPUIO which can be used only by the ARM. |
||||||
|
|
||||||
|
Base address FFFB:5000 is where the ARM accesses the MPUIO control registers |
||||||
|
(see 7.2.2 of the TRM for MPUIO reg definitions). |
||||||
|
|
||||||
|
Base address E101:5000 is reserved for ARM access of the same MPUIO control |
||||||
|
regs, but via the DSP I/O map. This address is unavailable on 1510. |
||||||
|
|
||||||
|
Base address FFFC:E000 is where the ARM accesses the GPIO config registers |
||||||
|
directly via its own peripheral bus. |
||||||
|
|
||||||
|
Base address E101:E000 is where the ARM can access the same GPIO config |
||||||
|
registers, but the access takes place through the ARM port interface (called |
||||||
|
API or MPUI) via the DSP's peripheral bus (DSP I/O space). |
||||||
|
|
||||||
|
Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses |
||||||
|
instead of the E101:E000 addresses. The DSP has only read access of the pin |
||||||
|
control register, so this may explain the inability to write to E101:E018. |
||||||
|
Try accessing pin control reg at FFFC:E018. |
||||||
|
*/ |
||||||
|
#define OMAP1510_GPIO_BASE 0xfffce000 |
||||||
|
#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE |
||||||
|
#define OMAP1510_GPIO_SIZE SZ_4K |
||||||
|
|
||||||
|
#define OMAP1510_MCBSP1_BASE 0xE1011000 |
||||||
|
#define OMAP1510_MCBSP1_SIZE SZ_4K |
||||||
|
#define OMAP1510_MCBSP1_START 0xE1011000 |
||||||
|
|
||||||
|
#define OMAP1510_MCBSP2_BASE 0xFFFB1000 |
||||||
|
|
||||||
|
#define OMAP1510_MCBSP3_BASE 0xE1017000 |
||||||
|
#define OMAP1510_MCBSP3_SIZE SZ_4K |
||||||
|
#define OMAP1510_MCBSP3_START 0xE1017000 |
||||||
|
|
||||||
|
/*
|
||||||
|
* Where's the flush address (for flushing D and I cache?) |
||||||
|
*/ |
||||||
|
#define FLUSH_BASE 0xdf000000 |
||||||
|
#define FLUSH_BASE_PHYS 0x00000000 |
||||||
|
|
||||||
|
#ifndef __ASSEMBLER__ |
||||||
|
|
||||||
|
#define PCIO_BASE 0 |
||||||
|
|
||||||
|
/*
|
||||||
|
* RAM definitions |
||||||
|
*/ |
||||||
|
#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET) |
||||||
|
#define KERNTOPHYS(a) ((unsigned long)(&a)) |
||||||
|
#define KERNEL_BASE (0x10008000) |
||||||
|
#endif |
||||||
|
|
||||||
|
/* macro to get at IO space when running virtually */ |
||||||
|
#define IO_ADDRESS(x) ((x)) |
||||||
|
|
||||||
|
/* ----------------------------------------------------------------------------
|
||||||
|
* OMAP1510 system registers |
||||||
|
* ---------------------------------------------------------------------------- |
||||||
|
*/ |
||||||
|
|
||||||
|
#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */ |
||||||
|
#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */ |
||||||
|
#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */ |
||||||
|
#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */ |
||||||
|
#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */ |
||||||
|
#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */ |
||||||
|
#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* OMAP1510 UART3 Registers |
||||||
|
*/ |
||||||
|
|
||||||
|
#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */ |
||||||
|
|
||||||
|
/* UART3 Registers Maping through MPU bus */ |
||||||
|
|
||||||
|
#define UART3_RHR (OMAP_MPU_UART3_BASE + 0) |
||||||
|
#define UART3_THR (OMAP_MPU_UART3_BASE + 0) |
||||||
|
#define UART3_DLL (OMAP_MPU_UART3_BASE + 0) |
||||||
|
#define UART3_IER (OMAP_MPU_UART3_BASE + 4) |
||||||
|
#define UART3_DLH (OMAP_MPU_UART3_BASE + 4) |
||||||
|
#define UART3_IIR (OMAP_MPU_UART3_BASE + 8) |
||||||
|
#define UART3_FCR (OMAP_MPU_UART3_BASE + 8) |
||||||
|
#define UART3_EFR (OMAP_MPU_UART3_BASE + 8) |
||||||
|
#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C) |
||||||
|
#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10) |
||||||
|
#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10) |
||||||
|
#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14) |
||||||
|
#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14) |
||||||
|
#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18) |
||||||
|
#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18) |
||||||
|
#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18) |
||||||
|
#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C) |
||||||
|
#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C) |
||||||
|
#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C) |
||||||
|
#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20) |
||||||
|
#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24) |
||||||
|
#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28) |
||||||
|
#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28) |
||||||
|
#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C) |
||||||
|
#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C) |
||||||
|
#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30) |
||||||
|
#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30) |
||||||
|
#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34) |
||||||
|
#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34) |
||||||
|
#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38) |
||||||
|
#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C) |
||||||
|
#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C) |
||||||
|
#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40) |
||||||
|
#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44) |
||||||
|
#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48) |
||||||
|
#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C) |
||||||
|
#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration Registers |
||||||
|
*/ |
||||||
|
#define FUNC_MUX_CTRL_0 0xfffe1000 |
||||||
|
#define FUNC_MUX_CTRL_1 0xfffe1004 |
||||||
|
#define FUNC_MUX_CTRL_2 0xfffe1008 |
||||||
|
#define COMP_MODE_CTRL_0 0xfffe100c |
||||||
|
#define FUNC_MUX_CTRL_3 0xfffe1010 |
||||||
|
#define FUNC_MUX_CTRL_4 0xfffe1014 |
||||||
|
#define FUNC_MUX_CTRL_5 0xfffe1018 |
||||||
|
#define FUNC_MUX_CTRL_6 0xfffe101C |
||||||
|
#define FUNC_MUX_CTRL_7 0xfffe1020 |
||||||
|
#define FUNC_MUX_CTRL_8 0xfffe1024 |
||||||
|
#define FUNC_MUX_CTRL_9 0xfffe1028 |
||||||
|
#define FUNC_MUX_CTRL_A 0xfffe102C |
||||||
|
#define FUNC_MUX_CTRL_B 0xfffe1030 |
||||||
|
#define FUNC_MUX_CTRL_C 0xfffe1034 |
||||||
|
#define FUNC_MUX_CTRL_D 0xfffe1038 |
||||||
|
#define PULL_DWN_CTRL_0 0xfffe1040 |
||||||
|
#define PULL_DWN_CTRL_1 0xfffe1044 |
||||||
|
#define PULL_DWN_CTRL_2 0xfffe1048 |
||||||
|
#define PULL_DWN_CTRL_3 0xfffe104c |
||||||
|
#define GATE_INH_CTRL_0 0xfffe1050 |
||||||
|
#define VOLTAGE_CTRL_0 0xfffe1060 |
||||||
|
#define TEST_DBG_CTRL_0 0xfffe1070 |
||||||
|
|
||||||
|
#define MOD_CONF_CTRL_0 0xfffe1080 |
||||||
|
|
||||||
|
/*
|
||||||
|
* Traffic Controller Memory Interface Registers |
||||||
|
*/ |
||||||
|
#define TCMIF_BASE 0xfffecc00 |
||||||
|
#define IMIF_PRIO (TCMIF_BASE + 0x00) |
||||||
|
#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04) |
||||||
|
#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08) |
||||||
|
#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c) |
||||||
|
#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10) |
||||||
|
#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14) |
||||||
|
#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18) |
||||||
|
#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c) |
||||||
|
#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20) |
||||||
|
#define EMIFF_MRS (TCMIF_BASE + 0x24) |
||||||
|
#define TC_TIMEOUT1 (TCMIF_BASE + 0x28) |
||||||
|
#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c) |
||||||
|
#define TC_TIMEOUT3 (TCMIF_BASE + 0x30) |
||||||
|
#define TC_ENDIANISM (TCMIF_BASE + 0x34) |
||||||
|
#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c) |
||||||
|
#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40) |
||||||
|
|
||||||
|
/*
|
||||||
|
* LCD Panel |
||||||
|
*/ |
||||||
|
#define TI925_LCD_BASE 0xFFFEC000 |
||||||
|
#define TI925_LCD_CONTROL (TI925_LCD_BASE) |
||||||
|
#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4) |
||||||
|
#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8) |
||||||
|
#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc) |
||||||
|
#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10) |
||||||
|
#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14) |
||||||
|
|
||||||
|
#define OMAP_LCD_CONTROL TI925_LCD_CONTROL |
||||||
|
|
||||||
|
/*
|
||||||
|
* MMC/SD Host Controller Registers |
||||||
|
*/ |
||||||
|
|
||||||
|
#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */ |
||||||
|
#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */ |
||||||
|
#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */ |
||||||
|
#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */ |
||||||
|
#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */ |
||||||
|
#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */ |
||||||
|
#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */ |
||||||
|
#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */ |
||||||
|
#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */ |
||||||
|
#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */ |
||||||
|
#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */ |
||||||
|
#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */ |
||||||
|
#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */ |
||||||
|
#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */ |
||||||
|
#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */ |
||||||
|
#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */ |
||||||
|
#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */ |
||||||
|
#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */ |
||||||
|
#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */ |
||||||
|
#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */ |
||||||
|
#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */ |
||||||
|
#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */ |
||||||
|
#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */ |
||||||
|
#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */ |
||||||
|
|
||||||
|
/* MMC masks */ |
||||||
|
|
||||||
|
#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */ |
||||||
|
#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */ |
||||||
|
#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */ |
||||||
|
#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */ |
||||||
|
#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */ |
||||||
|
#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */ |
||||||
|
#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */ |
||||||
|
#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */ |
||||||
|
#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */ |
||||||
|
#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */ |
||||||
|
#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */ |
||||||
|
#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */ |
||||||
|
#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */ |
||||||
|
|
||||||
|
/* 2.9.2 MPUI Interface Registers FFFE:C900 */ |
||||||
|
|
||||||
|
#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900) |
||||||
|
#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904) |
||||||
|
#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908) |
||||||
|
#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c) |
||||||
|
#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910) |
||||||
|
#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914) |
||||||
|
#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918) |
||||||
|
#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c) |
||||||
|
|
||||||
|
/* 2.9.6 Traffic Controller Memory Interface Registers: */ |
||||||
|
#define OMAP_IMIF_PRIO_REG 0xfffecc00 |
||||||
|
#define OMAP_EMIFS_PRIO_REG 0xfffecc04 |
||||||
|
#define OMAP_EMIFF_PRIO_REG 0xfffecc08 |
||||||
|
#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c |
||||||
|
#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10 |
||||||
|
#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14 |
||||||
|
#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18 |
||||||
|
#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c |
||||||
|
#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20 |
||||||
|
#define OMAP_EMIFF_MRS 0xfffecc24 |
||||||
|
#define OMAP_TIMEOUT1 0xfffecc28 |
||||||
|
#define OMAP_TIMEOUT2 0xfffecc2c |
||||||
|
#define OMAP_TIMEOUT3 0xfffecc30 |
||||||
|
#define OMAP_ENDIANISM 0xfffecc34 |
||||||
|
|
||||||
|
/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */ |
||||||
|
#define OMAP_EMIFS_CONFIG_FR (1 << 4) |
||||||
|
#define OMAP_EMIFS_CONFIG_PDE (1 << 3) |
||||||
|
#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) |
||||||
|
#define OMAP_EMIFS_CONFIG_BM (1 << 1) |
||||||
|
#define OMAP_EMIFS_CONFIG_WP (1 << 0) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Memory chunk set aside for the Framebuffer in SRAM |
||||||
|
*/ |
||||||
|
#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE |
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* DMA |
||||||
|
*/ |
||||||
|
|
||||||
|
#define OMAP1510_DMA_BASE 0xFFFED800 |
||||||
|
#define OMAP_DMA_BASE OMAP1510_DMA_BASE |
||||||
|
|
||||||
|
/* Global Register selection */ |
||||||
|
#define NO_GLOBAL_DMA_ACCESS 0 |
||||||
|
|
||||||
|
/* Channel select field
|
||||||
|
* NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc... |
||||||
|
*/ |
||||||
|
#define LCD_CHANNEL 0xc |
||||||
|
|
||||||
|
/* Register Select Field (LCD) */ |
||||||
|
#define DMA_LCD_CTRL 0 |
||||||
|
#define DMA_LCD_TOP_F1_L 1 |
||||||
|
#define DMA_LCD_TOP_F1_U 2 |
||||||
|
#define DMA_LCD_BOT_F1_L 3 |
||||||
|
#define DMA_LCD_BOT_F1_U 4 |
||||||
|
|
||||||
|
#define LCD_FRAME_MODE (1<<0) |
||||||
|
#define LCD_FRAME_IT_IE (1<<1) |
||||||
|
#define LCD_BUS_ERROR_IT_IE (1<<2) |
||||||
|
#define LCD_FRAME_1_IT_COND (1<<3) |
||||||
|
#define LCD_FRAME_2_IT_COND (1<<4) |
||||||
|
#define LCD_BUS_ERROR_IT_COND (1<<5) |
||||||
|
#define LCD_SOURCE_IMIF (1<<6) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Real-Time Clock |
||||||
|
*/ |
||||||
|
|
||||||
|
#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00) |
||||||
|
#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04) |
||||||
|
#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08) |
||||||
|
#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C) |
||||||
|
#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10) |
||||||
|
#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14) |
||||||
|
#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40) |
||||||
|
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------------
|
||||||
|
* OMAP1510 Interrupt Handlers |
||||||
|
* --------------------------------------------------------------------------- |
||||||
|
* |
||||||
|
*/ |
||||||
|
#define OMAP_IH1_BASE 0xfffecb00 |
||||||
|
#define OMAP_IH2_BASE 0xfffe0000 |
||||||
|
#define OMAP1510_ITR 0x0 |
||||||
|
#define OMAP1510_MASK 0x4 |
||||||
|
|
||||||
|
#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE |
||||||
|
#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR |
||||||
|
#define INTERRUPT_MASK_REGISTER OMAP1510_MASK |
||||||
|
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------------
|
||||||
|
* OMAP1510 TIMERS |
||||||
|
* --------------------------------------------------------------------------- |
||||||
|
* |
||||||
|
*/ |
||||||
|
|
||||||
|
#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000 |
||||||
|
|
||||||
|
/* 32k Timer Registers */ |
||||||
|
#define TIMER32k_CR 0x08 |
||||||
|
#define TIMER32k_TVR 0x00 |
||||||
|
#define TIMER32k_TCR 0x04 |
||||||
|
|
||||||
|
/* 32k Timer Control Register definition */ |
||||||
|
#define TIMER32k_TSS (1<<0) |
||||||
|
#define TIMER32k_TRB (1<<1) |
||||||
|
#define TIMER32k_INT (1<<2) |
||||||
|
#define TIMER32k_ARL (1<<3) |
||||||
|
|
||||||
|
/* MPU Timer base addresses */ |
||||||
|
#define OMAP1510_MPUTIMER_BASE 0xfffec500 |
||||||
|
#define OMAP1510_MPUTIMER_OFF 0x00000100 |
||||||
|
|
||||||
|
#define OMAP1510_TIMER1_BASE 0xfffec500 |
||||||
|
#define OMAP1510_TIMER2_BASE 0xfffec600 |
||||||
|
#define OMAP1510_TIMER3_BASE 0xfffec700 |
||||||
|
|
||||||
|
/* MPU Timer Registers */ |
||||||
|
#define CNTL_TIMER 0 |
||||||
|
#define LOAD_TIM 4 |
||||||
|
#define READ_TIM 8 |
||||||
|
|
||||||
|
/* CNTL_TIMER register bits */ |
||||||
|
#define MPUTIM_FREE (1<<6) |
||||||
|
#define MPUTIM_CLOCK_ENABLE (1<<5) |
||||||
|
#define MPUTIM_PTV_MASK (0x7<<PTV_BIT) |
||||||
|
#define MPUTIM_PTV_BIT 2 |
||||||
|
#define MPUTIM_AR (1<<1) |
||||||
|
#define MPUTIM_ST (1<<0) |
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------------
|
||||||
|
* OMAP1510 GPIO (SHARED) |
||||||
|
* --------------------------------------------------------------------------- |
||||||
|
* |
||||||
|
*/ |
||||||
|
#define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0) |
||||||
|
#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4) |
||||||
|
#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8) |
||||||
|
#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc) |
||||||
|
#define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10) |
||||||
|
#define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14) |
||||||
|
#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18) |
||||||
|
|
||||||
|
|
||||||
|
/* ---------------------------
|
||||||
|
* OMAP1510 MPUIO (ARM only) |
||||||
|
*---------------------------- |
||||||
|
*/ |
||||||
|
#define OMAP1510_MPUIO_BASE 0xFFFB5000 |
||||||
|
#define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0) |
||||||
|
#define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4) |
||||||
|
#define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8) |
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------------
|
||||||
|
* OMAP1510 TIPB (only) |
||||||
|
* --------------------------------------------------------------------------- |
||||||
|
* |
||||||
|
*/ |
||||||
|
#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 |
||||||
|
#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8) |
||||||
|
#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 |
||||||
|
#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8) |
||||||
|
|
||||||
|
/*
|
||||||
|
* --------------------------------------------------------------------------- |
||||||
|
* OMAP1510 Camera Interface |
||||||
|
* --------------------------------------------------------------------------- |
||||||
|
*/ |
||||||
|
#define CAMERA_BASE (IO_BASE + 0x6800) |
||||||
|
#define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00) |
||||||
|
#define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04) |
||||||
|
#define CAM_MODE_REG (CAMERA_BASE + 0x08) |
||||||
|
#define CAM_STATUS_REG (CAMERA_BASE + 0x0C) |
||||||
|
#define CAM_CAMDATA_REG (CAMERA_BASE + 0x10) |
||||||
|
#define CAM_GPIO_REG (CAMERA_BASE + 0x14) |
||||||
|
#define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18) |
||||||
|
|
||||||
|
#if 0 |
||||||
|
#ifndef __ASSEMBLY__ |
||||||
|
typedef struct { |
||||||
|
__u32 ctrlclock; |
||||||
|
__u32 it_status; |
||||||
|
__u32 mode; |
||||||
|
__u32 status; |
||||||
|
__u32 camdata; |
||||||
|
__u32 gpio; |
||||||
|
__u32 peak_counter; |
||||||
|
} camera_regs_t; |
||||||
|
#endif |
||||||
|
#endif |
||||||
|
|
||||||
|
/* CTRLCLOCK bit shifts */ |
||||||
|
#define FOSCMOD_BIT 0 |
||||||
|
#define FOSCMOD_MASK (0x7 << FOSCMOD_BIT) |
||||||
|
#define FOSCMOD_12MHz 0x0 |
||||||
|
#define FOSCMOD_6MHz 0x2 |
||||||
|
#define FOSCMOD_9_6MHz 0x4 |
||||||
|
#define FOSCMOD_24MHz 0x5 |
||||||
|
#define FOSCMOD_8MHz 0x6 |
||||||
|
#define POLCLK (1<<3) |
||||||
|
#define CAMEXCLK_EN (1<<4) |
||||||
|
#define MCLK_EN (1<<5) |
||||||
|
#define DPLL_EN (1<<6) |
||||||
|
#define LCLK_EN (1<<7) |
||||||
|
|
||||||
|
/* IT_STATUS bit shifts */ |
||||||
|
#define V_UP (1<<0) |
||||||
|
#define V_DOWN (1<<1) |
||||||
|
#define H_UP (1<<2) |
||||||
|
#define H_DOWN (1<<3) |
||||||
|
#define FIFO_FULL (1<<4) |
||||||
|
#define DATA_XFER (1<<5) |
||||||
|
|
||||||
|
/* MODE bit shifts */ |
||||||
|
#define CAMOSC (1<<0) |
||||||
|
#define IMGSIZE_BIT 1 |
||||||
|
#define IMGSIZE_MASK (0x3 << IMGSIZE_BIT) |
||||||
|
#define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */ |
||||||
|
#define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */ |
||||||
|
#define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */ |
||||||
|
#define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */ |
||||||
|
#define ORDERCAMD (1<<3) |
||||||
|
#define EN_V_UP (1<<4) |
||||||
|
#define EN_V_DOWN (1<<5) |
||||||
|
#define EN_H_UP (1<<6) |
||||||
|
#define EN_H_DOWN (1<<7) |
||||||
|
#define EN_DMA (1<<8) |
||||||
|
#define THRESHOLD (1<<9) |
||||||
|
#define THRESHOLD_BIT 9 |
||||||
|
#define THRESHOLD_MASK (0x7f<<9) |
||||||
|
#define EN_NIRQ (1<<16) |
||||||
|
#define EN_FIFO_FULL (1<<17) |
||||||
|
#define RAZ_FIFO (1<<18) |
||||||
|
|
||||||
|
/* STATUS bit shifts */ |
||||||
|
#define VSTATUS (1<<0) |
||||||
|
#define HSTATUS (1<<1) |
||||||
|
|
||||||
|
/* GPIO bit shifts */ |
||||||
|
#define CAM_RST (1<<0) |
||||||
|
|
||||||
|
|
||||||
|
/*********************
|
||||||
|
* Watchdog timer. |
||||||
|
*********************/ |
||||||
|
#define WDTIM_BASE 0xfffec800 |
||||||
|
#define WDTIM_CONTROL (WDTIM_BASE+0x00) |
||||||
|
#define WDTIM_LOAD (WDTIM_BASE+0x04) |
||||||
|
#define WDTIM_READ (WDTIM_BASE+0x04) |
||||||
|
#define WDTIM_MODE (WDTIM_BASE+0x08) |
||||||
|
|
||||||
|
/* Values to write to mode register to disable the watchdog function. */ |
||||||
|
#define DISABLE_SEQ1 0xF5 |
||||||
|
#define DISABLE_SEQ2 0xA0 |
||||||
|
|
||||||
|
/* WDTIM_CONTROL bit definitions. */ |
||||||
|
#define WDTIM_CONTROL_ST BIT7 |
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ---------------------------------------------------------------------------
|
||||||
|
* Differentiating processor versions for those who care. |
||||||
|
* --------------------------------------------------------------------------- |
||||||
|
* |
||||||
|
*/ |
||||||
|
#define OMAP1509 0 |
||||||
|
#define OMAP1510 1 |
||||||
|
|
||||||
|
#define OMAP1510_ID_CODE_REG 0xfffed404 |
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__ |
||||||
|
int cpu_type(void); |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* EVM Implementation Specifics. |
||||||
|
* |
||||||
|
* *** NOTE *** |
||||||
|
* Any definitions in these files should be prefixed by an identifier - |
||||||
|
* eg. OMAP1510P1_FLASH0_BASE . |
||||||
|
* |
||||||
|
*/ |
||||||
|
#ifdef CONFIG_OMAP_INNOVATOR |
||||||
|
#include "innovator.h" |
||||||
|
#endif |
||||||
|
|
||||||
|
#ifdef CONFIG_OMAP_1510P1 |
||||||
|
#include "omap1510p1.h" |
||||||
|
#endif |
||||||
|
|
||||||
|
/*****************************************************************************/ |
||||||
|
|
||||||
|
#define CLKGEN_RESET_BASE (0xfffece00) |
||||||
|
#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0) |
||||||
|
#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4) |
||||||
|
#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8) |
||||||
|
#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC) |
||||||
|
#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10) |
||||||
|
#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14) |
||||||
|
#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18) |
||||||
|
|
||||||
|
|
||||||
|
#define CK_CLKIN 12 /* MHz */ |
||||||
|
#define CK_RATEF 1 |
||||||
|
#define CK_IDLEF 2 |
||||||
|
#define CK_ENABLEF 4 |
||||||
|
#define CK_SELECTF 8 |
||||||
|
#ifndef __ASSEMBLER__ |
||||||
|
#define CK_DPLL1 ((volatile __u16 *)0xfffecf00) |
||||||
|
#else |
||||||
|
#define CK_DPLL1 (0xfffecf00) |
||||||
|
#endif |
||||||
|
#define SETARM_IDLE_SHIFT |
||||||
|
|
||||||
|
/* ARM_CKCTL bit shifts */ |
||||||
|
#define PERDIV 0 |
||||||
|
#define LCDDIV 2 |
||||||
|
#define ARMDIV 4 |
||||||
|
#define DSPDIV 6 |
||||||
|
#define TCDIV 8 |
||||||
|
#define DSPMMUDIV 10 |
||||||
|
#define ARM_TIMXO 12 |
||||||
|
#define EN_DSPCK 13 |
||||||
|
#define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */ |
||||||
|
|
||||||
|
#define ARM_CKCTL_RSRVD_BIT15 (1 << 15) |
||||||
|
#define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14) |
||||||
|
#define ARM_CKCTL_EN_DSPCK (1 << 13) |
||||||
|
#define ARM_CKCTL_ARM_TIMXO (1 << 12) |
||||||
|
#define ARM_CKCTL_DSPMMU_DIV1 (1 << 11) |
||||||
|
#define ARM_CKCTL_DSPMMU_DIV2 (1 << 10) |
||||||
|
#define ARM_CKCTL_TCDIV1 (1 << 9) |
||||||
|
#define ARM_CKCTL_TCDIV2 (1 << 8) |
||||||
|
#define ARM_CKCTL_DSPDIV1 (1 << 7) |
||||||
|
#define ARM_CKCTL_DSPDIV0 (1 << 6) |
||||||
|
#define ARM_CKCTL_ARMDIV1 (1 << 5) |
||||||
|
#define ARM_CKCTL_ARMDIV0 (1 << 4) |
||||||
|
#define ARM_CKCTL_LCDDIV1 (1 << 3) |
||||||
|
#define ARM_CKCTL_LCDDIV0 (1 << 2) |
||||||
|
#define ARM_CKCTL_PERDIV1 (1 << 1) |
||||||
|
#define ARM_CKCTL_PERDIV0 (1 << 0) |
||||||
|
|
||||||
|
/* ARM_IDLECT1 bit shifts */ |
||||||
|
#define IDLWDT_ARM 0 |
||||||
|
#define IDLXORP_ARM 1 |
||||||
|
#define IDLPER_ARM 2 |
||||||
|
#define IDLLCD_ARM 3 |
||||||
|
#define IDLLB_ARM 4 |
||||||
|
#define IDLHSAB_ARM 5 |
||||||
|
#define IDLIF_ARM 6 |
||||||
|
#define IDLDPLL_ARM 7 |
||||||
|
#define IDLAPI_ARM 8 |
||||||
|
#define IDLTIM_ARM 9 |
||||||
|
#define SETARM_IDLE 11 |
||||||
|
|
||||||
|
/* ARM_IDLECT2 bit shifts */ |
||||||
|
#define EN_WDTCK 0 |
||||||
|
#define EN_XORPCK 1 |
||||||
|
#define EN_PERCK 2 |
||||||
|
#define EN_LCDCK 3 |
||||||
|
#define EN_LBCK 4 |
||||||
|
#define EN_HSABCK 5 |
||||||
|
#define EN_APICK 6 |
||||||
|
#define EN_TIMCK 7 |
||||||
|
#define DMACK_REQ 8 |
||||||
|
#define EN_GPIOCK 9 |
||||||
|
#define EN_LBFREECK 10 |
||||||
|
|
||||||
|
#define ARM_RSTCT1_SW_RST (1 << 3) |
||||||
|
#define ARM_RSTCT1_DSP_RST (1 << 2) |
||||||
|
#define ARM_RSTCT1_DSP_EN (1 << 1) |
||||||
|
#define ARM_RSTCT1_ARM_RST (1 << 0) |
||||||
|
|
||||||
|
/* ARM_RSTCT2 bit shifts */ |
||||||
|
#define EN_PER 0 |
||||||
|
|
||||||
|
#define ARM_SYSST_RSRVD_BIT15 (1 << 15) |
||||||
|
#define ARM_SYSST_RSRVD_BIT14 (1 << 14) |
||||||
|
#define ARM_SYSST_CLOCK_SELECT2 (1 << 13) |
||||||
|
#define ARM_SYSST_CLOCK_SELECT1 (1 << 12) |
||||||
|
#define ARM_SYSST_CLOCK_SELECT0 (1 << 11) |
||||||
|
#define ARM_SYSST_RSRVD_BIT10 (1 << 10) |
||||||
|
#define ARM_SYSST_RSRVD_BIT9 (1 << 9) |
||||||
|
#define ARM_SYSST_RSRVD_BIT8 (1 << 8) |
||||||
|
#define ARM_SYSST_RSRVD_BIT7 (1 << 7) |
||||||
|
#define ARM_SYSST_IDLE_DSP (1 << 6) |
||||||
|
#define ARM_SYSST_POR (1 << 5) |
||||||
|
#define ARM_SYSST_EXT_RST (1 << 4) |
||||||
|
#define ARM_SYSST_ARM_MCRST (1 << 3) |
||||||
|
#define ARM_SYSST_ARM_WDRST (1 << 2) |
||||||
|
#define ARM_SYSST_GLOB_SWRST (1 << 1) |
||||||
|
#define ARM_SYSST_DSP_WDRST (1 << 0) |
||||||
|
|
||||||
|
/* Table 15-23. DPLL Control Registers: */ |
||||||
|
#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00) |
||||||
|
|
||||||
|
/* Table 15-24. Control Register (CTL_REG): */ |
||||||
|
|
||||||
|
#define DPLL_CTL_REG_IOB (1 << 13) |
||||||
|
#define DPLL_CTL_REG_PLL_MULT Fld(5,0) |
||||||
|
|
||||||
|
/*****************************************************************************/ |
||||||
|
|
||||||
|
/* OMAP INTERRUPT REGISTERS */ |
||||||
|
#define IRQ_ITR 0x00 |
||||||
|
#define IRQ_MIR 0x04 |
||||||
|
#define IRQ_SIR_IRQ 0x10 |
||||||
|
#define IRQ_SIR_FIQ 0x14 |
||||||
|
#define IRQ_CONTROL_REG 0x18 |
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#define IRQ_ISR 0x9c |
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#define IRQ_ILR0 0x1c |
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|
||||||
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#define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR) |
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#define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR) |
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|
||||||
|
/* INTERRUPT LEVEL REGISTER BITS */ |
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#define ILR_PRIORITY_MASK (0x3c) |
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|
#define ILR_PRIORITY_SHIFT (2) |
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#define ILR_LEVEL_TRIGGER (1<<1) |
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#define ILR_FIQ (1<<0) |
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|
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#define IRQ_LEVEL_INT 1 |
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#define IRQ_EDGE_INT 0 |
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@ -0,0 +1,170 @@ |
|||||||
|
/*
|
||||||
|
* (C) Copyright 2003 |
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|
* Texas Instruments. |
||||||
|
* Kshitij Gupta <kshitij@ti.com> |
||||||
|
* Configuation settings for the TI OMAP Innovator board. |
||||||
|
* |
||||||
|
* See file CREDITS for list of people who contributed to this |
||||||
|
* project. |
||||||
|
* |
||||||
|
* This program is free software; you can redistribute it and/or |
||||||
|
* modify it under the terms of the GNU General Public License as |
||||||
|
* published by the Free Software Foundation; either version 2 of |
||||||
|
* the License, or (at your option) any later version. |
||||||
|
* |
||||||
|
* This program is distributed in the hope that it will be useful, |
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||||
|
* GNU General Public License for more details. |
||||||
|
* |
||||||
|
* You should have received a copy of the GNU General Public License |
||||||
|
* along with this program; if not, write to the Free Software |
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||||
|
* MA 02111-1307 USA |
||||||
|
*/ |
||||||
|
|
||||||
|
#ifndef __CONFIG_H |
||||||
|
#define __CONFIG_H |
||||||
|
|
||||||
|
/*
|
||||||
|
* High Level Configuration Options |
||||||
|
* (easy to change) |
||||||
|
*/ |
||||||
|
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
||||||
|
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||||
|
#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ |
||||||
|
#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ |
||||||
|
|
||||||
|
/* input clock of PLL */ |
||||||
|
#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ |
||||||
|
|
||||||
|
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||||
|
|
||||||
|
#define CONFIG_MISC_INIT_R |
||||||
|
|
||||||
|
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||||
|
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||||
|
|
||||||
|
/*
|
||||||
|
* Size of malloc() pool |
||||||
|
*/ |
||||||
|
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||||
|
|
||||||
|
/*
|
||||||
|
* Hardware drivers |
||||||
|
*/ |
||||||
|
/*
|
||||||
|
#define CONFIG_DRIVER_SMC9196 |
||||||
|
#define CONFIG_SMC9196_BASE 0x08000300 |
||||||
|
#define CONFIG_SMC9196_EXT_PHY |
||||||
|
*/ |
||||||
|
#define CONFIG_DRIVER_LAN91C96 |
||||||
|
#define CONFIG_LAN91C96_BASE 0x08000300 |
||||||
|
#define CONFIG_LAN91C96_EXT_PHY |
||||||
|
|
||||||
|
/*
|
||||||
|
* NS16550 Configuration |
||||||
|
*/ |
||||||
|
#define CFG_NS16550 |
||||||
|
#define CFG_NS16550_SERIAL |
||||||
|
#define CFG_NS16550_REG_SIZE (-4) |
||||||
|
#define CFG_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ |
||||||
|
#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ |
||||||
|
|
||||||
|
/*
|
||||||
|
* select serial console configuration |
||||||
|
*/ |
||||||
|
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ |
||||||
|
|
||||||
|
/* allow to overwrite serial and ethaddr */ |
||||||
|
#define CONFIG_ENV_OVERWRITE |
||||||
|
|
||||||
|
#define CONFIG_ENV_OVERWRITE |
||||||
|
#define CONFIG_CONS_INDEX 1 |
||||||
|
#define CONFIG_BAUDRATE 115200 |
||||||
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||||
|
|
||||||
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) |
||||||
|
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT |
||||||
|
|
||||||
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||||
|
#include <cmd_confdefs.h> |
||||||
|
#include <configs/omap1510.h> |
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 3 |
||||||
|
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=157.87.82.48:/home/a0875451/mwd/myfs/target ip=dhcp" |
||||||
|
/*#define CONFIG_ETHADDR 00:0B:36:00:05:25 */ |
||||||
|
#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ |
||||||
|
#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ |
||||||
|
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ |
||||||
|
#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ |
||||||
|
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||||
|
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||||
|
/* what's this ? it's not used anywhere */ |
||||||
|
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options |
||||||
|
*/ |
||||||
|
#define CFG_LONGHELP /* undef to save memory */ |
||||||
|
#define CFG_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ |
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */ |
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||||
|
|
||||||
|
#define CFG_MEMTEST_START 0x10000000 /* memtest works on */ |
||||||
|
#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
||||||
|
|
||||||
|
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR 0x10000000 /* default load address */ |
||||||
|
|
||||||
|
/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
|
||||||
|
* This time is further subdivided by a local divisor. |
||||||
|
*/ |
||||||
|
#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
||||||
|
#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */ |
||||||
|
#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Stack sizes |
||||||
|
* |
||||||
|
* The stack sizes are set up in start.S using the settings below |
||||||
|
*/ |
||||||
|
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||||
|
#ifdef CONFIG_USE_IRQ |
||||||
|
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||||
|
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||||
|
#endif |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Physical Memory Map |
||||||
|
*/ |
||||||
|
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||||
|
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
||||||
|
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||||
|
|
||||||
|
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||||
|
|
||||||
|
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* FLASH and environment organization |
||||||
|
*/ |
||||||
|
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||||
|
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ |
||||||
|
#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ |
||||||
|
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000) /* addr of environment */ |
||||||
|
|
||||||
|
/* timeout values are in ticks */ |
||||||
|
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */ |
||||||
|
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */ |
||||||
|
|
||||||
|
#define CFG_ENV_IS_IN_FLASH 1 |
||||||
|
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
||||||
|
#define CFG_ENV_OFFSET 0x20000 /* environment starts here */ |
||||||
|
|
||||||
|
#endif /* __CONFIG_H */ |
||||||
Loading…
Reference in new issue