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x86: quark: MRC codes clean up

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This patch cleans up the quark MRC codes coding style by:
- Remove BIT0/1../31 defines from mrc_util.h
- Create names for the documented BITs and use them
- For undocumented single BITs, use (1 << n) directly
- For undocumented ORed BITs, use the hex number directly
- Remove redundancy parenthesis all over the codes
- Replace to use lower case hex numbers

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
master
Bin Meng 10 years ago committed by Simon Glass
parent b81bdf62e0
commit 312cc39e27
7 changed files with 955 additions and 1049 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 74
      arch/x86/cpu/quark/hte.c
  2. 4
      arch/x86/cpu/quark/hte.h
  3. 12
      arch/x86/cpu/quark/mrc.c
  4. 326
      arch/x86/cpu/quark/mrc_util.c
  5. 34
      arch/x86/cpu/quark/mrc_util.h
  6. 1205
      arch/x86/cpu/quark/smc.c
  7. 349
      arch/x86/cpu/quark/smc.h

74
arch/x86/cpu/quark/hte.c
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@ -20,9 +20,9 @@
*/
static void hte_enable_all_errors(void)
{
msg_port_write(HTE, 0x000200A2, 0xFFFFFFFF);
msg_port_write(HTE, 0x000200A3, 0x000000FF);
msg_port_write(HTE, 0x000200A4, 0x00000000);
msg_port_write(HTE, 0x000200a2, 0xffffffff);
msg_port_write(HTE, 0x000200a3, 0x000000ff);
msg_port_write(HTE, 0x000200a4, 0x00000000);
}
/**
@ -32,7 +32,7 @@ static void hte_enable_all_errors(void)
*/
static u32 hte_check_errors(void)
{
return msg_port_read(HTE, 0x000200A7);
return msg_port_read(HTE, 0x000200a7);
}
/**
@ -44,11 +44,11 @@ static void hte_wait_for_complete(void)
ENTERFN();
do {} while ((msg_port_read(HTE, 0x00020012) & BIT30) != 0);
do {} while ((msg_port_read(HTE, 0x00020012) & (1 << 30)) != 0);
tmp = msg_port_read(HTE, 0x00020011);
tmp |= BIT9;
tmp &= ~(BIT12 | BIT13);
tmp |= (1 << 9);
tmp &= ~((1 << 12) | (1 << 13));
msg_port_write(HTE, 0x00020011, tmp);
LEAVEFN();
@ -65,9 +65,9 @@ static void hte_clear_error_regs(void)
* Clear all HTE errors and enable error checking
* for burst and chunk.
*/
tmp = msg_port_read(HTE, 0x000200A1);
tmp |= BIT8;
msg_port_write(HTE, 0x000200A1, tmp);
tmp = msg_port_read(HTE, 0x000200a1);
tmp |= (1 << 8);
msg_port_write(HTE, 0x000200a1, tmp);
}
/**
@ -91,25 +91,25 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
u32 offset;
if (first_run) {
msg_port_write(HTE, 0x00020020, 0x01B10021);
msg_port_write(HTE, 0x00020020, 0x01b10021);
msg_port_write(HTE, 0x00020021, 0x06000000);
msg_port_write(HTE, 0x00020022, addr >> 6);
msg_port_write(HTE, 0x00020062, 0x00800015);
msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
msg_port_write(HTE, 0x00020064, 0xcccccccc);
msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
msg_port_write(HTE, 0x00020061, 0x00030008);
if (mode == WRITE_TRAIN)
pattern = 0xC33C0000;
pattern = 0xc33c0000;
else /* READ_TRAIN */
pattern = 0xAA5555AA;
pattern = 0xaa5555aa;
for (offset = 0x80; offset <= 0x8F; offset++)
for (offset = 0x80; offset <= 0x8f; offset++)
msg_port_write(HTE, offset, pattern);
}
msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
msg_port_write(HTE, 0x000200a1, 0xffff1000);
msg_port_write(HTE, 0x00020011, 0x00011000);
msg_port_write(HTE, 0x00020011, 0x00011100);
@ -119,7 +119,7 @@ static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr,
* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
* any bytelane errors.
*/
return (hte_check_errors() >> 8) & 0xFF;
return (hte_check_errors() >> 8) & 0xff;
}
/**
@ -153,7 +153,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
msg_port_write(HTE, 0x00020024, 0x06070000);
msg_port_write(HTE, 0x00020022, addr >> 6);
msg_port_write(HTE, 0x00020025, addr >> 6);
msg_port_write(HTE, 0x00020062, 0x0000002A);
msg_port_write(HTE, 0x00020062, 0x0000002a);
msg_port_write(HTE, 0x00020063, seed_victim);
msg_port_write(HTE, 0x00020064, seed_aggressor);
msg_port_write(HTE, 0x00020065, seed_victim);
@ -163,21 +163,21 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
*
* Start with bit0
*/
for (offset = 0x80; offset <= 0x8F; offset++) {
for (offset = 0x80; offset <= 0x8f; offset++) {
if ((offset % 8) == victim_bit)
msg_port_write(HTE, offset, 0x55555555);
else
msg_port_write(HTE, offset, 0xCCCCCCCC);
msg_port_write(HTE, offset, 0xcccccccc);
}
msg_port_write(HTE, 0x00020061, 0x00000000);
msg_port_write(HTE, 0x00020066, 0x03440000);
msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
msg_port_write(HTE, 0x000200a1, 0xffff1000);
}
tmp = 0x10001000 | (loop_cnt << 16);
msg_port_write(HTE, 0x00020011, tmp);
msg_port_write(HTE, 0x00020011, tmp | BIT8);
msg_port_write(HTE, 0x00020011, tmp | (1 << 8));
hte_wait_for_complete();
@ -185,7 +185,7 @@ static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr,
* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for
* any bytelane errors.
*/
return (hte_check_errors() >> 8) & 0xFF;
return (hte_check_errors() >> 8) & 0xff;
}
/**
@ -219,14 +219,14 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
msg_port_write(HTE, 0x00020062, 0x00000015);
for (offset = 0x80; offset <= 0x8F; offset++)
msg_port_write(HTE, offset, ((offset & 1) ? 0xA55A : 0x5AA5));
for (offset = 0x80; offset <= 0x8f; offset++)
msg_port_write(HTE, offset, ((offset & 1) ? 0xa55a : 0x5aa5));
msg_port_write(HTE, 0x00020021, 0x00000000);
msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1);
msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
msg_port_write(HTE, 0x00020064, 0xcccccccc);
msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
msg_port_write(HTE, 0x00020066, 0x03000000);
switch (flag) {
@ -243,7 +243,7 @@ u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag)
break;
default:
DPF(D_INFO, "Unknown parameter for flag: %d\n", flag);
return 0xFFFFFFFF;
return 0xffffffff;
}
DPF(D_INFO, "hte_mem_init");
@ -379,16 +379,16 @@ void hte_mem_op(u32 addr, u8 first_run, u8 is_write)
msg_port_write(HTE, 0x00020021, 0x06000000);
msg_port_write(HTE, 0x00020022, addr >> 6);
msg_port_write(HTE, 0x00020062, 0x00800015);
msg_port_write(HTE, 0x00020063, 0xAAAAAAAA);
msg_port_write(HTE, 0x00020064, 0xCCCCCCCC);
msg_port_write(HTE, 0x00020065, 0xF0F0F0F0);
msg_port_write(HTE, 0x00020063, 0xaaaaaaaa);
msg_port_write(HTE, 0x00020064, 0xcccccccc);
msg_port_write(HTE, 0x00020065, 0xf0f0f0f0);
msg_port_write(HTE, 0x00020061, 0x00030008);
for (offset = 0x80; offset <= 0x8F; offset++)
msg_port_write(HTE, offset, 0xC33C0000);
for (offset = 0x80; offset <= 0x8f; offset++)
msg_port_write(HTE, offset, 0xc33c0000);
}
msg_port_write(HTE, 0x000200A1, 0xFFFF1000);
msg_port_write(HTE, 0x000200a1, 0xffff1000);
msg_port_write(HTE, 0x00020011, 0x00011000);
msg_port_write(HTE, 0x00020011, 0x00011100);

4
arch/x86/cpu/quark/hte.h
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@ -29,10 +29,10 @@ enum {
#define HTE_LOOP_CNT 5
/* random seed for victim */
#define HTE_LFSR_VICTIM_SEED 0xF294BA21
#define HTE_LFSR_VICTIM_SEED 0xf294ba21
/* random seed for aggressor */
#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D
#define HTE_LFSR_AGRESSOR_SEED 0xeba7492d
u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag);
u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr,

12
arch/x86/cpu/quark/mrc.c
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@ -105,8 +105,8 @@ static void mrc_adjust_params(struct mrc_params *mrc_params)
* Column: 11 for 8Gbx8, else 10
*/
mrc_params->column_bits[0] =
((dram_params[0].density == 4) &&
(dram_width == X8)) ? (11) : (10);
(dram_params[0].density == 4) &&
(dram_width == X8) ? 11 : 10;
/*
* Determine row bits:
@ -117,9 +117,9 @@ static void mrc_adjust_params(struct mrc_params *mrc_params)
* 4Gbx16=15 4Gbx8=16
* 8Gbx16=16 8Gbx8=16
*/
mrc_params->row_bits[0] = 12 + (dram_params[0].density) +
(((dram_params[0].density < 4) &&
(dram_width == X8)) ? (1) : (0));
mrc_params->row_bits[0] = 12 + dram_params[0].density +
(dram_params[0].density < 4) &&
(dram_width == X8) ? 1 : 0;
/*
* Determine per-channel memory size:
@ -137,7 +137,7 @@ static void mrc_adjust_params(struct mrc_params *mrc_params)
* 4Gb x16 0x040000000 (1024MB)
* 4Gb x8 0x080000000 (2048MB)
*/
mrc_params->channel_size[0] = (1 << dram_params[0].density);
mrc_params->channel_size[0] = 1 << dram_params[0].density;
mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1;
mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1;
mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2;

326
arch/x86/cpu/quark/mrc_util.c
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@ -18,14 +18,14 @@
static const uint8_t vref_codes[64] = {
/* lowest to highest */
0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38,
0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38,
0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30,
0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28,
0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28,
0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20,
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
};
void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask)
@ -80,7 +80,7 @@ void select_mem_mgr(void)
ENTERFN();
dco = msg_port_read(MEM_CTLR, DCO);
dco &= ~BIT28;
dco &= ~DCO_PMICTL;
msg_port_write(MEM_CTLR, DCO, dco);
LEAVEFN();
@ -94,7 +94,7 @@ void select_hte(void)
ENTERFN();
dco = msg_port_read(MEM_CTLR, DCO);
dco |= BIT28;
dco |= DCO_PMICTL;
msg_port_write(MEM_CTLR, DCO, dco);
LEAVEFN();
@ -151,26 +151,25 @@ void set_rcvn(uint8_t channel, uint8_t rank,
* BL0 -> B01PTRCTL0[11:08] (0x0-0xF)
* BL1 -> B01PTRCTL0[23:20] (0x0-0xF)
*/
reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) :
(BIT11 | BIT10 | BIT9 | BIT8);
temp = (byte_lane & BIT0) ? ((pi_count / HALF_CLK) << 20) :
((pi_count / HALF_CLK) << 8);
reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
msk = (byte_lane & 1) ? 0xf00000 : 0xf00;
temp = (byte_lane & 1) ? (pi_count / HALF_CLK) << 20 :
(pi_count / HALF_CLK) << 8;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* Adjust PI_COUNT */
pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
/*
* PI (1/64 MCLK, 1 PIs)
* BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F)
* BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F)
*/
reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET));
msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
msk = 0x3f000000;
temp = pi_count << 24;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
@ -179,25 +178,25 @@ void set_rcvn(uint8_t channel, uint8_t rank,
* BL0/1 -> B01DBCTL1[08/11] (+1 select)
* BL0/1 -> B01DBCTL1[02/05] (enable)
*/
reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
msk = 0x00;
temp = 0x00;
/* enable */
msk |= (byte_lane & BIT0) ? BIT5 : BIT2;
msk |= (byte_lane & 1) ? (1 << 5) : (1 << 2);
if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
temp |= msk;
/* select */
msk |= (byte_lane & BIT0) ? BIT11 : BIT8;
msk |= (byte_lane & 1) ? (1 << 11) : (1 << 8);
if (pi_count < EARLY_DB)
temp |= msk;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* error check */
if (pi_count > 0x3F) {
if (pi_count > 0x3f) {
training_message(channel, rank, byte_lane);
mrc_post_code(0xee, 0xe0);
}
@ -224,11 +223,11 @@ uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane)
* BL0 -> B01PTRCTL0[11:08] (0x0-0xF)
* BL1 -> B01PTRCTL0[23:20] (0x0-0xF)
*/
reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= (byte_lane & BIT0) ? 20 : 8;
temp &= 0xF;
temp >>= (byte_lane & 1) ? 20 : 8;
temp &= 0xf;
/* Adjust PI_COUNT */
pi_count = temp * HALF_CLK;
@ -238,12 +237,12 @@ uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane)
* BL0 -> B0DLLPICODER0[29:24] (0x00-0x3F)
* BL1 -> B1DLLPICODER0[29:24] (0x00-0x3F)
*/
reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET));
reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= 24;
temp &= 0x3F;
temp &= 0x3f;
/* Adjust PI_COUNT */
pi_count += temp;
@ -275,10 +274,10 @@ void set_rdqs(uint8_t channel, uint8_t rank,
* BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47)
* BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47)
*/
reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE;
reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET));
msk = (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE;
reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
msk = 0x7f;
temp = pi_count << 0;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
@ -310,13 +309,13 @@ uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane)
* BL0 -> B0RXDQSPICODE[06:00] (0x00-0x47)
* BL1 -> B1RXDQSPICODE[06:00] (0x00-0x47)
*/
reg = (byte_lane & BIT0) ? B1RXDQSPICODE : B0RXDQSPICODE;
reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET));
reg = (byte_lane & 1) ? B1RXDQSPICODE : B0RXDQSPICODE;
reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
temp = msg_port_alt_read(DDRPHY, reg);
/* Adjust PI_COUNT */
pi_count = temp & 0x7F;
pi_count = temp & 0x7f;
LEAVEFN();
@ -346,26 +345,25 @@ void set_wdqs(uint8_t channel, uint8_t rank,
* BL0 -> B01PTRCTL0[07:04] (0x0-0xF)
* BL1 -> B01PTRCTL0[19:16] (0x0-0xF)
*/
reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
msk = (byte_lane & BIT0) ? (BIT19 | BIT18 | BIT17 | BIT16) :
(BIT7 | BIT6 | BIT5 | BIT4);
reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
msk = (byte_lane & 1) ? 0xf0000 : 0xf0;
temp = pi_count / HALF_CLK;
temp <<= (byte_lane & BIT0) ? 16 : 4;
temp <<= (byte_lane & 1) ? 16 : 4;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* Adjust PI_COUNT */
pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
/*
* PI (1/64 MCLK, 1 PIs)
* BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F)
* BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F)
*/
reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET));
msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16);
reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
msk = 0x3f0000;
temp = pi_count << 16;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
@ -374,25 +372,25 @@ void set_wdqs(uint8_t channel, uint8_t rank,
* BL0/1 -> B01DBCTL1[07/10] (+1 select)
* BL0/1 -> B01DBCTL1[01/04] (enable)
*/
reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
msk = 0x00;
temp = 0x00;
/* enable */
msk |= (byte_lane & BIT0) ? BIT4 : BIT1;
msk |= (byte_lane & 1) ? (1 << 4) : (1 << 1);
if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
temp |= msk;
/* select */
msk |= (byte_lane & BIT0) ? BIT10 : BIT7;
msk |= (byte_lane & 1) ? (1 << 10) : (1 << 7);
if (pi_count < EARLY_DB)
temp |= msk;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* error check */
if (pi_count > 0x3F) {
if (pi_count > 0x3f) {
training_message(channel, rank, byte_lane);
mrc_post_code(0xee, 0xe2);
}
@ -419,11 +417,11 @@ uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane)
* BL0 -> B01PTRCTL0[07:04] (0x0-0xF)
* BL1 -> B01PTRCTL0[19:16] (0x0-0xF)
*/
reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= (byte_lane & BIT0) ? 16 : 4;
temp &= 0xF;
temp >>= (byte_lane & 1) ? 16 : 4;
temp &= 0xf;
/* Adjust PI_COUNT */
pi_count = (temp * HALF_CLK);
@ -433,12 +431,12 @@ uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane)
* BL0 -> B0DLLPICODER0[21:16] (0x00-0x3F)
* BL1 -> B1DLLPICODER0[21:16] (0x00-0x3F)
*/
reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET));
reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= 16;
temp &= 0x3F;
temp &= 0x3f;
/* Adjust PI_COUNT */
pi_count += temp;
@ -471,26 +469,25 @@ void set_wdq(uint8_t channel, uint8_t rank,
* BL0 -> B01PTRCTL0[03:00] (0x0-0xF)
* BL1 -> B01PTRCTL0[15:12] (0x0-0xF)
*/
reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
msk = (byte_lane & BIT0) ? (BIT15 | BIT14 | BIT13 | BIT12) :
(BIT3 | BIT2 | BIT1 | BIT0);
reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
msk = (byte_lane & 1) ? 0xf000 : 0xf;
temp = pi_count / HALF_CLK;
temp <<= (byte_lane & BIT0) ? 12 : 0;
temp <<= (byte_lane & 1) ? 12 : 0;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* Adjust PI_COUNT */
pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
/*
* PI (1/64 MCLK, 1 PIs)
* BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F)
* BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F)
*/
reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET));
msk = (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
msk = 0x3f00;
temp = pi_count << 8;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
@ -499,25 +496,25 @@ void set_wdq(uint8_t channel, uint8_t rank,
* BL0/1 -> B01DBCTL1[06/09] (+1 select)
* BL0/1 -> B01DBCTL1[00/03] (enable)
*/
reg = B01DBCTL1 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
reg = B01DBCTL1 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
msk = 0x00;
temp = 0x00;
/* enable */
msk |= (byte_lane & BIT0) ? BIT3 : BIT0;
msk |= (byte_lane & 1) ? (1 << 3) : (1 << 0);
if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
temp |= msk;
/* select */
msk |= (byte_lane & BIT0) ? BIT9 : BIT6;
msk |= (byte_lane & 1) ? (1 << 9) : (1 << 6);
if (pi_count < EARLY_DB)
temp |= msk;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* error check */
if (pi_count > 0x3F) {
if (pi_count > 0x3f) {
training_message(channel, rank, byte_lane);
mrc_post_code(0xee, 0xe3);
}
@ -544,11 +541,11 @@ uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane)
* BL0 -> B01PTRCTL0[03:00] (0x0-0xF)
* BL1 -> B01PTRCTL0[15:12] (0x0-0xF)
*/
reg = B01PTRCTL0 + ((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET);
reg = B01PTRCTL0 + (byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET;
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= (byte_lane & BIT0) ? (12) : (0);
temp &= 0xF;
temp >>= (byte_lane & 1) ? 12 : 0;
temp &= 0xf;
/* Adjust PI_COUNT */
pi_count = temp * HALF_CLK;
@ -558,12 +555,12 @@ uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane)
* BL0 -> B0DLLPICODER0[13:08] (0x00-0x3F)
* BL1 -> B1DLLPICODER0[13:08] (0x00-0x3F)
*/
reg = (byte_lane & BIT0) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += (((byte_lane >> 1) * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET));
reg = (byte_lane & 1) ? B1DLLPICODER0 : B0DLLPICODER0;
reg += ((byte_lane >> 1) * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= 8;
temp &= 0x3F;
temp &= 0x3f;
/* Adjust PI_COUNT */
pi_count += temp;
@ -589,14 +586,14 @@ void set_wcmd(uint8_t channel, uint32_t pi_count)
* RDPTR (1/2 MCLK, 64 PIs)
* CMDPTRREG[11:08] (0x0-0xF)
*/
reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET);
msk = (BIT11 | BIT10 | BIT9 | BIT8);
reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET;
msk = 0xf00;
temp = pi_count / HALF_CLK;
temp <<= 8;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* Adjust PI_COUNT */
pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
/*
* PI (1/64 MCLK, 1 PIs)
@ -609,18 +606,13 @@ void set_wcmd(uint8_t channel, uint32_t pi_count)
* CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused)
* CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused)
*/
reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 |
BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 |
BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET;
msk = 0x3f3f3f3f;
temp = (pi_count << 24) | (pi_count << 16) |
(pi_count << 8) | (pi_count << 0);
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
reg = CMDDLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); /* PO */
reg = CMDDLLPICODER0 + channel * DDRIOCCC_CH_OFFSET; /* PO */
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/*
@ -628,24 +620,24 @@ void set_wcmd(uint8_t channel, uint32_t pi_count)
* CMDCFGREG0[17] (+1 select)
* CMDCFGREG0[16] (enable)
*/
reg = CMDCFGREG0 + (channel * DDRIOCCC_CH_OFFSET);
reg = CMDCFGREG0 + channel * DDRIOCCC_CH_OFFSET;
msk = 0x00;
temp = 0x00;
/* enable */
msk |= BIT16;
msk |= (1 << 16);
if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
temp |= msk;
/* select */
msk |= BIT17;
msk |= (1 << 17);
if (pi_count < EARLY_DB)
temp |= msk;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* error check */
if (pi_count > 0x3F)
if (pi_count > 0x3f)
mrc_post_code(0xee, 0xe4);
LEAVEFN();
@ -667,10 +659,10 @@ uint32_t get_wcmd(uint8_t channel)
* RDPTR (1/2 MCLK, 64 PIs)
* CMDPTRREG[11:08] (0x0-0xF)
*/
reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET);
reg = CMDPTRREG + channel * DDRIOCCC_CH_OFFSET;
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= 8;
temp &= 0xF;
temp &= 0xf;
/* Adjust PI_COUNT */
pi_count = temp * HALF_CLK;
@ -686,10 +678,10 @@ uint32_t get_wcmd(uint8_t channel)
* CMDDLLPICODER1[13:08] -> CMDSLICE R0 (unused)
* CMDDLLPICODER1[05:00] -> CMDSLICE L0 (unused)
*/
reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
reg = CMDDLLPICODER1 + channel * DDRIOCCC_CH_OFFSET;
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= 16;
temp &= 0x3F;
temp &= 0x3f;
/* Adjust PI_COUNT */
pi_count += temp;
@ -716,13 +708,13 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count)
* CCPTRREG[15:12] -> CLK1 (0x0-0xF)
* CCPTRREG[11:08] -> CLK0 (0x0-0xF)
*/
reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
msk = (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
msk = 0xff00;
temp = ((pi_count / HALF_CLK) << 12) | ((pi_count / HALF_CLK) << 8);
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* Adjust PI_COUNT */
pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
/*
* PI (1/64 MCLK, 1 PIs)
@ -731,16 +723,18 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count)
*/
reg = rank ? ECCB1DLLPICODER0 : ECCB1DLLPICODER0;
reg += (channel * DDRIOCCC_CH_OFFSET);
msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 |
BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8);
msk = 0x3f3f00;
temp = (pi_count << 16) | (pi_count << 8);
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
reg = rank ? ECCB1DLLPICODER1 : ECCB1DLLPICODER1;
reg += (channel * DDRIOCCC_CH_OFFSET);
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
reg = rank ? ECCB1DLLPICODER2 : ECCB1DLLPICODER2;
reg += (channel * DDRIOCCC_CH_OFFSET);
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
reg = rank ? ECCB1DLLPICODER3 : ECCB1DLLPICODER3;
reg += (channel * DDRIOCCC_CH_OFFSET);
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
@ -750,24 +744,24 @@ void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count)
* CCCFGREG1[11:08] (+1 select)
* CCCFGREG1[03:00] (enable)
*/
reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET);
reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET;
msk = 0x00;
temp = 0x00;
/* enable */
msk |= (BIT3 | BIT2 | BIT1 | BIT0);
msk |= 0xf;
if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
temp |= msk;
/* select */
msk |= (BIT11 | BIT10 | BIT9 | BIT8);
msk |= 0xf00;
if (pi_count < EARLY_DB)
temp |= msk;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* error check */
if (pi_count > 0x3F)
if (pi_count > 0x3f)
mrc_post_code(0xee, 0xe5);
LEAVEFN();
@ -790,10 +784,10 @@ uint32_t get_wclk(uint8_t channel, uint8_t rank)
* CCPTRREG[15:12] -> CLK1 (0x0-0xF)
* CCPTRREG[11:08] -> CLK0 (0x0-0xF)
*/
reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= rank ? 12 : 8;
temp &= 0xF;
temp &= 0xf;
/* Adjust PI_COUNT */
pi_count = temp * HALF_CLK;
@ -807,7 +801,7 @@ uint32_t get_wclk(uint8_t channel, uint8_t rank)
reg += (channel * DDRIOCCC_CH_OFFSET);
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= rank ? 16 : 8;
temp &= 0x3F;
temp &= 0x3f;
pi_count += temp;
@ -835,28 +829,31 @@ void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count)
* CCPTRREG[31:28] (0x0-0xF)
* CCPTRREG[27:24] (0x0-0xF)
*/
reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
msk = (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
msk = 0xff000000;
temp = ((pi_count / HALF_CLK) << 28) | ((pi_count / HALF_CLK) << 24);
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* Adjust PI_COUNT */
pi_count -= ((pi_count / HALF_CLK) & 0xF) * HALF_CLK;
pi_count -= ((pi_count / HALF_CLK) & 0xf) * HALF_CLK;
/*
* PI (1/64 MCLK, 1 PIs)
* ECCB1DLLPICODER?[29:24] (0x00-0x3F)
* ECCB1DLLPICODER?[29:24] (0x00-0x3F)
*/
reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET);
msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24);
reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET;
msk = 0x3f000000;
temp = (pi_count << 24);
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
reg = ECCB1DLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET);
reg = ECCB1DLLPICODER1 + channel * DDRIOCCC_CH_OFFSET;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
reg = ECCB1DLLPICODER2 + (channel * DDRIOCCC_CH_OFFSET);
reg = ECCB1DLLPICODER2 + channel * DDRIOCCC_CH_OFFSET;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
reg = ECCB1DLLPICODER3 + (channel * DDRIOCCC_CH_OFFSET);
reg = ECCB1DLLPICODER3 + channel * DDRIOCCC_CH_OFFSET;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/*
@ -864,24 +861,24 @@ void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count)
* CCCFGREG1[13:12] (+1 select)
* CCCFGREG1[05:04] (enable)
*/
reg = CCCFGREG1 + (channel * DDRIOCCC_CH_OFFSET);
reg = CCCFGREG1 + channel * DDRIOCCC_CH_OFFSET;
msk = 0x00;
temp = 0x00;
/* enable */
msk |= (BIT5 | BIT4);
msk |= 0x30;
if ((pi_count < EARLY_DB) || (pi_count > LATE_DB))
temp |= msk;
/* select */
msk |= (BIT13 | BIT12);
msk |= 0x3000;
if (pi_count < EARLY_DB)
temp |= msk;
mrc_alt_write_mask(DDRPHY, reg, temp, msk);
/* error check */
if (pi_count > 0x3F)
if (pi_count > 0x3f)
mrc_post_code(0xee, 0xe6);
LEAVEFN();
@ -906,10 +903,10 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank)
* CCPTRREG[31:28] (0x0-0xF)
* CCPTRREG[27:24] (0x0-0xF)
*/
reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET);
reg = CCPTRREG + channel * DDRIOCCC_CH_OFFSET;
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= 24;
temp &= 0xF;
temp &= 0xf;
/* Adjust PI_COUNT */
pi_count = temp * HALF_CLK;
@ -919,10 +916,10 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank)
* ECCB1DLLPICODER?[29:24] (0x00-0x3F)
* ECCB1DLLPICODER?[29:24] (0x00-0x3F)
*/
reg = ECCB1DLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET);
reg = ECCB1DLLPICODER0 + channel * DDRIOCCC_CH_OFFSET;
temp = msg_port_alt_read(DDRPHY, reg);
temp >>= 24;
temp &= 0x3F;
temp &= 0x3f;
/* Adjust PI_COUNT */
pi_count += temp;
@ -938,17 +935,16 @@ uint32_t get_wctl(uint8_t channel, uint8_t rank)
*/
void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting)
{
uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL);
uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL;
ENTERFN();
DPF(D_TRN, "Vref ch%d ln%d : val=%03X\n",
channel, byte_lane, setting);
mrc_alt_write_mask(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) +
((byte_lane >> 1) * DDRIODQ_BL_OFFSET)),
(vref_codes[setting] << 2),
(BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2));
mrc_alt_write_mask(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET +
(byte_lane >> 1) * DDRIODQ_BL_OFFSET,
vref_codes[setting] << 2, 0xfc);
/*
* need to wait ~300ns for Vref to settle
@ -969,15 +965,15 @@ uint32_t get_vref(uint8_t channel, uint8_t byte_lane)
{
uint8_t j;
uint32_t ret_val = sizeof(vref_codes) / 2;
uint32_t reg = (byte_lane & 0x1) ? (B1VREFCTL) : (B0VREFCTL);
uint32_t reg = (byte_lane & 0x1) ? B1VREFCTL : B0VREFCTL;
uint32_t temp;
ENTERFN();
temp = msg_port_alt_read(DDRPHY, (reg + (channel * DDRIODQ_CH_OFFSET) +
((byte_lane >> 1) * DDRIODQ_BL_OFFSET)));
temp = msg_port_alt_read(DDRPHY, reg + channel * DDRIODQ_CH_OFFSET +
(byte_lane >> 1) * DDRIODQ_BL_OFFSET);
temp >>= 2;
temp &= 0x3F;
temp &= 0x3f;
for (j = 0; j < sizeof(vref_codes); j++) {
if (vref_codes[j] == temp) {
@ -997,7 +993,7 @@ uint32_t get_vref(uint8_t channel, uint8_t byte_lane)
*/
uint32_t get_addr(uint8_t channel, uint8_t rank)
{
uint32_t offset = 0x02000000; /* 32MB */
uint32_t offset = 32 * 1024 * 1024; /* 32MB */
/* Begin product specific code */
if (channel > 0) {
@ -1040,8 +1036,8 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
uint32_t address = get_addr(channel, rank);
/* initialise msk[] */
msk[0] = rcvn ? BIT1 : BIT9; /* BL0 */
msk[1] = rcvn ? BIT0 : BIT8; /* BL1 */
msk[0] = rcvn ? (1 << 1) : (1 << 9); /* BL0 */
msk[1] = rcvn ? (1 << 0) : (1 << 8); /* BL1 */
/* cycle through each byte lane group */
for (bl_grp = 0; bl_grp < (NUM_BYTE_LANES / bl_divisor) / 2; bl_grp++) {
@ -1056,9 +1052,9 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
* DQTRAINSTS register
*/
sampled_val[j] = msg_port_alt_read(DDRPHY,
(DQTRAINSTS +
(bl_grp * DDRIODQ_BL_OFFSET) +
(channel * DDRIODQ_CH_OFFSET)));
DQTRAINSTS +
bl_grp * DDRIODQ_BL_OFFSET +
channel * DDRIODQ_CH_OFFSET);
}
/*
@ -1076,7 +1072,7 @@ uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
num_0s++;
}
if (num_1s > num_0s)
ret_val |= (1 << (bl + (bl_grp * 2)));
ret_val |= (1 << (bl + bl_grp * 2));
}
}
@ -1116,10 +1112,10 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
/* increase sample delay by 26 PI (0.2 CLK) */
if (rcvn) {
set_rcvn(channel, rank, bl,
delay[bl] + (sample * SAMPLE_DLY));
delay[bl] + sample * SAMPLE_DLY);
} else {
set_wdqs(channel, rank, bl,
delay[bl] + (sample * SAMPLE_DLY));
delay[bl] + sample * SAMPLE_DLY);
}
}
@ -1129,7 +1125,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
DPF(D_TRN,
"Find rising edge %s ch%d rnk%d: #%d dly=%d dqs=%02X\n",
(rcvn ? "RCVN" : "WDQS"), channel, rank, sample,
rcvn ? "RCVN" : "WDQS", channel, rank, sample,
sample * SAMPLE_DLY, sample_result[sample]);
}
@ -1137,7 +1133,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
* This pattern will help determine where we landed and ultimately
* how to place RCVEN/WDQS.
*/
for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
/* build transition_pattern (MSB is 1st sample) */
transition_pattern = 0;
for (sample = 0; sample < SAMPLE_CNT; sample++) {
@ -1202,7 +1198,7 @@ void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
/* take a sample */
temp = sample_dqs(mrc_params, channel, rank, rcvn);
/* check all each byte lane for proper edge */
for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
if (temp & (1 << bl)) {
/* sampled "1" */
if (direction[bl] == BACKWARD) {
@ -1340,10 +1336,10 @@ void lfsr32(uint32_t *lfsr_ptr)
lfsr = *lfsr_ptr;
for (i = 0; i < 32; i++) {
bit = 1 ^ (lfsr & BIT0);
bit = bit ^ ((lfsr & BIT1) >> 1);
bit = bit ^ ((lfsr & BIT2) >> 2);
bit = bit ^ ((lfsr & BIT22) >> 22);
bit = 1 ^ (lfsr & 1);
bit = bit ^ ((lfsr & 2) >> 1);
bit = bit ^ ((lfsr & 4) >> 2);
bit = bit ^ ((lfsr & 0x400000) >> 22);
lfsr = ((lfsr >> 1) | (bit << 31));
}
@ -1362,16 +1358,16 @@ void clear_pointers(void)
for (channel = 0; channel < NUM_CHANNELS; channel++) {
for (bl = 0; bl < NUM_BYTE_LANES; bl++) {
mrc_alt_write_mask(DDRPHY,
(B01PTRCTL1 +
(channel * DDRIODQ_CH_OFFSET) +
((bl >> 1) * DDRIODQ_BL_OFFSET)),
~BIT8, BIT8);
B01PTRCTL1 +
channel * DDRIODQ_CH_OFFSET +
(bl >> 1) * DDRIODQ_BL_OFFSET,
~(1 << 8), (1 << 8));
mrc_alt_write_mask(DDRPHY,
(B01PTRCTL1 +
(channel * DDRIODQ_CH_OFFSET) +
((bl >> 1) * DDRIODQ_BL_OFFSET)),
BIT8, BIT8);
B01PTRCTL1 +
channel * DDRIODQ_CH_OFFSET +
(bl >> 1) * DDRIODQ_BL_OFFSET,
(1 << 8), (1 << 8));
}
}
@ -1412,7 +1408,7 @@ static void print_timings_internal(uint8_t algo, uint8_t channel, uint8_t rank,
break;
}
for (bl = 0; bl < (NUM_BYTE_LANES / bl_divisor); bl++) {
for (bl = 0; bl < NUM_BYTE_LANES / bl_divisor; bl++) {
switch (algo) {
case RCVN:
DPF(D_INFO, " %03d", get_rcvn(channel, rank, bl));

34
arch/x86/cpu/quark/mrc_util.h
Unescape View File

@ -41,40 +41,6 @@
#define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__)
#define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__)
/* Generic Register Bits */
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
/* Message Bus Port */
#define MEM_CTLR 0x01
#define HOST_BRIDGE 0x03

1205
arch/x86/cpu/quark/smc.c
View File

File diff suppressed because it is too large Load Diff

349
arch/x86/cpu/quark/smc.h
Unescape View File

@ -24,46 +24,133 @@
#define DPMC1 0x07
#define DRFC 0x08
#define DSCH 0x09
#define DCAL 0x0A
#define DRMC 0x0B
#define PMSTS 0x0C
#define DCO 0x0F
#define DCAL 0x0a
#define DRMC 0x0b
#define PMSTS 0x0c
#define DCO 0x0f
#define DSTAT 0x20
#define SSKPD0 0x4A
#define SSKPD1 0x4B
#define SSKPD0 0x4a
#define SSKPD1 0x4b
#define DECCCTRL 0x60
#define DECCSTAT 0x61
#define DECCSBECNT 0x62
#define DECCSBECA 0x68
#define DECCSBECS 0x69
#define DECCDBECA 0x6A
#define DECCDBECS 0x6B
#define DECCDBECA 0x6a
#define DECCDBECS 0x6b
#define DFUSESTAT 0x70
#define SCRMSEED 0x80
#define SCRMLO 0x81
#define SCRMHI 0x82
/* DRP register defines */
#define DRP_RKEN0 (1 << 0)
#define DRP_RKEN1 (1 << 1)
#define DRP_PRI64BSPLITEN (1 << 13)
#define DRP_ADDRMAP_MAP0 (1 << 14)
#define DRP_ADDRMAP_MAP1 (1 << 15)
#define DRP_ADDRMAP_MASK 0x0000c000
/* DTR0 register defines */
#define DTR0_DFREQ_MASK 0x00000003
#define DTR0_TRP_MASK 0x000000f0
#define DTR0_TRCD_MASK 0x00000f00
#define DTR0_TCL_MASK 0x00007000
/* DTR1 register defines */
#define DTR1_TWCL_MASK 0x00000007
#define DTR1_TCMD_MASK 0x00000030
#define DTR1_TWTP_MASK 0x00000f00
#define DTR1_TCCD_12CLK (1 << 12)
#define DTR1_TCCD_18CLK (1 << 13)
#define DTR1_TCCD_MASK 0x00003000
#define DTR1_TFAW_MASK 0x000f0000
#define DTR1_TRAS_MASK 0x00f00000
#define DTR1_TRRD_MASK 0x03000000
#define DTR1_TRTP_MASK 0x70000000
/* DTR2 register defines */
#define DTR2_TRRDR_MASK 0x00000007
#define DTR2_TWWDR_MASK 0x00000700
#define DTR2_TRWDR_MASK 0x000f0000
/* DTR3 register defines */
#define DTR3_TWRDR_MASK 0x00000007
#define DTR3_TXXXX_MASK 0x00000070
#define DTR3_TRWSR_MASK 0x00000f00
#define DTR3_TWRSR_MASK 0x0001e000
#define DTR3_TXP_MASK 0x00c00000
/* DTR4 register defines */
#define DTR4_WRODTSTRT_MASK 0x00000003
#define DTR4_WRODTSTOP_MASK 0x00000070
#define DTR4_XXXX1_MASK 0x00000700
#define DTR4_XXXX2_MASK 0x00007000
#define DTR4_ODTDIS (1 << 15)
#define DTR4_TRGSTRDIS (1 << 16)
/* DPMC0 register defines */
#define DPMC0_PCLSTO_MASK 0x00070000
#define DPMC0_PREAPWDEN (1 << 21)
#define DPMC0_DYNSREN (1 << 23)
#define DPMC0_CLKGTDIS (1 << 24)
#define DPMC0_DISPWRDN (1 << 25)
#define DPMC0_ENPHYCLKGATE (1 << 29)
/* DRFC register defines */
#define DRFC_TREFI_MASK 0x00007000
#define DRFC_REFDBTCLR (1 << 21)
/* DSCH register defines */
#define DSCH_OOODIS (1 << 8)
#define DSCH_OOOST3DIS (1 << 9)
#define DSCH_NEWBYPDIS (1 << 12)
/* DCAL register defines */
#define DCAL_ZQCINT_MASK 0x00000700
#define DCAL_SRXZQCL_MASK 0x00003000
/* DRMC register defines */
#define DRMC_CKEMODE (1 << 4)
#define DRMC_ODTMODE (1 << 12)
#define DRMC_COLDWAKE (1 << 16)
/* PMSTS register defines */
#define PMSTS_DISR (1 << 0)
/* DCO register defines */
#define DCO_DRPLOCK (1 << 0)
#define DCO_CPGCLOCK (1 << 8)
#define DCO_PMICTL (1 << 28)
#define DCO_PMIDIS (1 << 29)
#define DCO_IC (1 << 31)
/* DECCCTRL register defines */
#define DECCCTRL_SBEEN (1 << 0)
#define DECCCTRL_DBEEN (1 << 1)
#define DECCCTRL_ENCBGEN (1 << 17)
/* DRAM init command */
#define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6))
#define DCMD_REF(rnk) (1 | ((rnk) << 22))
#define DCMD_PRE(rnk) (2 | ((rnk) << 22))
#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (BIT10 << 6))
#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (0x400 << 6))
#define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6))
#define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6))
#define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6))
#define DCMD_ZQCS(rnk) (6 | ((rnk) << 22))
#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (BIT10 << 6))
#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (0x400 << 6))
#define DCMD_NOP(rnk) (7 | ((rnk) << 22))
#define DDR3_EMRS1_DIC_40 (0)
#define DDR3_EMRS1_DIC_34 (1)
#define DDR3_EMRS1_DIC_40 0
#define DDR3_EMRS1_DIC_34 1
#define DDR3_EMRS1_RTTNOM_0 (0)
#define DDR3_EMRS1_RTTNOM_60 (0x04)
#define DDR3_EMRS1_RTTNOM_120 (0x40)
#define DDR3_EMRS1_RTTNOM_40 (0x44)
#define DDR3_EMRS1_RTTNOM_20 (0x200)
#define DDR3_EMRS1_RTTNOM_30 (0x204)
#define DDR3_EMRS1_RTTNOM_0 0
#define DDR3_EMRS1_RTTNOM_60 0x04
#define DDR3_EMRS1_RTTNOM_120 0x40
#define DDR3_EMRS1_RTTNOM_40 0x44
#define DDR3_EMRS1_RTTNOM_20 0x200
#define DDR3_EMRS1_RTTNOM_30 0x204
#define DDR3_EMRS2_RTTWR_60 (1 << 9)
#define DDR3_EMRS2_RTTWR_120 (1 << 10)
@ -80,87 +167,87 @@
#define DQOBSCKEBBCTL 0x0000
#define DQDLLTXCTL 0x0004
#define DQDLLRXCTL 0x0008
#define DQMDLLCTL 0x000C
#define DQMDLLCTL 0x000c
#define B0RXIOBUFCTL 0x0010
#define B0VREFCTL 0x0014
#define B0RXOFFSET1 0x0018
#define B0RXOFFSET0 0x001C
#define B0RXOFFSET0 0x001c
#define B1RXIOBUFCTL 0x0020
#define B1VREFCTL 0x0024
#define B1RXOFFSET1 0x0028
#define B1RXOFFSET0 0x002C
#define B1RXOFFSET0 0x002c
#define DQDFTCTL 0x0030
#define DQTRAINSTS 0x0034
#define B1DLLPICODER0 0x0038
#define B0DLLPICODER0 0x003C
#define B0DLLPICODER0 0x003c
#define B1DLLPICODER1 0x0040
#define B0DLLPICODER1 0x0044
#define B1DLLPICODER2 0x0048
#define B0DLLPICODER2 0x004C
#define B0DLLPICODER2 0x004c
#define B1DLLPICODER3 0x0050
#define B0DLLPICODER3 0x0054
#define B1RXDQSPICODE 0x0058
#define B0RXDQSPICODE 0x005C
#define B0RXDQSPICODE 0x005c
#define B1RXDQPICODER32 0x0060
#define B1RXDQPICODER10 0x0064
#define B0RXDQPICODER32 0x0068
#define B0RXDQPICODER10 0x006C
#define B0RXDQPICODER10 0x006c
#define B01PTRCTL0 0x0070
#define B01PTRCTL1 0x0074
#define B01DBCTL0 0x0078
#define B01DBCTL1 0x007C
#define B01DBCTL1 0x007c
#define B0LATCTL0 0x0080
#define B1LATCTL0 0x0084
#define B01LATCTL1 0x0088
#define B0ONDURCTL 0x008C
#define B0ONDURCTL 0x008c
#define B1ONDURCTL 0x0090
#define B0OVRCTL 0x0094
#define B1OVRCTL 0x0098
#define DQCTL 0x009C
#define B0RK2RKCHGPTRCTRL 0x00A0
#define B1RK2RKCHGPTRCTRL 0x00A4
#define DQRK2RKCTL 0x00A8
#define DQRK2RKPTRCTL 0x00AC
#define B0RK2RKLAT 0x00B0
#define B1RK2RKLAT 0x00B4
#define DQCLKALIGNREG0 0x00B8
#define DQCLKALIGNREG1 0x00BC
#define DQCLKALIGNREG2 0x00C0
#define DQCLKALIGNSTS0 0x00C4
#define DQCLKALIGNSTS1 0x00C8
#define DQCLKGATE 0x00CC
#define B0COMPSLV1 0x00D0
#define B1COMPSLV1 0x00D4
#define B0COMPSLV2 0x00D8
#define B1COMPSLV2 0x00DC
#define B0COMPSLV3 0x00E0
#define B1COMPSLV3 0x00E4
#define DQVISALANECR0TOP 0x00E8
#define DQVISALANECR1TOP 0x00EC
#define DQVISACONTROLCRTOP 0x00F0
#define DQVISALANECR0BL 0x00F4
#define DQVISALANECR1BL 0x00F8
#define DQVISACONTROLCRBL 0x00FC
#define DQTIMINGCTRL 0x010C
#define DQCTL 0x009c
#define B0RK2RKCHGPTRCTRL 0x00a0
#define B1RK2RKCHGPTRCTRL 0x00a4
#define DQRK2RKCTL 0x00a8
#define DQRK2RKPTRCTL 0x00ac
#define B0RK2RKLAT 0x00b0
#define B1RK2RKLAT 0x00b4
#define DQCLKALIGNREG0 0x00b8
#define DQCLKALIGNREG1 0x00bc
#define DQCLKALIGNREG2 0x00c0
#define DQCLKALIGNSTS0 0x00c4
#define DQCLKALIGNSTS1 0x00c8
#define DQCLKGATE 0x00cc
#define B0COMPSLV1 0x00d0
#define B1COMPSLV1 0x00d4
#define B0COMPSLV2 0x00d8
#define B1COMPSLV2 0x00dc
#define B0COMPSLV3 0x00e0
#define B1COMPSLV3 0x00e4
#define DQVISALANECR0TOP 0x00e8
#define DQVISALANECR1TOP 0x00ec
#define DQVISACONTROLCRTOP 0x00f0
#define DQVISALANECR0BL 0x00f4
#define DQVISALANECR1BL 0x00f8
#define DQVISACONTROLCRBL 0x00fc
#define DQTIMINGCTRL 0x010c
/* CH0-ECC */
#define ECCDLLTXCTL 0x2004
#define ECCDLLRXCTL 0x2008
#define ECCMDLLCTL 0x200C
#define ECCMDLLCTL 0x200c
#define ECCB1DLLPICODER0 0x2038
#define ECCB1DLLPICODER1 0x2040
#define ECCB1DLLPICODER2 0x2048
#define ECCB1DLLPICODER3 0x2050
#define ECCB01DBCTL0 0x2078
#define ECCB01DBCTL1 0x207C
#define ECCCLKALIGNREG0 0x20B8
#define ECCCLKALIGNREG1 0x20BC
#define ECCCLKALIGNREG2 0x20C0
#define ECCB01DBCTL1 0x207c
#define ECCCLKALIGNREG0 0x20b8
#define ECCCLKALIGNREG1 0x20bc
#define ECCCLKALIGNREG2 0x20c0
/* CH0-CMD */
#define CMDOBSCKEBBCTL 0x4800
#define CMDDLLTXCTL 0x4808
#define CMDDLLRXCTL 0x480C
#define CMDDLLRXCTL 0x480c
#define CMDMDLLCTL 0x4810
#define CMDRCOMPODT 0x4814
#define CMDDLLPICODER0 0x4820
@ -170,30 +257,30 @@
#define CMDCLKALIGNREG0 0x4850
#define CMDCLKALIGNREG1 0x4854
#define CMDCLKALIGNREG2 0x4858
#define CMDPMCONFIG0 0x485C
#define CMDPMCONFIG0 0x485c
#define CMDPMDLYREG0 0x4860
#define CMDPMDLYREG1 0x4864
#define CMDPMDLYREG2 0x4868
#define CMDPMDLYREG3 0x486C
#define CMDPMDLYREG3 0x486c
#define CMDPMDLYREG4 0x4870
#define CMDCLKALIGNSTS0 0x4874
#define CMDCLKALIGNSTS1 0x4878
#define CMDPMSTS0 0x487C
#define CMDPMSTS0 0x487c
#define CMDPMSTS1 0x4880
#define CMDCOMPSLV 0x4884
#define CMDBONUS0 0x488C
#define CMDBONUS0 0x488c
#define CMDBONUS1 0x4890
#define CMDVISALANECR0 0x4894
#define CMDVISALANECR1 0x4898
#define CMDVISACONTROLCR 0x489C
#define CMDCLKGATE 0x48A0
#define CMDTIMINGCTRL 0x48A4
#define CMDVISACONTROLCR 0x489c
#define CMDCLKGATE 0x48a0
#define CMDTIMINGCTRL 0x48a4
/* CH0-CLK-CTL */
#define CCOBSCKEBBCTL 0x5800
#define CCRCOMPIO 0x5804
#define CCDLLTXCTL 0x5808
#define CCDLLRXCTL 0x580C
#define CCDLLRXCTL 0x580c
#define CCMDLLCTL 0x5810
#define CCRCOMPODT 0x5814
#define CCDLLPICODER0 0x5820
@ -205,123 +292,123 @@
#define CCCLKALIGNREG0 0x5850
#define CCCLKALIGNREG1 0x5854
#define CCCLKALIGNREG2 0x5858
#define CCPMCONFIG0 0x585C
#define CCPMCONFIG0 0x585c
#define CCPMDLYREG0 0x5860
#define CCPMDLYREG1 0x5864
#define CCPMDLYREG2 0x5868
#define CCPMDLYREG3 0x586C
#define CCPMDLYREG3 0x586c
#define CCPMDLYREG4 0x5870
#define CCCLKALIGNSTS0 0x5874
#define CCCLKALIGNSTS1 0x5878
#define CCPMSTS0 0x587C
#define CCPMSTS0 0x587c
#define CCPMSTS1 0x5880
#define CCCOMPSLV1 0x5884
#define CCCOMPSLV2 0x5888
#define CCCOMPSLV3 0x588C
#define CCCOMPSLV3 0x588c
#define CCBONUS0 0x5894
#define CCBONUS1 0x5898
#define CCVISALANECR0 0x589C
#define CCVISALANECR1 0x58A0
#define CCVISACONTROLCR 0x58A4
#define CCCLKGATE 0x58A8
#define CCTIMINGCTL 0x58AC
#define CCVISALANECR0 0x589c
#define CCVISALANECR1 0x58a0
#define CCVISACONTROLCR 0x58a4
#define CCCLKGATE 0x58a8
#define CCTIMINGCTL 0x58ac
/* COMP */
#define CMPCTRL 0x6800
#define SOFTRSTCNTL 0x6804
#define MSCNTR 0x6808
#define NMSCNTRL 0x680C
#define NMSCNTRL 0x680c
#define LATCH1CTL 0x6814
#define COMPVISALANECR0 0x681C
#define COMPVISALANECR0 0x681c
#define COMPVISALANECR1 0x6820
#define COMPVISACONTROLCR 0x6824
#define COMPBONUS0 0x6830
#define TCOCNTCTRL 0x683C
#define TCOCNTCTRL 0x683c
#define DQANAODTPUCTL 0x6840
#define DQANAODTPDCTL 0x6844
#define DQANADRVPUCTL 0x6848
#define DQANADRVPDCTL 0x684C
#define DQANADRVPDCTL 0x684c
#define DQANADLYPUCTL 0x6850
#define DQANADLYPDCTL 0x6854
#define DQANATCOPUCTL 0x6858
#define DQANATCOPDCTL 0x685C
#define DQANATCOPDCTL 0x685c
#define CMDANADRVPUCTL 0x6868
#define CMDANADRVPDCTL 0x686C
#define CMDANADRVPDCTL 0x686c
#define CMDANADLYPUCTL 0x6870
#define CMDANADLYPDCTL 0x6874
#define CLKANAODTPUCTL 0x6880
#define CLKANAODTPDCTL 0x6884
#define CLKANADRVPUCTL 0x6888
#define CLKANADRVPDCTL 0x688C
#define CLKANADRVPDCTL 0x688c
#define CLKANADLYPUCTL 0x6890
#define CLKANADLYPDCTL 0x6894
#define CLKANATCOPUCTL 0x6898
#define CLKANATCOPDCTL 0x689C
#define DQSANAODTPUCTL 0x68A0
#define DQSANAODTPDCTL 0x68A4
#define DQSANADRVPUCTL 0x68A8
#define DQSANADRVPDCTL 0x68AC
#define DQSANADLYPUCTL 0x68B0
#define DQSANADLYPDCTL 0x68B4
#define DQSANATCOPUCTL 0x68B8
#define DQSANATCOPDCTL 0x68BC
#define CTLANADRVPUCTL 0x68C8
#define CTLANADRVPDCTL 0x68CC
#define CTLANADLYPUCTL 0x68D0
#define CTLANADLYPDCTL 0x68D4
#define CHNLBUFSTATIC 0x68F0
#define COMPOBSCNTRL 0x68F4
#define COMPBUFFDBG0 0x68F8
#define COMPBUFFDBG1 0x68FC
#define CLKANATCOPDCTL 0x689c
#define DQSANAODTPUCTL 0x68a0
#define DQSANAODTPDCTL 0x68a4
#define DQSANADRVPUCTL 0x68a8
#define DQSANADRVPDCTL 0x68ac
#define DQSANADLYPUCTL 0x68b0
#define DQSANADLYPDCTL 0x68b4
#define DQSANATCOPUCTL 0x68b8
#define DQSANATCOPDCTL 0x68bc
#define CTLANADRVPUCTL 0x68c8
#define CTLANADRVPDCTL 0x68cc
#define CTLANADLYPUCTL 0x68d0
#define CTLANADLYPDCTL 0x68d4
#define CHNLBUFSTATIC 0x68f0
#define COMPOBSCNTRL 0x68f4
#define COMPBUFFDBG0 0x68f8
#define COMPBUFFDBG1 0x68fc
#define CFGMISCCH0 0x6900
#define COMPEN0CH0 0x6904
#define COMPEN1CH0 0x6908
#define COMPEN2CH0 0x690C
#define COMPEN2CH0 0x690c
#define STATLEGEN0CH0 0x6910
#define STATLEGEN1CH0 0x6914
#define DQVREFCH0 0x6918
#define CMDVREFCH0 0x691C
#define CMDVREFCH0 0x691c
#define CLKVREFCH0 0x6920
#define DQSVREFCH0 0x6924
#define CTLVREFCH0 0x6928
#define TCOVREFCH0 0x692C
#define TCOVREFCH0 0x692c
#define DLYSELCH0 0x6930
#define TCODRAMBUFODTCH0 0x6934
#define CCBUFODTCH0 0x6938
#define RXOFFSETCH0 0x693C
#define RXOFFSETCH0 0x693c
#define DQODTPUCTLCH0 0x6940
#define DQODTPDCTLCH0 0x6944
#define DQDRVPUCTLCH0 0x6948
#define DQDRVPDCTLCH0 0x694C
#define DQDRVPDCTLCH0 0x694c
#define DQDLYPUCTLCH0 0x6950
#define DQDLYPDCTLCH0 0x6954
#define DQTCOPUCTLCH0 0x6958
#define DQTCOPDCTLCH0 0x695C
#define DQTCOPDCTLCH0 0x695c
#define CMDDRVPUCTLCH0 0x6968
#define CMDDRVPDCTLCH0 0x696C
#define CMDDRVPDCTLCH0 0x696c
#define CMDDLYPUCTLCH0 0x6970
#define CMDDLYPDCTLCH0 0x6974
#define CLKODTPUCTLCH0 0x6980
#define CLKODTPDCTLCH0 0x6984
#define CLKDRVPUCTLCH0 0x6988
#define CLKDRVPDCTLCH0 0x698C
#define CLKDRVPDCTLCH0 0x698c
#define CLKDLYPUCTLCH0 0x6990
#define CLKDLYPDCTLCH0 0x6994
#define CLKTCOPUCTLCH0 0x6998
#define CLKTCOPDCTLCH0 0x699C
#define DQSODTPUCTLCH0 0x69A0
#define DQSODTPDCTLCH0 0x69A4
#define DQSDRVPUCTLCH0 0x69A8
#define DQSDRVPDCTLCH0 0x69AC
#define DQSDLYPUCTLCH0 0x69B0
#define DQSDLYPDCTLCH0 0x69B4
#define DQSTCOPUCTLCH0 0x69B8
#define DQSTCOPDCTLCH0 0x69BC
#define CTLDRVPUCTLCH0 0x69C8
#define CTLDRVPDCTLCH0 0x69CC
#define CTLDLYPUCTLCH0 0x69D0
#define CTLDLYPDCTLCH0 0x69D4
#define FNLUPDTCTLCH0 0x69F0
#define CLKTCOPDCTLCH0 0x699c
#define DQSODTPUCTLCH0 0x69a0
#define DQSODTPDCTLCH0 0x69a4
#define DQSDRVPUCTLCH0 0x69a8
#define DQSDRVPDCTLCH0 0x69ac
#define DQSDLYPUCTLCH0 0x69b0
#define DQSDLYPDCTLCH0 0x69b4
#define DQSTCOPUCTLCH0 0x69b8
#define DQSTCOPDCTLCH0 0x69bc
#define CTLDRVPUCTLCH0 0x69c8
#define CTLDRVPDCTLCH0 0x69cc
#define CTLDLYPUCTLCH0 0x69d0
#define CTLDLYPDCTLCH0 0x69d4
#define FNLUPDTCTLCH0 0x69f0
/* PLL */
#define MPLLCTRL0 0x7800
@ -332,17 +419,17 @@
#define MPLLDFT 0x7828
#define MPLLMON0CTL 0x7830
#define MPLLMON1CTL 0x7838
#define MPLLMON2CTL 0x783C
#define MPLLMON2CTL 0x783c
#define SFRTRIM 0x7850
#define MPLLDFTOUT0 0x7858
#define MPLLDFTOUT1 0x785C
#define MPLLDFTOUT1 0x785c
#define MASTERRSTN 0x7880
#define PLLLOCKDEL 0x7884
#define SFRDEL 0x7888
#define CRUVISALANECR0 0x78F0
#define CRUVISALANECR1 0x78F4
#define CRUVISACONTROLCR 0x78F8
#define IOSFVISALANECR0 0x78FC
#define CRUVISALANECR0 0x78f0
#define CRUVISALANECR1 0x78f4
#define CRUVISACONTROLCR 0x78f8
#define IOSFVISALANECR0 0x78fc
#define IOSFVISALANECR1 0x7900
#define IOSFVISACONTROLCR 0x7904
@ -350,7 +437,7 @@
/* DRAM Specific Message Bus OpCodes */
#define MSG_OP_DRAM_INIT 0x68
#define MSG_OP_DRAM_WAKE 0xCA
#define MSG_OP_DRAM_WAKE 0xca
#define SAMPLE_SIZE 6
@ -377,9 +464,9 @@
/* offset into "vref_codes[]" for minimum allowed VREF setting */
#define VREF_MIN 0x00
/* offset into "vref_codes[]" for maximum allowed VREF setting */
#define VREF_MAX 0x3F
#define VREF_MAX 0x3f
#define RDQS_MIN 0x00 /* minimum RDQS delay value */
#define RDQS_MAX 0x3F /* maximum RDQS delay value */
#define RDQS_MAX 0x3f /* maximum RDQS delay value */
/* how many WDQ codes to jump while margining */
#define WDQ_STEP 1

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