- use watchdog to reset PXA250 systems - added progress callbacks to (some of the) ARM code - update for Cogent CSB226 board * Add support for FPS860 boardmaster
wdenk
22 years ago
parent
e95b61cfb0
commit
384ae02506
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/*
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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/*
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* board/config.h - configuration options, board specific |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* High Level Configuration Options |
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* (easy to change) |
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*/ |
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#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ |
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#define CONFIG_FPS860L 1 /* ...on a FingerPrint Sensor */ |
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#undef CONFIG_8xx_CONS_SMC1 |
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#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ |
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#undef CONFIG_8xx_CONS_NONE |
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#define CONFIG_BAUDRATE 115200 |
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#if 0 |
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
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#else |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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#endif |
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#define CONFIG_BOOTCOMMAND "bootm 40040000" /* autoboot command */ |
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
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#define CONFIG_BOARD_TYPES 1 /* support board types */ |
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#define CONFIG_BOOTARGS "root=/dev/nfs rw " \ |
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"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
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"nfsaddrs=10.0.0.99:10.0.0.2" |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
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#undef CONFIG_WATCHDOG /* watchdog disabled */ |
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#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL |
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
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CFG_CMD_ASKENV | \
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CFG_CMD_DHCP | \
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CFG_CMD_DATE ) |
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
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#include <cmd_confdefs.h> |
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/*
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* Miscellaneous configurable options |
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*/ |
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#define CFG_LONGHELP /* undef to save memory */ |
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#else |
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
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#endif |
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
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#define CFG_MAXARGS 16 /* max number of command args */ |
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
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#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
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/*
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* Low Level Configuration Settings |
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* (address mappings, register initial values, etc.) |
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* You should know what you are doing if you make changes here. |
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*/ |
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register |
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*/ |
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#define CFG_IMMR 0xFFF00000 |
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM) |
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*/ |
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#define CFG_INIT_RAM_ADDR CFG_IMMR |
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration |
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* (Set up by the startup code) |
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* Please note that CFG_SDRAM_BASE _must_ start at 0 |
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*/ |
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#define CFG_SDRAM_BASE 0x00000000 |
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#define CFG_FLASH_BASE 0x40000000 |
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
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#define CFG_MONITOR_BASE CFG_FLASH_BASE |
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
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/*
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* For booting Linux, the board info and command line data |
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* have to be in the first 8 MB of memory, since this is |
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* the maximum mapped by the Linux kernel during initialization. |
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*/ |
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
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/*-----------------------------------------------------------------------
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* FLASH organization |
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*/ |
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
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#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
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#define CFG_ENV_IS_IN_FLASH 1 |
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#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
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/* Address and size of Redundant Environment Sector */ |
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) |
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
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/*-----------------------------------------------------------------------
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* Hardware Information Block |
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*/ |
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#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
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#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
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#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
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/*-----------------------------------------------------------------------
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* Cache Configuration |
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*/ |
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
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#endif |
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9 |
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* SYPCR can only be written once after reset! |
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*----------------------------------------------------------------------- |
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
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*/ |
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#if defined(CONFIG_WATCHDOG) |
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
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#else |
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
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#endif |
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6 |
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*----------------------------------------------------------------------- |
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* PCMCIA config., multi-function pin tri-state |
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*/ |
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26 |
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*----------------------------------------------------------------------- |
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* Clear Reference Interrupt Status, Timebase freezing enabled |
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*/ |
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27 |
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*----------------------------------------------------------------------- |
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*/ |
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#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31 |
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*----------------------------------------------------------------------- |
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
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*/ |
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#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
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*----------------------------------------------------------------------- |
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* Reset PLL lock status sticky bit, timer expired status bit and timer |
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* interrupt status bit - leave PLL multiplication factor unchanged ! |
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*/ |
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#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) |
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27 |
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*----------------------------------------------------------------------- |
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* Set clock output, timebase and RTC source and divider, |
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* power management and some other internal clocks |
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*/ |
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#define SCCR_MASK SCCR_EBDF11 |
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#define CFG_SCCR (SCCR_TBS | \ |
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SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
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SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
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SCCR_DFALCD00) |
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/*-----------------------------------------------------------------------
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* PCMCIA stuff |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
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#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
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/*-----------------------------------------------------------------------
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* |
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*----------------------------------------------------------------------- |
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* |
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*/ |
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/*#define CFG_DER 0x2002000F*/ |
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#define CFG_DER 0 |
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/*
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* Init Memory Controller: |
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* |
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* BR0/1 and OR0/1 (FLASH) |
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*/ |
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#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
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#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any) |
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* but not too much to meddle with FLASH accesses |
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*/ |
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#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
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#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
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/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ |
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
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OR_SCY_5_CLK | OR_EHTR) |
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
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#define CFG_OR1_REMAP CFG_OR0_REMAP |
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#define CFG_OR1_PRELIM CFG_OR0_PRELIM |
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#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
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/*
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* BR2/3 and OR2/3 (SDRAM) |
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* |
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*/ |
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#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
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#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
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#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ |
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
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#define CFG_OR_TIMING_SDRAM 0x00000A00 |
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#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) |
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#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
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#define CFG_OR3_PRELIM CFG_OR2_PRELIM |
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#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
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/*
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* Memory Periodic Timer Prescaler |
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*/ |
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/* periodic timer for refresh */ |
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#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */ |
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/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ |
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#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
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#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ |
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/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ |
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#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
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#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
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/*
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* MAMR settings for SDRAM |
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*/ |
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/* 8 column SDRAM */ |
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#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
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/* 9 column SDRAM */ |
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#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
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MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
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MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
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/*
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* Internal Definitions |
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* |
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* Boot Flags |
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*/ |
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
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#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
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#endif /* __CONFIG_H */ |
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