Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>master
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/*
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* Copyright 2014 Freescale Semiconductor, Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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*/ |
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#ifndef __FSL_STREAM_ID_H |
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#define __FSL_STREAM_ID_H |
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/* Stream IDs on ls2085a devices are not hardwired and are
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* programmed by sw. There are a limited number of stream IDs |
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* available, and the partitioning of them is scenario dependent. |
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* This header defines the partitioning between legacy, PCI, |
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* and DPAA2 devices. |
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* |
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* This partitiong can be customized in this file depending |
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* on the specific hardware config-- e.g. perhaps not all |
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* PEX controllers are in use. |
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* |
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* On LS2085 stream IDs are programmed in AMQ registers (32-bits) for |
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* each of the different bus masters. The relationship between |
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* the AMQ registers and stream IDs is defined in the table below: |
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* AMQ bit streamID bit |
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* --------------------------- |
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* PL[18] 9 |
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* BMT[17] 8 |
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* VA[16] 7 |
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* [15] - |
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* ICID[14:7] - |
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* ICID[6:0] 6-0 |
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* ---------------------------- |
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*/ |
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#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ |
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#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ |
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#define FSL_INVALID_STREAM_ID 0 |
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#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) |
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/* legacy devices */ |
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#define FSL_USB1_STREAM_ID 1 |
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#define FSL_USB2_STREAM_ID 2 |
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#define FSL_SDMMC_STREAM_ID 3 |
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#define FSL_SATA1_STREAM_ID 4 |
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#define FSL_SATA2_STREAM_ID 5 |
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#define FSL_DMA_STREAM_ID 6 |
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/* PCI - programmed in PEXn_LUT by OS */ |
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/* 4 IDs per controller */ |
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#define FSL_PEX1_STREAM_ID_START 7 |
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#define FSL_PEX1_STREAM_ID_END 10 |
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#define FSL_PEX2_STREAM_ID_START 11 |
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#define FSL_PEX2_STREAM_ID_END 14 |
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#define FSL_PEX3_STREAM_ID_START 15 |
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#define FSL_PEX3_STREAM_ID_END 18 |
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#define FSL_PEX4_STREAM_ID_START 19 |
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#define FSL_PEX4_STREAM_ID_END 22 |
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/* DPAA2 - set in MC DPC and alloced by MC */ |
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#define FSL_DPAA2_STREAM_ID_START 23 |
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#define FSL_DPAA2_STREAM_ID_END 63 |
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#endif |
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