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Merge git://git.denx.de/u-boot-tegra

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master
Tom Rini 7 years ago
parent 4951e9420e ee92194acd
commit 3b19c1dbe0
15 changed files with 3125 additions and 0 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 1
      arch/arm/dts/Makefile
  2. 2203
      arch/arm/dts/tegra124-apalis.dts
  3. 2
      arch/arm/include/asm/arch-tegra/tegra_mmc.h
  4. 7
      arch/arm/mach-tegra/tegra124/Kconfig
  5. 30
      board/toradex/apalis-tk1/Kconfig
  6. 7
      board/toradex/apalis-tk1/MAINTAINERS
  7. 5
      board/toradex/apalis-tk1/Makefile
  8. 175
      board/toradex/apalis-tk1/apalis-tk1.c
  9. 117
      board/toradex/apalis-tk1/as3722_init.c
  10. 41
      board/toradex/apalis-tk1/as3722_init.h
  11. 287
      board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
  12. 47
      configs/apalis-tk1_defconfig
  13. 11
      drivers/mmc/Kconfig
  14. 16
      drivers/mmc/tegra_mmc.c
  15. 176
      include/configs/apalis-tk1.h

1
arch/arm/dts/Makefile
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@ -58,6 +58,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra30-colibri.dtb \
tegra30-tec-ng.dtb \
tegra114-dalmore.dtb \
tegra124-apalis.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-cei-tk1-som.dtb \

2203
arch/arm/dts/tegra124-apalis.dts
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File diff suppressed because it is too large Load Diff

2
arch/arm/include/asm/arch-tegra/tegra_mmc.h
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@ -108,6 +108,8 @@ struct tegra_mmc {
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
#define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK (1 << 17)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)

7
arch/arm/mach-tegra/tegra124/Kconfig
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@ -4,6 +4,12 @@ choice
prompt "Tegra124 board select"
optional
config TARGET_APALIS_TK1
bool "Toradex Apalis TK1 module"
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select ARCH_SUPPORT_PSCI
config TARGET_JETSON_TK1
bool "NVIDIA Tegra124 Jetson TK1 board"
select BOARD_LATE_INIT
@ -46,5 +52,6 @@ source "board/cei/cei-tk1-som/Kconfig"
source "board/nvidia/jetson-tk1/Kconfig"
source "board/nvidia/nyan-big/Kconfig"
source "board/nvidia/venice2/Kconfig"
source "board/toradex/apalis-tk1/Kconfig"
endif

30
board/toradex/apalis-tk1/Kconfig
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@ -0,0 +1,30 @@
if TARGET_APALIS_TK1
config SYS_BOARD
default "apalis-tk1"
config SYS_VENDOR
default "toradex"
config SYS_CONFIG_NAME
default "apalis-tk1"
config TDX_CFG_BLOCK
default y
config TDX_HAVE_MMC
default y
config TDX_CFG_BLOCK_DEV
default "0"
config TDX_CFG_BLOCK_PART
default "1"
# Toradex config block in eMMC, at the end of 1st "boot sector"
config TDX_CFG_BLOCK_OFFSET
default "-512"
source "board/toradex/common/Kconfig"
endif

7
board/toradex/apalis-tk1/MAINTAINERS
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@ -0,0 +1,7 @@
Apalis TK1
M: Marcel Ziswiler <marcel.ziswiler@toradex.com>
S: Maintained
F: board/toradex/apalis-tk1/
F: include/configs/apalis-tk1.h
F: configs/apalis-tk1_defconfig
F: arch/arm/dts/tegra124-apalis.dtb

5
board/toradex/apalis-tk1/Makefile
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@ -0,0 +1,5 @@
# Copyright (c) 2016 Toradex, Inc.
# SPDX-License-Identifier: GPL-2.0+
obj-y += as3722_init.o
obj-y += apalis-tk1.o

175
board/toradex/apalis-tk1/apalis-tk1.c
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/*
* Copyright (c) 2016 Toradex, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch-tegra/ap.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
#include <power/as3722.h>
#include "../common/tdx-common.h"
#include "pinmux-config-apalis-tk1.h"
#define LAN_RESET_N TEGRA_GPIO(S, 2)
int arch_misc_init(void)
{
if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
NVBOOTTYPE_RECOVERY)
printf("USB recovery mode\n");
return 0;
}
int checkboard(void)
{
puts("Model: Toradex Apalis TK1 2GB\n");
return 0;
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
return ft_common_board_setup(blob, bd);
}
#endif
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
*/
void pinmux_init(void)
{
pinmux_clear_tristate_input_clamping();
gpio_config_table(apalis_tk1_gpio_inits,
ARRAY_SIZE(apalis_tk1_gpio_inits));
pinmux_config_pingrp_table(apalis_tk1_pingrps,
ARRAY_SIZE(apalis_tk1_pingrps));
pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
ARRAY_SIZE(apalis_tk1_drvgrps));
}
#ifdef CONFIG_PCI_TEGRA
int tegra_pcie_board_init(void)
{
struct udevice *pmic;
int err;
err = as3722_init(&pmic);
if (err) {
error("failed to initialize AS3722 PMIC: %d\n", err);
return err;
}
err = as3722_sd_enable(pmic, 4);
if (err < 0) {
error("failed to enable SD4: %d\n", err);
return err;
}
err = as3722_sd_set_voltage(pmic, 4, 0x24);
if (err < 0) {
error("failed to set SD4 voltage: %d\n", err);
return err;
}
err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH |
AS3722_GPIO_INVERT);
if (err < 0) {
error("failed to configure GPIO#1 as output: %d\n", err);
return err;
}
err = as3722_gpio_direction_output(pmic, 2, 1);
if (err < 0) {
error("failed to set GPIO#2 high: %d\n", err);
return err;
}
/* Reset I210 Gigabit Ethernet Controller */
gpio_request(LAN_RESET_N, "LAN_RESET_N");
gpio_direction_output(LAN_RESET_N, 0);
/*
* Make sure we don't get any back feeding from LAN_WAKE_N resp.
* DEV_OFF_N
*/
gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N");
gpio_direction_output(TEGRA_GPIO(O, 5), 0);
gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N");
gpio_direction_output(TEGRA_GPIO(O, 6), 0);
/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
err = as3722_ldo_enable(pmic, 9);
if (err < 0) {
error("failed to enable LDO9: %d\n", err);
return err;
}
err = as3722_ldo_enable(pmic, 10);
if (err < 0) {
error("failed to enable LDO10: %d\n", err);
return err;
}
err = as3722_ldo_set_voltage(pmic, 9, 0x80);
if (err < 0) {
error("failed to set LDO9 voltage: %d\n", err);
return err;
}
err = as3722_ldo_set_voltage(pmic, 10, 0x80);
if (err < 0) {
error("failed to set LDO10 voltage: %d\n", err);
return err;
}
mdelay(100);
/* Make sure controller gets enabled by disabling DEV_OFF_N */
gpio_set_value(TEGRA_GPIO(O, 6), 1);
/* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */
err = as3722_ldo_set_voltage(pmic, 9, 0xff);
if (err < 0) {
error("failed to set LDO9 voltage: %d\n", err);
return err;
}
err = as3722_ldo_set_voltage(pmic, 10, 0xff);
if (err < 0) {
error("failed to set LDO10 voltage: %d\n", err);
return err;
}
mdelay(100);
gpio_set_value(LAN_RESET_N, 1);
#ifdef APALIS_TK1_PCIE_EVALBOARD_INIT
#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
/* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation
Board */
gpio_request(PEX_PERST_N, "PEX_PERST_N");
gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
gpio_direction_output(PEX_PERST_N, 0);
gpio_direction_output(RESET_MOCI_CTRL, 0);
/* Must be asserted for 100 ms after power and clocks are stable */
mdelay(100);
gpio_set_value(PEX_PERST_N, 1);
/* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until
900 us After PEX_PERST# De-assertion */
mdelay(1);
gpio_set_value(RESET_MOCI_CTRL, 1);
#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */
return 0;
}
#endif /* CONFIG_PCI_TEGRA */

117
board/toradex/apalis-tk1/as3722_init.c
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@ -0,0 +1,117 @@
/*
* Copyright (c) 2012-2016 Toradex, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include "as3722_init.h"
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
void tegra_i2c_ll_write_addr(uint addr, uint config)
{
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
writel(addr, &reg->cmd_addr0);
writel(config, &reg->cnfg);
}
void tegra_i2c_ll_write_data(uint data, uint config)
{
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
writel(data, &reg->cmd_data1);
writel(config, &reg->cnfg);
}
void pmic_enable_cpu_vdd(void)
{
debug("%s entry\n", __func__);
#ifdef AS3722_SD1VOLTAGE_DATA
/* Set up VDD_CORE, for boards where OTP is incorrect*/
debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
#endif
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
/*
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.0V, then enable the VDD regulator.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
/*
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.0V, then enable the VDD regulator.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
/*
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.2V, then enable the VDD regulator.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
/*
* Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
* First set it to value closest to 3.3V, then enable the regulator
*
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
/*
* Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
* First set it to bypass 3.3V straight thru, then enable the regulator
*
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
}

41
board/toradex/apalis-tk1/as3722_init.h
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/*
* Copyright (c) 2012-2016 Toradex, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* AS3722-PMIC-specific early init regs */
#define AS3722_I2C_ADDR 0x80
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
#define AS3722_SDCONTROL_REG 0x4D
#define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
#define AS3722_LDCONTROL_REG 0x4E
#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
#define AS3722_LDO1CONTROL_DATA (0x0200 | AS3722_LDCONTROL_REG)
#define AS3722_LDO1VOLTAGE_DATA (0x7F00 | AS3722_LDO1VOLTAGE_REG)
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
#define I2C_SEND_2_BYTES 0x0A02
void pmic_enable_cpu_vdd(void);

287
board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
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/*
* Copyright (c) 2016, Toradex, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PINMUX_CONFIG_APALIS_TK1_H_
#define _PINMUX_CONFIG_APALIS_TK1_H_
#define GPIO_INIT(_port, _gpio, _init) \
{ \
.gpio = TEGRA_GPIO(_port, _gpio), \
.init = TEGRA_GPIO_INIT_##_init, \
}
static const struct tegra_gpio_config apalis_tk1_gpio_inits[] = {
/* port, pin, init_val */
GPIO_INIT(A, 1, IN),
GPIO_INIT(B, 1, IN),
GPIO_INIT(C, 0, OUT0),
GPIO_INIT(I, 5, IN),
GPIO_INIT(I, 6, IN),
GPIO_INIT(J, 0, IN),
GPIO_INIT(J, 2, IN),
GPIO_INIT(K, 2, IN),
GPIO_INIT(K, 7, IN),
GPIO_INIT(N, 2, OUT1),
GPIO_INIT(N, 4, OUT1),
GPIO_INIT(N, 5, OUT1),
GPIO_INIT(N, 7, IN),
GPIO_INIT(O, 5, IN),
GPIO_INIT(Q, 0, OUT0), /* Shift_CTRL_OE[0] */
GPIO_INIT(Q, 1, OUT0), /* Shift_CTRL_OE[1] */
GPIO_INIT(Q, 2, OUT0), /* Shift_CTRL_OE[2] */
GPIO_INIT(Q, 4, OUT0), /* Shift_CTRL_OE[4] */
GPIO_INIT(Q, 5, OUT1), /* Shift_CTRL_Dir_Out[0] */
GPIO_INIT(Q, 6, OUT1), /* Shift_CTRL_Dir_Out[1] */
GPIO_INIT(Q, 7, OUT1), /* Shift_CTRL_Dir_Out[2] */
GPIO_INIT(R, 0, OUT0), /* Shift_CTRL_Dir_In[0] */
GPIO_INIT(R, 1, OUT0), /* Shift_CTRL_Dir_In[1] */
GPIO_INIT(R, 2, OUT0), /* Shift_CTRL_OE[3] */
GPIO_INIT(S, 3, OUT0), /* Shift_CTRL_Dir_In[2] */
GPIO_INIT(U, 4, OUT1),
GPIO_INIT(W, 3, IN),
GPIO_INIT(W, 5, IN),
GPIO_INIT(BB, 0, IN),
GPIO_INIT(BB, 3, OUT0),
GPIO_INIT(BB, 4, IN),
GPIO_INIT(BB, 5, OUT1),
GPIO_INIT(BB, 6, OUT0),
GPIO_INIT(CC, 5, IN),
GPIO_INIT(DD, 3, IN),
GPIO_INIT(EE, 3, IN),
GPIO_INIT(EE, 5, IN),
GPIO_INIT(FF, 1, IN),
};
#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
{ \
.pingrp = PMUX_PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.od = PMUX_PIN_OD_##_od, \
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
.lock = PMUX_PIN_LOCK_DEFAULT, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
static const struct pmux_pingrp_config apalis_tk1_pingrps[] = {
/* pingrp, mux, pull, tri, e_input, od, rcv_sel */
PINCFG(CLK_32K_OUT_PA0, SOC, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_CTS_N_PA1, GMI, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_FS_PA2, HDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_SCLK_PA3, HDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DIN_PA4, HDA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP2_DOUT_PA5, HDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PB0, UARTD, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PB1, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RTS_N_PC0, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG3, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG4, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PG7, SPI4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH2, PWM2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH3, PWM3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PH7, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PI5, RSVD2, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
PINCFG(PI6, RSVD1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ0, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
PINCFG(PJ2, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK2, RSVD1, UP, TRISTATE, INPUT, ENABLE, DEFAULT),
PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PK4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SPDIF_IN_PK6, SPDIF, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PK7, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_DOUT_PN2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN0_PN4, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(USB_VBUS_EN1_PN5, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
PINCFG(HDMI_INT_PN7, RSVD1, DOWN, TRISTATE, INPUT, DEFAULT, NORMAL),
PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA4_PO5, ULPI, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL0_PQ0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL1_PQ1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL2_PQ2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL4_PQ4, KBC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL5_PQ5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL6_PQ6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_COL7_PQ7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW4_PR4, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW9_PS1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW10_PS2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW12_PS4, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW15_PS7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(KB_ROW17_PT1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU1, UARTA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PU2, UARTA, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PU6, PWM3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PV0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CD_N_PV2, RSVD3, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_WP_N_PV3, SDMMC1, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DDC_SCL_PV4, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DDC_SDA_PV5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W2_AUD_PW2, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_W3_AUD_PW3, SPI6, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_OUT_PW5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X1_AUD_PX1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X4_AUD_PX4, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X5_AUD_PX5, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X6_AUD_PX6, SPI2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(GPIO_X7_AUD_PX7, SPI2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PBB0, VGP6, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB4, VGP4, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PBB5, VGP5, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L0_RST_N_PDD1, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_WAKE_N_PDD3, RSVD2, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L1_RST_N_PDD5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
/*
* Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka not
* tristated and input driver enabled as well as it features some magic
* properties even though the external loopback is disabled and the internal
* loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
* being set to 0xfffd according to the TRM!
*/
PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(SDMMC3_CLK_LB_IN_PEE5, RSVD2, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(DP_HPD_PFF0, DP, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(PFF2, RSVD2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
PINCFG(PWR_INT_N, PMI, UP, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
PINCFG(OWR, RSVD2, NORMAL, TRISTATE, OUTPUT, DEFAULT, NORMAL),
PINCFG(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT, DEFAULT, DEFAULT),
PINCFG(JTAG_RTCK, RTCK, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
};
#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
.lpmd = PMUX_LPMD_##_lpmd, \
.schmt = PMUX_SCHMT_##_schmt, \
.hsm = PMUX_HSM_##_hsm, \
}
static const struct pmux_drvgrp_config apalis_tk1_drvgrps[] = {
};
#endif /* PINMUX_CONFIG_APALIS_TK1_H */

47
configs/apalis-tk1_defconfig
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@ -0,0 +1,47 @@
CONFIG_ARM=y
CONFIG_TEGRA=y
CONFIG_TEGRA124=y
CONFIG_TARGET_APALIS_TK1=y
CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis"
CONFIG_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOOTDELAY=1
CONFIG_CONSOLE_MUX=y
CONFIG_SYS_STDIO_DEREGISTER=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="Apalis TK1 # "
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
CONFIG_CMD_USB=y
CONFIG_CMD_DFU=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
# CONFIG_DM_MMC_OPS is not set
CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCI_TEGRA=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Toradex"
CONFIG_G_DNL_VENDOR_NUM=0x1b67
CONFIG_G_DNL_PRODUCT_NUM=0xffff
CONFIG_OF_LIBFDT_OVERLAY=y

11
drivers/mmc/Kconfig
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@ -367,6 +367,17 @@ config MMC_SUNXI
endif
config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
bool "Disable external clock loopback"
depends on MMC_SDHCI_TEGRA && TEGRA124
help
Disable the external clock loopback and use the internal one on SDMMC3
as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits
being set to 0xfffd according to the TRM.
TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
approach once proper kernel integration made it mainline.
endmenu
config SYS_FSL_ERRATUM_ESDHC111

16
drivers/mmc/tegra_mmc.c
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@ -513,6 +513,22 @@ static int tegra_mmc_init(struct mmc *mmc)
tegra_mmc_reset(priv, mmc);
#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
/*
* Disable the external clock loopback and use the internal one on
* SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
* bits being set to 0xfffd according to the TRM.
*
* TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
* approach once proper kernel integration made it mainline.
*/
if (priv->reg == (void *)0x700b0400) {
mask = readl(&priv->reg->venmiscctl);
mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
writel(mask, &priv->reg->venmiscctl);
}
#endif
priv->version = readw(&priv->reg->hcver);
debug("host version = %x\n", priv->version);

176
include/configs/apalis-tk1.h
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@ -0,0 +1,176 @@
/*
* Copyright (c) 2017 Toradex, Inc.
*
* Configuration settings for the Toradex Apalis TK1 modules.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <linux/sizes.h>
/* enable PMIC */
#define CONFIG_AS3722_POWER
#include "tegra124-common.h"
#define CONFIG_ARCH_MISC_INIT
/* High-level configuration options */
#define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
/* SD/MMC support */
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
/* Environment in eMMC, before config block at the end of 1st "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \
CONFIG_TDX_CFG_BLOCK_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1
/* USB host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
/* PCI host support */
#undef CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI
/* PCI networking support */
#define CONFIG_E1000_NO_NVM
/* General networking support */
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_TFTP_TSIZE
/* Miscellaneous commands */
#define CONFIG_FAT_WRITE
#undef CONFIG_IPADDR
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#undef CONFIG_SERVERIP
#define CONFIG_SERVERIP 192.168.10.1
#define CONFIG_BOOTCOMMAND \
"run emmcboot; setenv fdtfile ${soc}-apalis-${fdt_board}.dtb && " \
"run distro_bootcmd"
#define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \
"boot part 0 1 mmcpart 0; " \
"rootfs part 0 2 mmcpart 0; " \
"uImage fat 0 1 mmcpart 0; " \
"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
#define EMMC_BOOTCMD \
"emmcargs=ip=off root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait\0" \
"emmcboot=run setup; setenv bootargs ${defargs} ${emmcargs} " \
"${setupargs} ${vidargs}; echo Booting from internal eMMC " \
"chip...; run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"bootm ${kernel_addr_r} - ${dtbparam}\0" \
"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
"${soc}-apalis-${fdt_board}.dtb && " \
"setenv dtbparam ${fdt_addr_r}\0"
#define NFS_BOOTCMD \
"nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \
"nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \
"${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
"run nfsdtbload; dhcp ${kernel_addr_r} " \
"&& run fdt_fixup && bootm ${kernel_addr_r} - ${dtbparam}\0" \
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \
"${soc}-apalis-${fdt_board}.dtb " \
"&& setenv dtbparam ${fdt_addr_r}\0"
#define SD_BOOTCMD \
"sdargs=ip=off root=/dev/mmcblk1p2 rw rootfstype=ext3 rootwait\0" \
"sdboot=run setup; setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
"${vidargs}; echo Booting from SD card in 8bit slot...; " \
"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"bootm ${kernel_addr_r} - ${dtbparam}\0" \
"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
"${soc}-apalis-${fdt_board}.dtb " \
"&& setenv dtbparam ${fdt_addr_r}\0"
#define USB_BOOTCMD \
"usbargs=ip=off root=/dev/sda2 rw rootfstype=ext3 rootwait\0" \
"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"bootm ${kernel_addr_r} - ${dtbparam}\0" \
"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
"${soc}-apalis-${fdt_board}.dtb " \
"&& setenv dtbparam ${fdt_addr_r}\0"
#define BOARD_EXTRA_ENV_SETTINGS \
"boot_file=uImage\0" \
"console=ttyS0\0" \
"defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
"usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0\0" \
"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
EMMC_BOOTCMD \
"fdt_board=eval\0" \
"fdt_fixup=;\0" \
NFS_BOOTCMD \
SD_BOOTCMD \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \
"setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \
"|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1 " \
"${loadaddr} flash_blk.img && " \
"source ${loadaddr}\0" \
"setup=setenv setupargs igb_mac=${ethaddr} " \
"consoleblank=0 no_console_suspend=1 console=tty1 " \
"console=${console},${baudrate}n8 debug_uartport=lsport,0 " \
"${memargs}\0" \
"setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \
"setusbupdate=usb start && setenv interface usb; setenv drive 0; " \
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
"source ${loadaddr}\0" \
USB_BOOTCMD \
"vidargs=video=tegrafb0:640x480-16@60 fbcon=map:1\0"
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
#define CONFIG_SYS_CBSIZE 1024
/* Increase arguments buffer size */
#undef CONFIG_SYS_BARGSIZE
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Increase print buffer size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Increase maximum number of arguments */
#undef CONFIG_SYS_MAXARGS
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_CMD_TIME
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#include "tegra-common-usb-gadget.h"
#include "tegra-common-post.h"
/* Reserve top 1M for secure RAM */
#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000
#endif /* __CONFIG_H */
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