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@ -834,7 +834,7 @@ spd_init(unsigned char i2c_address, unsigned int ddr_num, |
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debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); |
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debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); |
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#endif |
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#endif |
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asm("sync;isync"); |
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asm volatile("sync;isync"); |
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udelay(500); |
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udelay(500); |
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/*
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/*
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@ -1032,7 +1032,7 @@ unsigned int enable_ddr(unsigned int ddr_num) |
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*/ |
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*/ |
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if (config == 0x02) { |
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if (config == 0x02) { |
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ddr->err_disable = 0x00000000; |
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ddr->err_disable = 0x00000000; |
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asm("sync;isync;"); |
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asm volatile("sync;isync;"); |
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ddr->err_sbe = 0x00ff0000; |
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ddr->err_sbe = 0x00ff0000; |
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ddr->err_int_en = 0x0000000d; |
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ddr->err_int_en = 0x0000000d; |
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sdram_cfg_1 |= 0x20000000; /* ECC_EN */ |
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sdram_cfg_1 |= 0x20000000; /* ECC_EN */ |
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@ -1325,7 +1325,7 @@ ddr_enable_ecc(unsigned int dram_size) |
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*/ |
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*/ |
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debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); |
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debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); |
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ddr1->err_disable = 0x00000000; |
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ddr1->err_disable = 0x00000000; |
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asm("sync;isync;msync"); |
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asm volatile("sync;isync"); |
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debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); |
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debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable); |
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} |
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} |
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