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@ -105,17 +105,16 @@ static struct pci_config_table pci_integrator_config_table[] = { |
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}; |
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#endif |
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// V3 access routines
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/* V3 access routines */ |
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#define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v)) |
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#define _V3Read16(o) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o))) |
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#define _V3Write32(o,v) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned int)(v)) |
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#define _V3Read32(o) (*(volatile unsigned int *)(PCI_V3_BASE + (unsigned int)(o))) |
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// Compute address necessary to access PCI config space for the given
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// bus and device.
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#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \ |
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({ \
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/* Compute address necessary to access PCI config space for the given */ |
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/* bus and device. */ |
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#define PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) ({ \ |
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unsigned int __address, __devicebit; \
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unsigned short __mapaddress; \
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unsigned int __dev = PCI_DEV (__devfn); /* FIXME to check!! (slot?) */ \
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@ -147,13 +146,11 @@ static struct pci_config_table pci_integrator_config_table[] = { |
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__address |= __offset & 0xFF; /* bits 7..0 = register number */ \
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} \
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_V3Write16 (V3_LB_MAP1, __mapaddress); \
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\
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__address; \
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}) |
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// _V3OpenConfigWindow - open V3 configuration window
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#define _V3OpenConfigWindow() \ |
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{ \
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/* _V3OpenConfigWindow - open V3 configuration window */ |
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#define _V3OpenConfigWindow() { \ |
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/* Set up base0 to see all 512Mbytes of memory space (not */ \
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/* prefetchable), this frees up base1 for re-use by configuration*/ \
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/* memory */ \
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@ -167,9 +164,8 @@ static struct pci_config_table pci_integrator_config_table[] = { |
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0x40 | V3_LB_BASE_M_ENABLE)); \
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} |
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// _V3CloseConfigWindow - close V3 configuration window
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#define _V3CloseConfigWindow() \ |
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{ \
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/* _V3CloseConfigWindow - close V3 configuration window */ |
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#define _V3CloseConfigWindow() { \ |
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/* Reassign base1 for use by prefetchable PCI memory */ \
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_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + 0x10000000) & 0xFFF00000) \
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| 0x84 | V3_LB_BASE_M_ENABLE)); \
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@ -182,69 +178,88 @@ static struct pci_config_table pci_integrator_config_table[] = { |
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0x80 | V3_LB_BASE_M_ENABLE)); \
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} |
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static int pci_integrator_read_byte (struct pci_controller *hose, pci_dev_t dev, |
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int offset, unsigned char *val) |
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{ |
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_V3OpenConfigWindow (); |
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*val = *(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset); |
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*val = *(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), |
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PCI_FUNC (dev), |
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offset); |
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_V3CloseConfigWindow (); |
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return 0; |
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} |
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static int pci_integrator_read__word(struct pci_controller *hose, pci_dev_t dev, |
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int offset, unsigned short *val) |
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static int pci_integrator_read__word (struct pci_controller *hose, |
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pci_dev_t dev, int offset, |
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unsigned short *val) |
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{ |
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_V3OpenConfigWindow (); |
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*val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset); |
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*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), |
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PCI_FUNC (dev), |
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offset); |
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_V3CloseConfigWindow (); |
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return 0; |
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} |
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static int pci_integrator_read_dword(struct pci_controller *hose, pci_dev_t dev, |
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int offset, unsigned int *val) |
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static int pci_integrator_read_dword (struct pci_controller *hose, |
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pci_dev_t dev, int offset, |
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unsigned int *val) |
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{ |
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_V3OpenConfigWindow (); |
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*val = *(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset); |
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*val |= (*(volatile unsigned int *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset+2))) << 16; |
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*val = *(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), |
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PCI_FUNC (dev), |
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offset); |
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*val |= (*(volatile unsigned int *) |
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PCI_CONFIG_ADDRESS (PCI_BUS (dev), PCI_FUNC (dev), |
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(offset + 2))) << 16; |
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_V3CloseConfigWindow (); |
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return 0; |
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} |
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static int pci_integrator_write_byte(struct pci_controller *hose, pci_dev_t dev, |
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int offset, unsigned char val) |
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static int pci_integrator_write_byte (struct pci_controller *hose, |
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pci_dev_t dev, int offset, |
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unsigned char val) |
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{ |
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_V3OpenConfigWindow (); |
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*(volatile unsigned char *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val; |
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*(volatile unsigned char *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), |
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PCI_FUNC (dev), |
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offset) = val; |
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_V3CloseConfigWindow (); |
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return 0; |
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} |
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static int pci_integrator_write_word(struct pci_controller *hose, pci_dev_t dev, |
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int offset,unsigned short val) |
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static int pci_integrator_write_word (struct pci_controller *hose, |
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pci_dev_t dev, int offset, |
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unsigned short val) |
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{ |
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_V3OpenConfigWindow (); |
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*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = val; |
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*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), |
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PCI_FUNC (dev), |
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offset) = val; |
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_V3CloseConfigWindow (); |
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return 0; |
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} |
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static int pci_integrator_write_dword(struct pci_controller *hose, pci_dev_t dev, |
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int offset, unsigned int val) |
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static int pci_integrator_write_dword (struct pci_controller *hose, |
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pci_dev_t dev, int offset, |
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unsigned int val) |
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{ |
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_V3OpenConfigWindow (); |
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*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), offset) = (val & 0xFFFF); |
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*(volatile unsigned short *)PCI_CONFIG_ADDRESS(PCI_BUS(dev), PCI_FUNC(dev), (offset + 2)) = ((val >> 16) & 0xFFFF); |
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*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), |
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PCI_FUNC (dev), |
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offset) = (val & 0xFFFF); |
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*(volatile unsigned short *) PCI_CONFIG_ADDRESS (PCI_BUS (dev), |
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PCI_FUNC (dev), |
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(offset + 2)) = ((val >> 16) & 0xFFFF); |
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_V3CloseConfigWindow (); |
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return 0; |
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} |
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/******************************
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* PCI initialisation |
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******************************/ |
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@ -271,17 +286,21 @@ void pci_init_board(void) |
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/* Now write the Base I/O Address Word to V3_BASE + 0x6C */ |
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*(volatile unsigned short *)(V3_BASE + V3_LB_IO_BASE) = (unsigned short)(V3_BASE >> 16); |
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*(volatile unsigned short *) (V3_BASE + V3_LB_IO_BASE) = |
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(unsigned short) (V3_BASE >> 16); |
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do { |
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*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) = 0xAA; |
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*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) = 0x55; |
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} while (*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA) != 0xAA || |
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*(volatile unsigned char *)(V3_BASE + V3_MAIL_DATA + 4) != 0x55); |
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*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + 4) = |
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0x55; |
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} while (*(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA) != 0xAA |
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|| *(volatile unsigned char *) (V3_BASE + V3_MAIL_DATA + |
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4) != 0x55); |
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/* Make sure that V3 register access is not locked, if it is, unlock it */ |
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if ((*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) & V3_SYSTEM_M_LOCK) |
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if ((*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) & |
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V3_SYSTEM_M_LOCK) |
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== V3_SYSTEM_M_LOCK) |
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*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = 0xA05F; |
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@ -293,11 +312,13 @@ void pci_init_board(void) |
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/* Clear RST_OUT to 0; keep the PCI bus in reset until we've finished */ |
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*(volatile unsigned short *)(V3_BASE + V3_SYSTEM) &= ~V3_SYSTEM_M_RST_OUT; |
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*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) &= |
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~V3_SYSTEM_M_RST_OUT; |
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/* Make all accesses from PCI space retry until we're ready for them */ |
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*(volatile unsigned short *)(V3_BASE + V3_PCI_CFG) |= V3_PCI_CFG_M_RETRY_EN; |
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*(volatile unsigned short *) (V3_BASE + V3_PCI_CFG) |= |
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V3_PCI_CFG_M_RETRY_EN; |
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/* Set up any V3 PCI Configuration Registers that we absolutely have to */ |
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/* LB_CFG controls Local Bus protocol. */ |
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@ -313,24 +334,27 @@ void pci_init_board(void) |
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/* PCI_MAP0 controls where the PCI to CPU memory window is on Local Bus */ |
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*(volatile unsigned int *)(V3_BASE + V3_PCI_MAP0) = (INTEGRATOR_BOOT_ROM_BASE) | |
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(V3_PCI_MAP_M_ADR_SIZE_512M | |
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*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP0) = |
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(INTEGRATOR_BOOT_ROM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_512M | |
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V3_PCI_MAP_M_REG_EN | |
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V3_PCI_MAP_M_ENABLE); |
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/* PCI_BASE0 is the PCI address of the start of the window */ |
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*(volatile unsigned int *)(V3_BASE + V3_PCI_BASE0) = INTEGRATOR_BOOT_ROM_BASE; |
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*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE0) = |
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INTEGRATOR_BOOT_ROM_BASE; |
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/* PCI_MAP1 is LOCAL address of the start of the window */ |
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*(volatile unsigned int *)(V3_BASE + V3_PCI_MAP1) = (INTEGRATOR_HDR0_SDRAM_BASE) | |
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(V3_PCI_MAP_M_ADR_SIZE_1024M | V3_PCI_MAP_M_REG_EN | |
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*(volatile unsigned int *) (V3_BASE + V3_PCI_MAP1) = |
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(INTEGRATOR_HDR0_SDRAM_BASE) | (V3_PCI_MAP_M_ADR_SIZE_1024M | |
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V3_PCI_MAP_M_REG_EN | |
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V3_PCI_MAP_M_ENABLE); |
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/* PCI_BASE1 is the PCI address of the start of the window */ |
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*(volatile unsigned int *)(V3_BASE + V3_PCI_BASE1) = INTEGRATOR_HDR0_SDRAM_BASE; |
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*(volatile unsigned int *) (V3_BASE + V3_PCI_BASE1) = |
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INTEGRATOR_HDR0_SDRAM_BASE; |
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/* Set up the windows from local bus memory into PCI configuration, */ |
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/* I/O and Memory. */ |
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@ -371,17 +395,20 @@ void pci_init_board(void) |
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/* now we can allow in PCI MEMORY accesses */ |
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*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD) = |
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(*(volatile unsigned short *)(V3_BASE + V3_PCI_CMD)) | V3_COMMAND_M_MEM_EN; |
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(*(volatile unsigned short *) (V3_BASE + V3_PCI_CMD)) | |
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V3_COMMAND_M_MEM_EN; |
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/* Set RST_OUT to take the PCI bus is out of reset, PCI devices can */ |
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/* initialise and lock the V3 system register so that no one else */ |
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/* can play with it */ |
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*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = |
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(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_RST_OUT; |
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(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | |
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V3_SYSTEM_M_RST_OUT; |
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*(volatile unsigned short *) (V3_BASE + V3_SYSTEM) = |
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(*(volatile unsigned short *)(V3_BASE + V3_SYSTEM)) | V3_SYSTEM_M_LOCK; |
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(*(volatile unsigned short *) (V3_BASE + V3_SYSTEM)) | |
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V3_SYSTEM_M_LOCK; |
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/*
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* Register the hose |
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@ -396,26 +423,22 @@ void pci_init_board(void) |
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/* PCI Memory - config space */ |
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pci_set_region (hose->regions + 1, |
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0x00000000, 0x62000000, 0x01000000, |
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PCI_REGION_MEM); |
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0x00000000, 0x62000000, 0x01000000, PCI_REGION_MEM); |
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/* PCI V3 regs */ |
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pci_set_region (hose->regions + 2, |
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0x00000000, 0x61000000, 0x00080000, |
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PCI_REGION_MEM); |
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0x00000000, 0x61000000, 0x00080000, PCI_REGION_MEM); |
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/* PCI I/O space */ |
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pci_set_region (hose->regions + 3, |
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0x00000000, 0x60000000, 0x00010000, |
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PCI_REGION_IO); |
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0x00000000, 0x60000000, 0x00010000, PCI_REGION_IO); |
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pci_set_ops (hose, |
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pci_integrator_read_byte, |
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pci_integrator_read__word, |
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pci_integrator_read_dword, |
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pci_integrator_write_byte, |
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pci_integrator_write_word, |
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pci_integrator_write_dword); |
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pci_integrator_write_word, pci_integrator_write_dword); |
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hose->region_count = 4; |
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@ -452,4 +475,3 @@ int dram_init (void) |
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{ |
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return 0; |
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} |
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