Add device tree for T2080QDS board and enable CONFIG_OF_CONTROL so that device tree can be compiled. Update board README for device tree usage. Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>lime2-spi
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// SPDX-License-Identifier: GPL-2.0+ OR X11 |
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/* |
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* e6500 Power ISA Device Tree Source (include) |
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* |
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* Copyright 2013 Freescale Semiconductor Inc. |
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* Copyright 2018 NXP |
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*/ |
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/ { |
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cpus { |
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power-isa-version = "2.06"; |
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power-isa-b; // Base |
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power-isa-e; // Embedded |
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power-isa-atb; // Alternate Time Base |
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power-isa-cs; // Cache Specification |
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power-isa-ds; // Decorated Storage |
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power-isa-e.ed; // Embedded.Enhanced Debug |
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power-isa-e.pd; // Embedded.External PID |
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power-isa-e.hv; // Embedded.Hypervisor |
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power-isa-e.le; // Embedded.Little-Endian |
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power-isa-e.pm; // Embedded.Performance Monitor |
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power-isa-e.pc; // Embedded.Processor Control |
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power-isa-ecl; // Embedded Cache Locking |
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power-isa-exp; // External Proxy |
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power-isa-fp; // Floating Point |
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power-isa-fp.r; // Floating Point.Record |
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power-isa-mmc; // Memory Coherence |
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power-isa-scpm; // Store Conditional Page Mobility |
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power-isa-wt; // Wait |
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power-isa-64; // 64-bit |
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power-isa-e.pt; // Embedded.Page Table |
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power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT |
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power-isa-e.em; // Embedded Multi-Threading |
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power-isa-v; // Vector (AltiVec) |
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fsl,eref-er; // Enhanced Reservations |
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fsl,eref-deo; // Data Cache Extended Operations |
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mmu-type = "power-embedded"; |
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}; |
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}; |
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// SPDX-License-Identifier: GPL-2.0+ OR X11 |
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/* |
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* T2080/T2081 Silicon/SoC Device Tree Source (pre include) |
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* |
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* Copyright 2013 Freescale Semiconductor Inc. |
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* Copyright 2018 NXP |
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*/ |
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/dts-v1/; |
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/include/ "e6500_power_isa.dtsi" |
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/ { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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interrupt-parent = <&mpic>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: PowerPC,e6500@0 { |
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device_type = "cpu"; |
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reg = <0 1>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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cpu1: PowerPC,e6500@2 { |
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device_type = "cpu"; |
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reg = <2 3>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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cpu2: PowerPC,e6500@4 { |
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device_type = "cpu"; |
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reg = <4 5>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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cpu3: PowerPC,e6500@6 { |
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device_type = "cpu"; |
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reg = <6 7>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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}; |
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soc: soc@ffe000000 { |
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>; |
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reg = <0xf 0xfe000000 0 0x00001000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "soc"; |
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compatible = "simple-bus"; |
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mpic: pic@40000 { |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <4>; |
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reg = <0x40000 0x40000>; |
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compatible = "fsl,mpic"; |
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device_type = "open-pic"; |
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clock-frequency = <0x0>; |
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}; |
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}; |
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}; |
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// SPDX-License-Identifier: GPL-2.0+ OR X11 |
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/* |
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* T2080QDS Device Tree Source |
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* |
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* Copyright 2013 - 2015 Freescale Semiconductor Inc. |
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* Copyright 2018 NXP |
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*/ |
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/include/ "t2080.dtsi" |
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/ { |
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model = "fsl,T2080QDS"; |
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compatible = "fsl,T2080QDS"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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interrupt-parent = <&mpic>; |
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}; |
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